CN110460499A - The method of ethernet signal linear speed acquisition monitoring and analysis - Google Patents
The method of ethernet signal linear speed acquisition monitoring and analysis Download PDFInfo
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- CN110460499A CN110460499A CN201910787327.0A CN201910787327A CN110460499A CN 110460499 A CN110460499 A CN 110460499A CN 201910787327 A CN201910787327 A CN 201910787327A CN 110460499 A CN110460499 A CN 110460499A
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- ethernet
- programmable gate
- field programmable
- gate array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
- H04L43/0894—Packet rate
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Environmental & Geological Engineering (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention belongs to Ethernet communication technology fields, disclose the method for ethernet signal linear speed acquisition monitoring and analysis, it include: insertion connection field programmable gate array in the MII bus between MAC and PHY, so that MAC is connect by MII bus with field programmable gate array, field programmable gate array is connect by MII bus with PHY, and field programmable gate array has ethernet port, Consol mouthfuls and storage unit.The present invention realizes the ability effectively improved to ethernet device diagnosis, reduces maintenance cost.
Description
Technical field
The invention belongs to Ethernet communication technology field more particularly to the sides of ethernet signal linear speed acquisition monitoring and analysis
Method.
Background technique
Ethernet device is widely used in industry spot, and equipment job site environment is often more complicated and harsh, once
Equipment breaks down, and field technician is difficult effectively to be analyzed and accurate judgement, will cause high maintenance cost.
Summary of the invention
The method for being designed to provide ethernet signal linear speed acquisition monitoring and analysis of the embodiment of the present invention, can be effective
The ability diagnosed to ethernet device is improved, maintenance cost is reduced.
The embodiments of the present invention are implemented as follows:
The method of ethernet signal linear speed acquisition monitoring and analysis, comprising:
Insertion connection field programmable gate array in MII bus between MAC and PHY, so that MAC passes through MII bus
It is connect with field programmable gate array, field programmable gate array is connect by MII bus with PHY, field programmable gate array
Have the function of that ethernet mac MII interface, ethernet PHY function MII interface, ethernet PHY functional interface and serial port function connect
Mouthful, field programmable gate array has ethernet port, Consol mouthfuls and storage unit；
Field programmable gate array is read out, monitors and analyzes to the data packet transmitted in MII bus, realizes Ethernet
Linear speed acquisition, monitoring and the analysis of signal store the data packet, monitoring and analysis result by the storage unit；
Field programmable gate array externally provides the data packet, monitoring by its ethernet port and Consol mouthfuls and divides
Analyse result.
Wherein, the MII bus can be RMII bus, RGMII bus, SGMII bus or QSGMII bus.
Wherein, the storage unit is memory ram item, Flash, standard machinery hard disk or solid state hard disk.
The embodiment of the present invention is inside embedded network equipment, by the interface between MAC and PHY, i.e., MAC and PHY it
Between interface on be inserted directly into connection FPGA, realize ethernet signal linear speed acquisition, monitoring and analysis.Net is externally provided simultaneously
Network interface and serial ports are checked and are judged to equipment fault for field technician.The present invention can be effectively improved to device diagnostic
Ability, reduce maintenance cost.
Detailed description of the invention
Fig. 1 is the functional block diagram for the method that the present invention realizes ethernet signal linear speed acquisition monitoring and analysis.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Specific implementation of the invention is described in detail below in conjunction with specific embodiment:
As shown in Figure 1, the method for ethernet signal linear speed acquisition monitoring and analysis, comprising:
Insertion connection field programmable gate array in MII bus between MAC and PHY, so that MAC passes through MII bus
It is connect with field programmable gate array, field programmable gate array is connect by MII bus with PHY, field programmable gate array
Have the function of that ethernet mac MII interface, ethernet PHY function MII interface, ethernet PHY functional interface and serial port function connect
Mouthful, field programmable gate array has ethernet port, Consol mouthfuls and storage unit；
Field programmable gate array is read out, monitors and analyzes to the data packet transmitted in MII bus, realizes Ethernet
Linear speed acquisition, monitoring and the analysis of signal store the data packet, monitoring and analysis result by the storage unit；
Field programmable gate array externally provides the data packet, monitoring by its ethernet port and Consol mouthfuls and divides
Analyse result.
It about field programmable gate array, is analyzed according to function logic, is to realize four kinds of functional interfaces, ethernet mac
Function MII interface, ethernet PHY function MII interface, ethernet PHY functional interface and serial port function interface.These realization sides
Method can program field programmable gate array and realize.Finally, company of the field programmable gate array realization ethernet mac to PHY
It connects, the connection of PHY to MAC, field programmable gate array is serially connected between MAC and PHY by bus, and PHY functional interface is straight
A network interface RJ45 in succession；Serial interface is connected to serial ports input and output part.Thus as shown in Figure 1, MAC is sent to the data of PHY,
The end PHY can be just reached after field programmable gate array is handled, equally, PHY is sent to the data of MAC by field programmable gate
The end MAC can be just reached after ARRAY PROCESSING, field programmable gate array realization is sent to the data of PHY to MAC and PHY is sent to MAC's
Reading, processing, monitoring and the analysis of data.
The implementation that the present invention uses is as shown in Figure 1:
(1) MAC layer and PHY layer pass through MII interface communication, connection FPGA are inserted directly into MII bus, FPGA is to data packet
Be read out, analyze, under the premise of not influencing between ethernet port data storage forwarding linear speed acquisition, monitoring, analysis and
Store Ethernet data bag.
(2) FPGA mounts storage unit, realizes processing and storage to network packet.
(3) FPGA externally provides ethernet port and Consol mouthfuls, and FPGA is acquired ethernet signal, monitors and divides
Analysis facilitates field technician to pass through PC to failure and check and judge.
(4) it is forwarded between ethernet port by the storage that MAC carries out Ethernet data bag, these Ethernet data bags
It is acquired and is read by FPGA to whole linear speeds, storage unit stores these data packets.
The present invention is that connection FPGA is inserted directly on interface between MAC layer and PHY layer, and FPGA is to Ethernet data bag
It is read out and handles, realize the linear speed acquisition of ethernet signal, monitoring and analysis；Ethernet data envelope curve is realized in the present invention
The data storage forwarding between ethernet port is not influenced while speed acquisition, monitoring and analysis and is not take up Ethernet resource；
Interface between the MAC and PHY can be MII bus, can also be RMII bus, RGMII bus, SGMII bus,
QSGMII bus etc., but it is not limited to above several buses；FPGA stores collected ethernet signal by storage unit, deposits
Storage unit can be memory ram item, can also be Flash, standard machinery hard disk or solid state hard disk.
Technical term explanation in the present invention:
MAC:Media Access Control, that is, media access control；
PHY:Port Physical Layer, that is, port physical layer；
MII:Media Independent Interface, that is, Media Independent Interface；
FPGA:Field Programmable Gate Array, that is, field programmable gate array；
GMII (Gigabit MII): GMII is 8bit parallel synchronous transceiver interface, using 8 interface data, work clock
125MHz, therefore transmission rate is up to 1000Mbps.The 10/100Mbps working method of compatible MII defined simultaneously；
The gmii interface that RGMII simplifies is known as RGMII, GMII and RGMII and is all made of 8 bit data interfaces, work clock
125MHz, therefore transmission rate is up to 1000Mbps；
RMII:Reduced Media Independant Interface simplify the media independent interface, is the ether of standard
One of network interface has less I/O to transmit than MII；
SGMII--Serial Gigabit Media Independent Interface, SGMII are between PHY and MAC
Interface, similar with GMII and RGMII, only GMII and RGMII is parallel, and is needed with Lu Shizhong, PCB layout
It is relatively cumbersome, and be not suitable with backboard application, and SGMII be it is serial, do not need to provide other clock, MAC and PHY are needed
CDR is wanted to go recovered clock.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to restrict the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (3)
1. the method for ethernet signal linear speed acquisition monitoring and analysis characterized by comprising
Insertion connection field programmable gate array in MII bus between MAC and PHY, so that MAC is by MII bus and now
Field programmable gate array connection, field programmable gate array are connect by MII bus with PHY, and field programmable gate array has
Ethernet mac function MII interface, ethernet PHY function MII interface, ethernet PHY functional interface and serial port function interface,
Field programmable gate array has ethernet port, Consol mouthfuls and storage unit；
Field programmable gate array is read out, monitors and analyzes to the data packet transmitted in MII bus, realizes ethernet signal
Linear speed acquisition, monitoring and analysis, pass through the storage unit and store the data packet, monitoring and analysis result；
Field programmable gate array externally provides the data packet, monitoring and analysis knot by its ethernet port and Consol mouthfuls
Fruit.
2. the method for the acquisition of ethernet signal linear speed monitoring and analysis according to claim 1, it is characterised in that: described
MII bus can be RMII bus, RGMII bus, SGMII bus or QSGMII bus.
3. the method for the acquisition of ethernet signal linear speed monitoring and analysis according to claim 1, it is characterised in that: described to deposit
Storage unit is memory ram item, Flash, standard machinery hard disk or solid state hard disk.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910787327.0A CN110460499A (en) | 2019-08-22 | 2019-08-22 | The method of ethernet signal linear speed acquisition monitoring and analysis |
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| CN201910787327.0A CN110460499A (en) | 2019-08-22 | 2019-08-22 | The method of ethernet signal linear speed acquisition monitoring and analysis |
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| CN110460499A true CN110460499A (en) | 2019-11-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111030831A (en) * | 2019-12-10 | 2020-04-17 | 深圳震有科技股份有限公司 | Network port linear speed packet capturing device and method |
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| CN204089874U (en) * | 2014-09-12 | 2015-01-07 | 国家电网公司 | A kind of switch supporting packet storage |
| CN104702354A (en) * | 2015-03-16 | 2015-06-10 | 毕节供电局 | FPGA-based (field programmable gate array-based) PTN (packet transport network) equipment time delay monitoring device and method |
| CN205647557U (en) * | 2016-05-19 | 2016-10-12 | 龙芯中科技术有限公司 | Ethernet interface circuit and network equipment |
| CN206442403U (en) * | 2016-12-21 | 2017-08-25 | 淮北师范大学 | A kind of vehicle communication experiment porch |
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2019
- 2019-08-22 CN CN201910787327.0A patent/CN110460499A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103210609A (en) * | 2010-11-16 | 2013-07-17 | Abb研究有限公司 | Electronic device for communication in a data network including a protective circuit for identifying unwanted data |
| CN204089874U (en) * | 2014-09-12 | 2015-01-07 | 国家电网公司 | A kind of switch supporting packet storage |
| CN104702354A (en) * | 2015-03-16 | 2015-06-10 | 毕节供电局 | FPGA-based (field programmable gate array-based) PTN (packet transport network) equipment time delay monitoring device and method |
| CN205647557U (en) * | 2016-05-19 | 2016-10-12 | 龙芯中科技术有限公司 | Ethernet interface circuit and network equipment |
| CN206442403U (en) * | 2016-12-21 | 2017-08-25 | 淮北师范大学 | A kind of vehicle communication experiment porch |
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| CN111030831A (en) * | 2019-12-10 | 2020-04-17 | 深圳震有科技股份有限公司 | Network port linear speed packet capturing device and method |
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Application publication date: 20191115 |