CN204088293U - Semiconductor chip package - Google Patents
Semiconductor chip package Download PDFInfo
- Publication number
- CN204088293U CN204088293U CN201420583226.4U CN201420583226U CN204088293U CN 204088293 U CN204088293 U CN 204088293U CN 201420583226 U CN201420583226 U CN 201420583226U CN 204088293 U CN204088293 U CN 204088293U
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- pptc
- substrate
- semiconductor chip
- chip package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 101000669528 Homo sapiens Tachykinin-4 Proteins 0.000 claims abstract description 47
- OKUGPJPKMAEJOE-UHFFFAOYSA-N S-propyl dipropylcarbamothioate Chemical compound CCCSC(=O)N(CCC)CCC OKUGPJPKMAEJOE-UHFFFAOYSA-N 0.000 claims abstract description 47
- 102100039365 Tachykinin-4 Human genes 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 29
- 239000011521 glass Substances 0.000 claims abstract description 17
- 239000004744 fabric Substances 0.000 claims abstract description 14
- 239000003822 epoxy resin Substances 0.000 claims description 10
- 229920000647 polyepoxide Polymers 0.000 claims description 10
- 230000001154 acute effect Effects 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 238000005336 cracking Methods 0.000 abstract description 6
- 230000008859 change Effects 0.000 abstract description 5
- 238000007711 solidification Methods 0.000 abstract description 4
- 230000008023 solidification Effects 0.000 abstract description 4
- 239000003365 glass fiber Substances 0.000 abstract description 3
- 230000006872 improvement Effects 0.000 description 8
- 239000007788 liquid Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 3
- 239000008393 encapsulating agent Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of semiconductor chip package, and wherein, described encapsulating structure comprises: PPTC substrate; The first insulating barrier and the second insulating barrier is coated with respectively in the upper and lower surface of described PPTC substrate; Diode; Electrical connector; Through hole, is extended to lower surface by the upper surface of the first insulating barrier, penetrates the first insulating barrier; Diode is connected with PPTC electrical property of substrate; Described encapsulating structure also comprises encapsulating material and glass fabric, and the first insulating barrier that encapsulating material covers, described diode and described electrical connector, described glass fabric wraps up the lower surface of described encapsulating material and described PPTC substrate.Compared with prior art, the utility model is by adding glass fabric in a mold in advance, the encapsulating structure with glass fibre obtained after solidification, considerably improve the intensity of encapsulating material, can be good at solving the protrusion of surface occurred when being encapsulated in high/low temperature sudden change, the unusual conditions such as cracking.
Description
Technical field
The utility model belongs to field of semiconductor manufacture, particularly relates to a kind of semiconductor chip package.
Background technology
Traditional semiconductor die package mode is generally will be that solid-state encapsulating material melts and injects mould and the packaging process of fast curing-formed (5 ~ 50 seconds) again at normal temperatures by HTHP.This kind of packaged type is in the course of processing, and packed product needed bears higher temperature and pressure, if need the product of encapsulation itself not bear HTHP, just can not use this kind of solid-state material packaged type.Be liquid epoxy encapsulant under utilizing normal temperature, low pressure injects mould, and use baking-curing can solve the shortcoming of the non-refractory high pressure of packed material own, but the glass transition temperature of the epoxy encapsulant of liquid (Tg) is lower, after solidification, the intensity of epoxy encapsulant is low, is easily subject to high/low temperature sudden change (as reflow soldering, high/low-temperature impact etc.) impact, protrusion of surface occurs, the unusual conditions such as cracking, impact encapsulation quality.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor chip package solved the problems of the technologies described above.
Wherein, the semiconductor chip package of the utility model one execution mode, comprising:
PPTC substrate, it comprises upper surface and the lower surface opposing with upper surface;
First insulating barrier, covers on the upper surface of described PPTC substrate;
Second insulating barrier, covers on the lower surface of described PPTC substrate;
Diode, has the first electrode surface and second electrode surface opposing with described first electrode surface;
Electrical connector;
Through hole, is extended to lower surface by the upper surface of described first insulating barrier, penetrates described first insulating barrier; First electrode surface of described diode is connected with described PPTC electrical property of substrate by described through hole, and the second electrode surface of described diode is connected with described PPTC electrical property of substrate with described through hole by described electrical connector;
Wherein, described encapsulating structure also comprises encapsulating material and glass fabric, described encapsulating material covers the first insulating barrier of the upper surface of described PPTC substrate, described diode and described electrical connector, and described glass fabric wraps up the lower surface of described encapsulating material and described PPTC substrate.
As further improvement of the utility model, described PPTC substrate is composited by the PCT plate of multiple individual layer.
As further improvement of the utility model, described through hole can be circle or square at the opening shape of described first insulating barrier upper surface, and the angle between the inwall of described through hole and described PPTC substrate can be acute angle or right angle or obtuse angle.
As further improvement of the utility model, the inwall of described through hole is provided with conducting medium.
As further improvement of the utility model, the material of described conducting medium is copper.
As further improvement of the utility model, described encapsulating material is liquid-state epoxy resin.
As further improvement of the utility model, described liquid-state epoxy resin has low glass state inversion temperature (Tg).
As further improvement of the utility model, described electrical connector is metal clip or wire.
As further improvement of the utility model, each electrode surface of described diode to be formed with corresponding conductor by surface-pasted mode (SMT) to be electrically connected.
Compared with prior art, the utility model is by adding glass fabric in a mold in advance, and then solidify, the encapsulating structure with glass fibre obtained, considerably improve the intensity of encapsulating material epoxy resin, can be good at solving the protrusion of surface occurred when being encapsulated in high/low temperature sudden change, the unusual conditions such as cracking.
Accompanying drawing explanation
Fig. 1 is the side-looking structural representation of encapsulating structure in the utility model encapsulating structure one execution mode;
Fig. 2 is the flow chart of steps of method for packing in the utility model encapsulating structure one execution mode.
Embodiment
Below with reference to embodiment shown in the drawings, the utility model is described in detail.But these execution modes do not limit the utility model, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection range of the present utility model.
As shown in Figure 1, in the utility model one execution mode, semiconductor chip package comprises PPTC substrate 10, and this PPTC substrate 10 comprises upper surface and the lower surface opposing with this upper surface.This PPTC substrate 10 is composited by the PCT plate of multiple individual layer.Be coated with the first insulating barrier 11 at the upper surface of this PPTC substrate 10, be coated with the second insulating barrier 12 at the lower surface of this PPTC substrate 10.
Diode 20, have the first electrode surface 21 and second electrode surface 22 opposing with described first electrode surface 21, diode 20 adopts the mode of surface mount (SMT) to be placed on the first insulating barrier 11 of PPTC substrate 10.
In order to the electric connection of the first electrode surface 21 with PPTC substrate 10 that realize diode 20, on the first insulating barrier 11, the position of corresponding diode 20 is provided with at least one through hole 111, this through hole 111 is extended to lower surface by the upper surface of the first insulating barrier 11, and penetrates.Further, the inwall of through hole 111 is provided with conducting medium (not shown), and preferably, the material of conducting medium is copper, and diode 20 and the first insulating barrier 11 realize the electric connection with PPTC substrate 10 by the conducting medium on the inwall of through hole 111.Preferably, in the present embodiment, the quantity of through hole 111 is multiple, and be also provided with at least one identical through hole 112 in the position of not corresponding diode 20, this through hole can be circle at the opening shape of the first insulating barrier 11 upper surface, also can be square, the angle between this through-hole wall and PPTC substrate 10 can be acute angle, right angle or obtuse angle.
Electrical connector 30, preferable alloy folder or wire, second electrode surface 22 of its one end and diode 20 is fitted, the other end is directly electrically connected the conducting medium on through hole 112 inwall of PPTC substrate 10 first insulating barrier 11, so realizes the second electrode surface 22 of diode 20 and the electric connection of PPTC substrate 10.
Described encapsulating structure also comprises encapsulating material 40, and this encapsulating material 40 covers the first insulating barrier 11, diode 20 and electrical connector 30 on the upper surface of PPTC substrate 10.Because PPTC substrate 10 can not bear HTHP, therefore encapsulating material 40 is liquid epoxy resin under need selecting normal temperature, and this material under low pressure can inject mould, baking temperature is up to 150 DEG C, and such encapsulation condition can not bring impact to PPTC substrate 10.In addition, epoxy resin due to liquid state has low glass state conversion temperature (Tg), therefore its package strength is not after hardening very high, is easily subject to high/low temperature sudden change (as reflow soldering, high/low-temperature impact etc.) impact, there is protrusion of surface, the unusual conditions such as cracking.In order to solve the problem, glass fabric 50 is introduced in the utility model, with the second insulating barrier 12 of the lower surface of glass fabric 50 wrapping and encapsulating material 40 and described PPTC substrate 10, can avoid occurring encapsulating structure protrusion of surface, the unusual conditions such as cracking.
Shown in ginseng Fig. 2, be the flow chart of steps of method for packing in encapsulating structure one execution mode, it comprises:
S1, provide a PPTC substrate, it comprises upper surface and the lower surface opposing with upper surface.This PPTC substrate 10 is composited by the PCT plate of multiple individual layer.Form the first insulating barrier 11 at the upper surface of this PPTC substrate 10, form the second insulating barrier 12 at the lower surface of this PPTC substrate 10.
S2, provide a diode, it has the first electrode surface and second electrode surface opposing with described first electrode surface.On the first insulating barrier 11, the position of corresponding diode 20 is provided with at least one through hole 111, and this through hole 111 is extended to lower surface by the upper surface of the first insulating barrier 11, and penetrates.Further, the inwall of through hole 111 is provided with conducting medium (not shown), preferably, in the present embodiment, the quantity of through hole 111 is multiple, and is also provided with at least one identical through hole 112 in the position of not corresponding diode 20, and this through hole can be circle at the opening shape of the first insulating barrier 11 upper surface, also can be square, the angle between this through-hole wall and PPTC substrate 10 can be acute angle, right angle or obtuse angle.
S3, described diode to be connected with described PPTC electrical property of substrate.Diode 20 and the first insulating barrier 11 realize the electric connection with PPTC substrate 10 by the conducting medium on the inwall of through hole 111, one electrical connector 30 is provided, preferable alloy folder or wire, second electrode surface 22 of its one end and diode 20 is fitted, the other end is directly electrically connected the conducting medium on through hole 112 inwall of PPTC substrate 10 first insulating barrier 11, so realizes the second electrode surface 22 of diode 20 and the electric connection of PPTC substrate 10.Each electrode surface of diode 20 be to be formed with corresponding conductor by surface-pasted mode (SMT) to be electrically connected.
S4, provide a mould, put into glass fabric in the mold, the described diode and described PPTC substrate that more form electric connection are put into described mould.In order to increase the hardness after encapsulating material solidification, before encapsulating material injects mould, put into a glass fabric in a mold, glass fabric has good wetability to encapsulating material liquid-state epoxy resin, so can not affect it in liquid-state epoxy resin injection mold process to be full of whole cavity body of mould.
S5, liquid encapsulating material is injected mould, baking makes described liquid encapsulating material solidify.Liquid-state epoxy resin under low pressure injects mould, here low pressure refers to the normal atmospheric pressure in daily life, baking-curing temperature is up to 150 DEG C, liquid-state epoxy resin after solidification and glass fabric have good combining closely, can bear as reflow soldering, the various mal-condition such as high/low-temperature impact and protrusion of surface does not occur, cracking hierarchical phenomenon, and because glass fibre has the characteristic of high-tensile strength, the intensity of whole encapsulating structure is improved, use the method for packing that this kind novel, whole encapsulating structure can be made to reach insulation, high temperature resistant, shock resistance, damping, moistureproof, waterproof, the effects such as dust-proof and resistance to chemical attack.
Be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, technical scheme in each execution mode also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
A series of detailed description listed is above only illustrating for feasibility execution mode of the present utility model; they are also not used to limit protection range of the present utility model, all do not depart from the utility model skill equivalent implementations of doing of spirit or change all should be included within protection range of the present utility model.
Claims (9)
1. a semiconductor chip package, comprising:
PPTC substrate, it comprises upper surface and the lower surface opposing with upper surface;
First insulating barrier, covers on the upper surface of described PPTC substrate;
Second insulating barrier, covers on the lower surface of described PPTC substrate;
Diode, has the first electrode surface and second electrode surface opposing with described first electrode surface;
Electrical connector;
Through hole, is extended to lower surface by the upper surface of described first insulating barrier, penetrates described first insulating barrier; First electrode surface of described diode is connected with described PPTC electrical property of substrate by described through hole, and the second electrode surface of described diode is connected with described PPTC electrical property of substrate with described through hole by described electrical connector;
It is characterized in that, described encapsulating structure also comprises encapsulating material and glass fabric, described encapsulating material covers the first insulating barrier of the upper surface of described PPTC substrate, described diode and described electrical connector, and described glass fabric wraps up the lower surface of described encapsulating material and described PPTC substrate.
2. semiconductor chip package according to claim 1, is characterized in that, described PPTC substrate is composited by the PCT plate of multiple individual layer.
3. semiconductor chip package according to claim 1, it is characterized in that, described through hole can be circle or square at the opening shape of described first insulating barrier upper surface, and the angle between the inwall of described through hole and described PPTC substrate can be acute angle or right angle or obtuse angle.
4. semiconductor chip package according to claim 3, is characterized in that, the inwall of described through hole is provided with conducting medium.
5. semiconductor chip package according to claim 4, is characterized in that, the material of described conducting medium is copper.
6. semiconductor chip package according to claim 1, is characterized in that, described encapsulating material is liquid-state epoxy resin.
7. semiconductor chip package according to claim 6, is characterized in that, described liquid-state epoxy resin has low glass state inversion temperature Tg.
8. semiconductor chip package according to claim 1, is characterized in that, described electrical connector is metal clip or wire.
9. semiconductor chip package according to claim 1, is characterized in that, each electrode surface of described diode to be formed with corresponding conductor by surface-pasted mode SMT to be electrically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420583226.4U CN204088293U (en) | 2014-10-10 | 2014-10-10 | Semiconductor chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420583226.4U CN204088293U (en) | 2014-10-10 | 2014-10-10 | Semiconductor chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204088293U true CN204088293U (en) | 2015-01-07 |
Family
ID=52180974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420583226.4U Expired - Lifetime CN204088293U (en) | 2014-10-10 | 2014-10-10 | Semiconductor chip package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204088293U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105173441A (en) * | 2015-08-28 | 2015-12-23 | 镇江宝纳电磁新材料有限公司 | Electronic element storage device |
-
2014
- 2014-10-10 CN CN201420583226.4U patent/CN204088293U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105173441A (en) * | 2015-08-28 | 2015-12-23 | 镇江宝纳电磁新材料有限公司 | Electronic element storage device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103620763A (en) | Power semiconductor module and method of manufacturing same | |
| CN204088293U (en) | Semiconductor chip package | |
| CN203536467U (en) | LED device having transition substrate | |
| CN103579201B (en) | Adopt semiconductor device electromagnetic armouring structure and the manufacture method of conductive packaging material | |
| CN206340542U (en) | A kind of QFN surface-adhered types RGB LED encapsulation modules | |
| CN101221630A (en) | Smart card encapsulation and its encapsulation structure | |
| CN203055893U (en) | Re-wiring thermal enhanced FCQFN packaging device | |
| CN101483289B (en) | Assembling method for DC electric connector and DC electric connector | |
| CN104269361B (en) | Method for packaging semiconductor chip | |
| CN205920989U (en) | A LED support and LED for face down chip | |
| CN202350944U (en) | Integrated injection temperature sensor | |
| CN107910145A (en) | A kind of embedded varistor and its manufacture craft | |
| CN204067374U (en) | A kind of high-power high-current diode package structure | |
| CN211209948U (en) | Insulation structure of connecting point of heating plate pole piece and wire | |
| CN103579202B (en) | Organic substrate semiconducter device electromagnetic armouring structure and making method | |
| CN204118116U (en) | A kind of LED encapsulation structure | |
| CN204130728U (en) | Wire and cable connector | |
| CN201773836U (en) | Package lead of integrated circuit device | |
| CN202948921U (en) | Non-insulated type power module | |
| CN207265046U (en) | A kind of DIP encapsulating structures with embedded PIN needle | |
| CN205319144U (en) | Encapsulation chip's structure | |
| CN201945400U (en) | Injection-moulding temperature sensor for anti-thermal shock | |
| CN201590336U (en) | Novel ceramic feed-through capacitor with resistance to temperature impact | |
| CN211828759U (en) | FC chip packaging structure based on glass substrate | |
| CN203850290U (en) | Plastic-sealed lead frame suitable for high-temperature electrical appliances |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20150107 |