CN204067332U - Based on the salient point flip-chip CSP packaging part of substrate - Google Patents
Based on the salient point flip-chip CSP packaging part of substrate Download PDFInfo
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- CN204067332U CN204067332U CN201420447273.6U CN201420447273U CN204067332U CN 204067332 U CN204067332 U CN 204067332U CN 201420447273 U CN201420447273 U CN 201420447273U CN 204067332 U CN204067332 U CN 204067332U
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- salient point
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- 239000000758 substrate Substances 0.000 title claims abstract description 158
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 47
- 239000000945 filler Substances 0.000 claims abstract description 15
- 238000011049 filling Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims abstract description 4
- 239000010949 copper Substances 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 22
- 239000000919 ceramic Substances 0.000 abstract description 11
- 239000000463 material Substances 0.000 abstract description 11
- 238000002161 passivation Methods 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 9
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- 238000012360 testing method Methods 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
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- 239000004411 aluminium Substances 0.000 description 2
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- 238000002360 preparation method Methods 0.000 description 2
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- 238000005476 soldering Methods 0.000 description 2
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- 241001397104 Dima Species 0.000 description 1
- 150000001398 aluminium Chemical class 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
A kind of salient point flip-chip CSP packaging part based on substrate, comprise substrate and the IC chip of upside-down mounting on substrate, and be filled with lower filler, substrate comprises again the substrate intermediate layer that all there is track on upper and lower surface, substrate intermediate layer has the sidewall be connected with track of multiple tubular, all there is multiple substrate pads be connected with track above and below, substrate intermediate layer.With FR-4 copper-clad plate or BT substrate for substrate material, obtain substrate through the operation such as boring, plating, paving dry film, exposure, development.Passivation wafer, chip bonding pad is formed UBM layer, coating photoresist, and copy pattern on photoresist layer, forms Sn/Pb metal level, and reflux to obtain weldering salient point, and flip-chip, melt weldering salient point, lower filling, obtains CSP packaging part.The high-frequency electrical performance that this packaging part solves wire bond package in the connection of existing IC encapsulated circuit is poor, the encapsulation problem that the thermal expansion mismatch between ceramic substrate and PCB is larger.
Description
Technical field
The utility model belongs to electronic device and manufactures technical field of semiconductor encapsulation, relates to a kind of salient point flip-chip CSP packaging part based on substrate.
Background technology
Growing along with electronic information technology, integrated antenna package on the one hand towards high performance future development, on the other hand towards compact future development.In IC encapsulation, chip and the connection of substrate (lead frame) are that power supply provides circuit with the distribution of signal and is connected, have three kinds of modes to can be used for realizing the inside connection of IC chip package: wire bonding, carrier band automatic welding and flip chip bonding.At present, the IC chip connected mode of more than 90% is still wire bonding, because bonding wire is longer, cause adopting the distribution of packaging part of wire bond package and stray inductance, resistance and electric capacity comparatively large, have impact on the signal integrity of packaging part and frequency characteristic etc.In high side device and high-density packages field, especially in high frequency field, the limitation that Wire Bonding Technology is natural, makes it be difficult to become a kind of frequent adopted packing forms, so be necessary that upside-down mounting (Flip-Chip) technology proposing a kind of low cost is to replace traditional Wire Bonding Technology.
CSP (Chip Scale Package) encapsulates, and namely wafer-level package is the packing forms grown up in recent years, at present hundreds of product existing, and constantly occurs some new products.However, domestic CSP technology is still in the junior stage, and does not form unified standard.CSP product chips pad on market today and the connected mode of enclosed chip pad adopt flip-chip bonding mostly, and base plate for packaging also adopts ceramic substrate decades ago.But after silicon (silicon die) is installed on ceramic substrate, due to ceramic substrate do not mate with the thermal coefficient of expansion (CTE) of PCB substrate, too large (CTE of ceramic substrate is 6 ~ 8ppm/ DEG C to difference, the CTE of PCB substrate is 16 ~ 19ppm/ DEG C), be difficult to ceramic substrate to be arranged to again in PCB substrate.Move towards the requirement of densification, high performance and high reliability to adapt to PCB, solve the CTE mismatch problem of ceramic substrate and PCB substrate, IC base plate for packaging is rapid moves towards organic substrate (pcb board) by inorganic substrate (ceramic substrate).
Summary of the invention
In connecting for current IC encapsulated circuit, the high-frequency electrical performance of wire bond package is poor, the encapsulation present situation that thermal expansion mismatch (TEM) between ceramic substrate and PCB is larger, the utility model provides a kind of weldering salient point flip-chip CSP packaging part based on substrate, is applicable to the encapsulation that chip is held in low-power consumption and low extraction (I/O).
For achieving the above object, the technical scheme that the utility model adopts is: a kind of salient point flip-chip CSP packaging part based on substrate, comprise substrate, substrate comprises again the substrate intermediate layer that upper surface and lower surface are equipped with track, substrate intermediate layer is processed with multiple hole, in each hole, equal plating has the sidewall of tubular, sidewall two ends are connected with substrate intermediate layer lower surface track with substrate intermediate layer upper surface track respectively by via pad, are provided with multiple second substrate pad be connected with the track below substrate intermediate layer below substrate intermediate layer; Substrate intermediate layer is provided with multiple first substrate pad be connected with the track of substrate intermediate layer, upper surface and the lower surface of substrate are all printed with solder mask layer, and the upper surface of all first substrate pads and the surface of all second substrate pads are all exposed outside solder mask layer; First substrate pad is provided with IC chip, and IC chip is provided with multiple chip bonding pad, and a chip bonding pad is connected with a first substrate pad by the weldering salient point bottom a chip bonding pad; Lower filler is filled with between IC chip and substrate; Lower filler fills up the space around all weldering salient points, and all weldering salient points, upper surface of base plate and IC chip lower surface are all covered in lower filler.
The utility model is applicable to the encapsulation that chip is held in low-power consumption and low extraction (I/O), this CSP packaging part adopts dedicated substrate and flip-chip, the high-frequency electrical performance solving wire bond package in the connection of existing IC encapsulated circuit is poor, the encapsulation problem that the thermal expansion mismatch (TEM) between ceramic substrate and PCB is larger.Use the flip chip interconnects technology of weldering salient point, make this packaging part slim body, can be used in miniaturized products, and this packaging part does not use bonding wire in encapsulation process, chip soldering salient point pad on substrate is directly combined, so the distribution of packaging part and stray inductance, resistance, electric capacity are less, ensure that signal integrity and the frequency characteristic of packaging part.Meanwhile, the heat that this packaging part chip distributes directly propagates on substrate by weldering salient point, therefore the heat dispersion of packaging part is also better.And in substrate manufacture process, FR-4 copper-clad plate or BT substrate is adopted to instead of traditional ceramic substrate, so avoid thermal coefficient of expansion (CTE) mismatch problem of base plate for packaging and PCB substrate, and this substrate manufacture process is simple, substantially reduces packaging cost.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the utility model CSP packaging part.
Fig. 2 is the schematic diagram of IC chip in the utility model CSP packaging part.
Fig. 3 is the schematic diagram of the substrate material that the utility model CSP packaging part adopts.
Fig. 4 is when preparing the substrate used in the utility model CSP packaging part, the schematic diagram on substrate material after boring.
Fig. 5, when preparing the substrate used in the utility model CSP packaging part, electroplates the schematic diagram after sidewall in the hole that substrate material bores.
Fig. 6, when preparing the substrate used in the utility model CSP packaging part, substrate material forms the schematic diagram of dry film figure.
Fig. 7 is when preparing the substrate used in the utility model CSP packaging part, forms the schematic diagram of the pcb board of track.
Fig. 8 is when preparing the substrate used in the utility model CSP packaging part, at the schematic diagram of pcb board surface-coated solder mask layer.
Fig. 9 is when preparing the substrate used in the utility model CSP packaging part, forms the schematic diagram of substrate pads on pcb board surface.
Figure 10 is when preparing the utility model CSP packaging part, and the passivation layer on chip bonding pad surface is by the schematic diagram after etching.
Figure 11, when preparing the utility model CSP packaging part, chip bonding pad is prepared the schematic diagram after UBM layer.
Figure 12, when preparing the utility model CSP packaging part, wafer applies the schematic diagram after photoresist.
Figure 13, when preparing the utility model CSP packaging part, photoresist layer forms the schematic diagram of window.
Figure 14 is when preparing the utility model CSP packaging part, electroplates the schematic diagram of Sn/Pb metal level in the window.
Figure 15 is when preparing the utility model CSP packaging part, removes the schematic diagram after the photoresist layer outside window.
Figure 16 is when preparing the utility model CSP packaging part, forms the schematic diagram of weldering salient point after backflow.
In figure: 1.IC chip, 2. chip bonding pad, 3. weld salient point, 4. first substrate pad, 5. track, 6. descends filler, 7. solder mask layer, 8. via pad, 9. through hole, 10. sidewall, 11. second substrate pads, 12. substrates, 13. substrate intermediate layers, 14. layers of copper, 15. holes, 16. dry films, 17. passivation layers, 18.UBM layer, 19. photoresist layers, 20. windows, 21.Cu layer, 22. Sn/Pb metal levels.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in detail.
As shown in Figure 1, the utility model CPS packaging part, comprise substrate 12, upper surface and the lower surface in the substrate intermediate layer 13 in substrate 12 are equipped with track 5, substrate intermediate layer 13 are processed with multiple hole 15, and in each hole 15, all plating has the copper sidewall 10 of tubular, the two ends of sidewall 10 are respectively equipped with the via pad 8 be connected with this sidewall 10, via pad 8 is connected with the track 5 on substrate, and the endoporus of sidewall 10 is through hole 9, and in through hole 9, filling has ink; Be provided with multiple second substrate pad 11 below substrate intermediate layer 13, second substrate pad 11 is copper pad; Multiple first substrate pad 4 is provided with above substrate intermediate layer 13, all first substrate pads 4 are all connected with the track 5 above substrate intermediate layer 13, track 5 above substrate intermediate layer 13 is drawn from first substrate pad 4 and is distributed in the middle of substrate intermediate layer 13 again, the track 5 distributed again is connected with second substrate pad 11 with sidewall 10 by via pad 8, meanwhile, second substrate pad 11 is connected with the track 5 below substrate intermediate layer 13; The upper surface of substrate 12 and lower surface are all printed with solder mask layer 7, and the upper surface of all first substrate pads 4 and the surface of all second substrate pads 11 are all exposed outside solder mask layer 7; First substrate pad 4 is provided with IC chip 1 as shown in Figure 2, IC chip 1 is provided with two row pads, often row pad forms by multiple chip bonding pad 2, and each chip bonding pad 2 is equipped with weldering salient point 3, chip bonding pad 2 and is connected with a first substrate pad 4 by the weldering salient point 3 on this chip bonding pad 2; Be filled with lower filler 6 between IC chip 1 and substrate 12, the space around all weldering salient points 3 is all filled up by lower filler 6, and all weldering salient points 3, substrate 12 upper surface and IC chip 1 lower surface is covered completely.
The substrate 12 used in the utility model CSP packaging part adopts following methods to obtain:
Step 1: according to requirements design substrate 12;
Step 2: substrate material chooses FR-4 copper-clad plate or BT substrate, as shown in Figure 3, substrate material is made up of the layers of copper 14 that substrate intermediate layer 13, substrate intermediate layer 13 upper surface and substrate intermediate layer 13 lower surface cover; According to the designing requirement of substrate 12, adopt machine drilling mode, substrate material forms multiple hole 15 running through substrate material, as shown in Figure 4;
Step 3: adopt electroplating technology, at the sidewall 10 that the thickness of electroplating surface one deck tubular in hole 15 is copper uniformly, the endoporus of sidewall 10 is through hole 9, and the two ends of sidewall 10 are connected with the layers of copper 14 on lower surface with substrate intermediate layer 13 upper surface respectively, as shown in Figure 5;
Step 4: circuit diagram is formed:
First, the layers of copper 14 on the upper and lower surface of substrate material lays one deck dry film 16 respectively, by exposure, development, remove the dry film 16 except visuals in two-layer layers of copper 14, the layers of copper 14 of interbed 13 upper surface in a substrate forms the dry film figure identical with upper surface of base plate track wiring diagram, the layers of copper 14 of interbed 13 lower surface in a substrate forms the dry film figure identical with base lower surface track wiring diagram, as shown in Figure 6; Then, etch, remove the protective effect of exposed layers of copper 14(due to dry film figure, can not be affected by the layers of copper 14 that dry film figure covers), the upper surface of interbed 13 and lower surface form track 5 respectively in a substrate, and the via pad 8 be connected with sidewall 10, as shown in Figure 7; Finally, remove the dry film that track 5 covers, with ink filling through hole 9, after carrying out semi-solid preparation, polishing surface, makes surfacing, obtains semi-finished product substrate,
Step 5: at upper surface and the lower surface coating solder mask layer 7 of semi-finished product substrate, then carry out semi-solid preparation, as shown in Figure 8;
Step 6: by UV exposure, development, remove the solder mask layer 7 at semi-finished product upper surface of base plate first substrate pad 4 design attitude place, remove the solder mask layer 7 at semi-finished product base lower surface second substrate pad 11 design attitude place; Then zinc-plated at the design attitude place of the first substrate pad 4 exposed, form first substrate pad 4, in the design attitude place copper facing of the second substrate pad 11 exposed, form second substrate pad 11, as shown in Figure 9;
Step 7: by washing and drying, segmentation, test verification, obtain substrate.
The utility model CSP packaging part adopts following method to obtain:
Step 1: obtained substrate as stated above;
Step 2: coating passivation layer
Supplied materials wafer is placed on the workbench of energy High Rotation Speed, then passivating solution is expelled to crystal circle center position, afterwards high speed rotational operation platform, by the effect of centrifugal force, passivating solution is coated in crystal column surface uniformly, form passivation layer 17;
Step 3: passivation layer perforate
Adopt engraving method or laser ablation method, remove the passivation layer 17 on chip bonding pad 2 surface on wafer, form passivation layer opening, as shown in Figure 10, the aluminium press welding block on exposed chip pad 2, cleans this aluminium press welding block;
Step 4: sputtered with Ti layer and Cu layer
First at the whole surface sputtering Ti layer of wafer, then on this Ti layer, sputter Cu layer again, form Ti/Cu layer, the Ti/Cu layer be covered on chip bonding pad 2 is UBM layer 18, as shown in figure 11;
Step 5: coating photoresist
Photoresist is coated in equably on Ti/Cu layer, form photoresist layer 19, as shown in figure 12, then wafer is toasted, baking time determines the (thickness of photoresist layer: 35 ± 0.5 μm according to the kind of photoresist and thickness, baking time: 15 ± 3 seconds, baking temperature: 80 ± 5 DEG C), photoresist and Ti/Cu layer are combined closely;
Step 6: photoetching weldering salient point figure
First, mask aligner alignment system butt welding salient point mask plate and wafer is used to aim at; Make a chip bonding pad 2 on the corresponding wafer of a graph window on mask plate, namely chip bonding pad 2 is in the below of a graph window on mask plate, then, ultraviolet light is radiated on photoresist layer 19 by the graph window on mask plate, exposure-processed is carried out to wafer, make the photoresist layer 19 of exposed portion that photochemical reaction occur, change the dissolubility of photoresist in developer solution; Finally, use developing solution dissolution that photochemically reactive photoresist layer 19 occurs, graph window on mask plate is copied on photoresist layer 19, photoresist layer 19 is formed window 20, the size of window 20 is greater than the size of the passivation layer opening on passivation layer 17, expose UBM layer 18, as shown in figure 13;
Step 7: electroplated metal layer
First, UBM layer 18 electroplates Cu, form Cu layer 21, then on Cu layer 21, electroplate the solder of 63wt%Sn and 37wt%Pb composition, form Sn/Pb metal level 22, Sn/Pb metal level 22 and fill window 20, as shown in figure 14, the position at Sn/Pb metal level 22 top, higher than the position at photoresist layer 19 top, forms mushroom-shaped salient point at window 20 place;
Step 8: remove photoresist:
Cleaning fluid removes the remaining photoresist layer 19 of crystal column surface with photoresist, as shown in figure 15;
Step 9: peel off Ti/Cu layer:
Remove the Ti/Cu layer outside Sn/Pb metal level 22 area of coverage with hydrogen peroxide etching, and reclaim used hydrogenperoxide steam generator;
Step 10: backflow
Wafer is put into reflow soldering, at high temperature makes Sn/Pb metal level 22 on chip bonding pad 2 melt, in capillary effect, the weldering salient point 3 of the ball-type that self-assembling formation is smooth on chip bonding pad 2 of the solder after thawing, as shown in figure 16;
Step 11: the wafer cutting and separating making weldering salient point 3 is become single IC chip 1, and use isopropyl alcohol to clean substrate obtained in the IC chip 1 of cutting and separating and step 1, to reduce the pollution such as particulate, grease; First substrate pad 4 corresponding with chip bonding pad 2 on substrate applies no-clean scaling powder, then, use flip-chip back bonding equipment pickup IC chip 1, by equipment configuration, camera is looked up/overlooked to mutatis mutandis, the position of automatic adjustment IC chip 1, after chip bonding pad 2 is alignd one by one with first substrate pad 4, IC chip 1 is tipped upside down on substrate;
Step 12: the substrate of IC chip 1 is placed on the conveyer belt of DIMA SMT system by back-off, this system uses nitrogen, and (oxygen purity is set as 50 × 10
-6) environment, melt solder, make weldering salient point 3 and first substrate pad 4 strong bonded;
Step 13: use lower pad device, be filled between IC chip 1 and substrate by lower filler 6, make all weldering salient points 3 all be closed in lower filler 6, lower filler 6 butt welding salient point 3 plays reinforcing and protective effect, improves product reliability; After lower filling, according to the physical characteristic of lower filler 6 to carrying out Post RDBMS process; Lower filler encapsulating can, by die bonding on substrate, prevent from, because the thermal expansion mismatch (TEM) between silicon and lamination organic substrate causes solder joint to be out of shape fracture, ensureing the reliability of weldering salient point;
Step 14: after Post RDBMS, by inspection, test, marking, cutting and separating, packaging, obtaining the salient point flip-chip CSP packaging part based on substrate, it is to be noted when testing, testing power supply is direct current 5V, impacts packaging part electrical property to avoid electric current.
Claims (3)
1. the salient point flip-chip CSP packaging part based on substrate, it is characterized in that, described packaging part comprises substrate (12), substrate (12) comprises again the substrate intermediate layer (13) that upper surface and lower surface are equipped with track (5), substrate intermediate layer (13) is processed with multiple hole (15), in each hole (15), all plating has the sidewall (10) of tubular, sidewall (10) two ends are connected with substrate intermediate layer (13) lower surface track (5) with substrate intermediate layer (13) upper surface track (5) respectively by via pad (8), multiple second substrate pad (11) be connected with the track (5) below substrate intermediate layer (13) is provided with below substrate intermediate layer (13), substrate intermediate layer (13) is provided with multiple first substrate pad (4) be connected with the track (5) above substrate intermediate layer (13) above, the upper surface of substrate (12) and lower surface are all printed with solder mask layer (7), and solder mask layer (7) is all exposed outward in the upper surface of all first substrate pads (4) and the surface of all second substrate pads (11), first substrate pad (4) is provided with IC chip (1), IC chip (1) is provided with multiple chip bonding pad (2), and a chip bonding pad (2) is connected with a first substrate pad (4) by weldering salient point (3), lower filler (6) is filled with between IC chip (1) and substrate (12), lower filler (6) fills up all weldering salient points (3) space around, and all weldering salient points (3), substrate (12) upper surface and IC chip (1) lower surface are all covered in lower filler (6).
2., as claimed in claim 1 based on the salient point flip-chip CSP packaging part of substrate, it is characterized in that, described sidewall (10) is copper sidewall.
3. as claimed in claim 1 or 2 based on the salient point flip-chip CSP packaging part of substrate, it is characterized in that, in described sidewall (10) endoporus, filling has ink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420447273.6U CN204067332U (en) | 2014-08-08 | 2014-08-08 | Based on the salient point flip-chip CSP packaging part of substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420447273.6U CN204067332U (en) | 2014-08-08 | 2014-08-08 | Based on the salient point flip-chip CSP packaging part of substrate |
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| Publication Number | Publication Date |
|---|---|
| CN204067332U true CN204067332U (en) | 2014-12-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420447273.6U Expired - Lifetime CN204067332U (en) | 2014-08-08 | 2014-08-08 | Based on the salient point flip-chip CSP packaging part of substrate |
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| Country | Link |
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| CN (1) | CN204067332U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201156A (en) * | 2014-08-08 | 2014-12-10 | 天水华天科技股份有限公司 | Substrate based bumped flip chip CSP (Chip Scale Package) package part, substrate and manufacturing method |
| CN107743022A (en) * | 2017-10-19 | 2018-02-27 | 深圳华远微电科技有限公司 | Ceramic CSP package substrate constructions |
-
2014
- 2014-08-08 CN CN201420447273.6U patent/CN204067332U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201156A (en) * | 2014-08-08 | 2014-12-10 | 天水华天科技股份有限公司 | Substrate based bumped flip chip CSP (Chip Scale Package) package part, substrate and manufacturing method |
| CN107743022A (en) * | 2017-10-19 | 2018-02-27 | 深圳华远微电科技有限公司 | Ceramic CSP package substrate constructions |
| CN107743022B (en) * | 2017-10-19 | 2024-06-11 | 浙江华远微电科技有限公司 | Ceramic CSP packaging substrate structure |
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