CN204066681U - The gate driver circuit of flat-panel monitor and low-power consumption output module thereof - Google Patents
The gate driver circuit of flat-panel monitor and low-power consumption output module thereof Download PDFInfo
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- CN204066681U CN204066681U CN201420256515.3U CN201420256515U CN204066681U CN 204066681 U CN204066681 U CN 204066681U CN 201420256515 U CN201420256515 U CN 201420256515U CN 204066681 U CN204066681 U CN 204066681U
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Abstract
The utility model discloses the low-power consumption output module of the gate driver circuit of flat-panel monitor, comprise the output module of multiple driver elements of cascade, the output module of each driver element comprises cascaded-output level, output stage and control end; Described cascaded-output level is connected with AC signal line, is driven by AC signal; Described output stage is connected with direct current signal line, is driven by direct current signal; Described cascaded-output level is connected with the output stage of the driver element of next stage; The capable pixel of output signal Direct driver of output stage; Described control end, using the output signal of cascaded-output level as input signal, controls the on off state of output stage.The invention also discloses the gate driver circuit of the flat-panel monitor comprising above-mentioned output module.Output module simple structure of the present utility model, consumes transparency area little, adopts output module of the present utility model can save the main dynamic power consumption of gate driver circuit.
Description
Technical field
The utility model relates to the gate driver technology of flat-panel monitor, particularly a kind of gate driver circuit of flat-panel monitor and low-power consumption output module thereof.
Background technology
The raster data model of flat-panel monitor has two kinds of methods to realize, a kind of integrated circuit of CMOS that adopts realizes, CMOS technology is ripe, speed is fast, often large-sized display adopts the gate driver technology of CMOS, but due to CMOS technology and TFT technology incompatible, need to increase extra technique, as COG technology; CMOS is less than TFT area, needs to sacrifice some frame areas and CMOS chip is connected with tft array.Another kind method is exactly that the gate drivers adopting TFT to form replaces CMOS integrated circuit, and advantage has minimizing processing step, realizes narrow frame; Shortcoming is in large-sized display screen, and long lead-in wire and too much device, can cause yield to decline.In the display screen of small-medium size, in order to pursue hommization, attractive in appearanceization, the grid integrated drive of TFT becomes the indispensable part of panel, and particularly in a mobile device, high-resolution display screen has been main flow, TFT grid integrated drive becomes more important, we require that grid integrated drive area occupied is less, and power consumption is lower, make the attractive in appearance and mobile device of display screen have the duration more lengthened.
The Driving technique of grid integrated drive electronics often can be divided into, and exchanges Driving technique and direct drive technology.Exchange Driving technique due to circuit working principle simple, adopt TFT device less, and be extensively subject to the application of flat pannel display producer, but adopt the gate driver circuit exchanging Driving technique, in the extraneous clock signal of the drain electrode of pull-up TFT, for providing the sweep signal of array, because the size of pull-up TFT is comparatively large, stray capacitance is large, therefore cannot avoid the dynamic power consumption of output stage, particularly in the high-resolution display screen of large scale, dynamic power consumption becomes the main power consumption of circuit working; Adopt the grid integrated drive electronics of direct drive technology, the grid integrated drive electronics drive principle of direct drive technology is complicated, needs more TFT device, not only consume more transparency area, and more cabling, easily cause signal disturbing and loss, be difficult to ensure signal integrity.
Utility model content
In order to overcome the above-mentioned shortcoming of prior art with not enough, the purpose of this utility model is the output module of the gate driver circuit providing a kind of flat-panel monitor, simple structure, consumes transparency area little, adopt output module of the present utility model, save the dynamic power consumption that gate driver circuit is main.
Another object of the present utility model is that providing package contains the gate driver circuit of the flat-panel monitor of above-mentioned output module.
The purpose of this utility model is achieved through the following technical solutions:
The low-power consumption output module of the gate driver circuit of flat-panel monitor, comprises the output module of multiple driver elements of cascade, and the output module of each driver element comprises cascaded-output level, output stage and control end; Described cascaded-output level is connected with AC signal line, is driven by AC signal; Described output stage is connected with direct current signal line, is driven by direct current signal; Described cascaded-output level is connected with the output stage of the driver element of next stage; The capable pixel of output signal Direct driver of output stage; Described control end, using the output signal of cascaded-output level as input signal, controls the on off state of output stage.
The gate driver circuit of flat-panel monitor, comprises multiple driver elements of cascade, comprises above-mentioned low-power consumption output module.
Preferably, each driver element comprises the first ~ the 15 transistor and the first ~ the second electric capacity;
The grid of third transistor, the grid of the 4th transistor are connected with the first clock cable CLK1 respectively; Second electrode of third transistor is connected with the first power lead VDD; First electrode of third transistor and the second Electrode connection of the 4th transistor; First electrode of the 4th transistor is connected with the second electrode of the 5th transistor, the second electrode of the 11 transistor, the first end of the second electric capacity, the grid of the 8th transistor, the grid of the tenth transistor respectively; The grid of the 5th transistor, the grid of the 6th transistor are connected with signal input part VIN respectively; First electrode of the 5th transistor and the second Electrode connection of the 6th transistor; First electrode of the 6th transistor respectively with the first electrode, the first electrode of the 13 transistor, the second end of the second electric capacity, the first electrode of the 8th transistor, first Electrode connection of the 14 transistor of second source line VSSL, the 11 transistor;
The grid of the first transistor, the grid of transistor seconds are connected with second clock signal wire CLK2 respectively; Second electrode of the first transistor is connected with input end VIN; First electrode of the first transistor respectively with the second electrode of transistor seconds, the second Electrode connection of the tenth two-transistor; First electrode of transistor seconds is connected with the second electrode of the 13 transistor, the grid of the 7th transistor, the first end of the first electric capacity respectively;
Second electrode of the 7th transistor is connected with the first electrode of the tenth two-transistor, the 3rd clock cable CLK3 respectively; First electrode of the 7th transistor respectively with the second electrode, the grid of the tenth two-transistor, the grid of the 9th transistor, second Electrode connection of the 14 transistor of the first electric capacity second end, the 8th transistor, tie point is as the output terminal COUT of cascaded-output level;
Second electrode of the 9th transistor is connected with the first power lead VDD; First electrode of the 9th transistor and the output terminal OUT of driver element, the second electrode of the 15 transistor, the second Electrode connection of the tenth transistor; First electrode of the tenth transistor is connected with the first electrode of the 15 transistor, the 3rd power lead VSS respectively; The grid of the 13 transistor is connected with the grid of the 14 transistor, the grid of the 15 transistor, initialize signal line init respectively.
Preferably, each driver element comprises the first ~ the 16 transistor and the first ~ the second electric capacity;
The grid of third transistor, the grid of the 4th transistor are connected with the first clock cable CLK1 respectively; Second electrode of third transistor is connected with the first power lead VDD; First electrode of third transistor and the second Electrode connection of the 4th transistor; First electrode of the 4th transistor is connected with the second electrode of the 5th transistor, the second electrode of the 11 transistor, the first end of the second electric capacity, the grid of the 8th transistor, the grid of the tenth transistor respectively; The grid of the 5th transistor, the grid of the 6th transistor are connected with input end VIN respectively; First electrode of the 5th transistor and the second Electrode connection of the 6th transistor; First electrode of the 6th transistor respectively with the first electrode, the first electrode of the 13 transistor, the second end of the second electric capacity, the first electrode of the 8th transistor, the first electrode of the 14 transistor, first Electrode connection of the 16 transistor of second source line VSSL, the 11 transistor;
The grid of the first transistor, the grid of transistor seconds are connected with second clock signal wire CLK2 respectively; Second electrode of the first transistor is connected with input end VIN; Second Electrode connection of the first electrode of the first transistor and the second electrode of transistor seconds, the tenth two-transistor; First electrode of transistor seconds is connected with the second electrode of the 13 transistor, the grid of the 7th transistor, the first end of the first electric capacity respectively;
Second electrode of the 7th transistor is connected with the tenth two-transistor first electrode, the 3rd clock cable CLK3 respectively; Second electrode of the first electrode of the 7th transistor and the second end of the first electric capacity, the 8th transistor, the grid of the tenth two-transistor, the grid of the 9th transistor, the second electrode of the 14 transistor, the grid of the 16 transistor are connected, as the output terminal COUT of cascaded-output level;
Second electrode of the 9th transistor is connected with the first power lead VDD, the second electrode of the 15 transistor, the grid of the 15 transistor respectively; First electrode of the 9th transistor respectively with output terminal OUT, the second electrode of the tenth transistor, second Electrode connection of the tenth transistor of driver element; First electrode of the tenth transistor is connected with the 3rd power lead VSS; The grid of the tenth transistor respectively with the first electrode of the 15 transistor, the second Electrode connection of the 16 transistor; The grid of the 13 transistor, the grid of the 14 transistor are connected with initialize signal line init respectively.
Preferably, each driver element comprises each driver element and comprises the first ~ the 13 transistor and the first electric capacity;
Second electrode of third transistor is connected with the first power lead VDD; The grid of third transistor, first crystal tube grid, the grid of transistor seconds, the first electrode of the 4th transistor are connected with the first clock cable CLK1 respectively; First electrode of third transistor, the second electrode of the 4th transistor, the second electrode of the tenth transistor, the grid of the 6th transistor are connected with the grid of the 8th transistor respectively; The grid of the 4th transistor, the first electrode of transistor seconds, the second electrode of the 11 transistor, the grid of the 5th transistor are connected with the first end of the first electric capacity respectively;
Second electrode of the first transistor is connected with input end VIN; First electrode of the first transistor respectively with the second electrode of transistor seconds, the second Electrode connection of the 9th transistor;
First electrode of the 9th transistor, the second electrode of the 5th transistor are connected with second clock signal wire CLK2; Second electrode of the second electrode of the first electrode of the 5th transistor, the second end of the first electric capacity, the 6th transistor, the grid of the 9th transistor, the tenth two-transistor is connected with the grid of the 7th transistor respectively; Being connected with second source line VSSL respectively of first electrode of the first electrode of the 11 transistor, the first electrode of the tenth transistor, the 6th transistor, the tenth two-transistor first electrode; The grid of the tenth transistor is the output terminal COUT of cascaded-output level;
Second electrode of the 7th transistor is connected with the first power lead VDD; First electrode of the 7th transistor, the second electrode of the 8th transistor, the second electrode of the 13 transistor are connected with the output terminal OUT of driver element respectively; First electrode of the 8th transistor, the first electrode of the 13 transistor are connected with the 3rd power lead VSS respectively; The grid of the 11 transistor, the grid of the tenth two-transistor, the grid of the 13 transistor connect initialize signal init respectively.
Preferably, each driver element comprises each driver element and comprises the first ~ the 14 transistor and the first electric capacity;
Second electrode of third transistor is connected with the first power lead VDD; The grid of the grid of third transistor, the grid of the first transistor, transistor seconds, the first electrode of the 4th transistor are connected with clock signal clk 1 respectively; Second electrode of the first electrode of third transistor, the second electrode of the 4th transistor, the tenth transistor is connected with the grid of the 6th transistor respectively; The grid of the 4th transistor, the first electrode of transistor seconds, the second electrode of the 11 transistor, the grid of the 5th transistor are connected with the first end of the first electric capacity respectively;
Second electrode of the first transistor is connected with input end VIN; First electrode of the first transistor respectively with the second electrode of transistor seconds, the second Electrode connection of the 9th transistor;
First electrode of the 9th transistor, the second electrode of the 5th transistor are connected with clock cable CLK2 respectively; Second electrode of the first electrode of the 5th transistor, the second end of the first electric capacity, the 6th transistor, the grid of the 9th transistor, the second electrode of the tenth two-transistor, the grid of the 7th transistor, the grid of the 14 transistor are connected with the output terminal COUT of cascaded-output level respectively; First electrode of the 11 transistor, the first electrode of the tenth transistor, the first electrode of the 6th transistor, the first electrode of the tenth two-transistor are connected with second source line VSSL respectively; The grid of the tenth transistor connects the output terminal COUT of cascaded-output level; Grid, the tenth two-transistor grid of the 11 transistor connect initialize signal line init respectively;
Second electrode of the 7th transistor, the grid of the 13 transistor, the second electrode of the 13 transistor are connected with the first power lead VDD; First electrode of the 7th transistor, the second electrode of the 8th transistor are connected with the output terminal OUT of driver element respectively; The grid of the 8th transistor, the first electrode of the 13 transistor respectively with the 14 transistor second Electrode connection; First electrode of the 14 transistor, the first electrode of the 8th transistor are connected with the 3rd power lead VSS.
Compared with prior art, the utility model has the following advantages and beneficial effect:
(1) output module of the gate driver circuit of flat-panel monitor of the present utility model, adopts AC and DC combination drive technology, efficiently avoid the dynamic power consumption that main circuit that output stage brings is wanted, reduces circuit power consumption.
(2) adopt the gate driver circuit of the flat-panel monitor of output module of the present utility model, simple structure, consume transparency area little.
(3) gate driver circuit of flat-panel monitor of the present utility model can realize oem character set type of drive, is applicable to the display screen of higher ppi.
(4) gate driver circuit of flat-panel monitor of the present utility model only can adopt two clock cables, and make circuit structure more simple, peripheral driver is simpler.
Accompanying drawing explanation
Fig. 1 is the multistage gate driver circuit schematic diagram of embodiment of the present utility model.
Fig. 2 is the grid electrode drive circuit structure figure of embodiment 1 of the present utility model.
Fig. 3 is the schematic diagram of the output module of the gate driver circuit of embodiment 1 of the present utility model.
Fig. 4 is the Control timing sequence figure of the gate driver circuit of embodiment 1 of the present utility model.
Fig. 5 is the grid electrode drive circuit structure figure of embodiment 2 of the present utility model.
Fig. 6 is the Control timing sequence figure of the gate driver circuit of embodiment 2 of the present utility model.
Fig. 7 is the grid electrode drive circuit structure figure of embodiment 3 of the present utility model.
Fig. 8 is the Control timing sequence figure of the gate driver circuit of embodiment 3 of the present utility model.
Fig. 9 is the grid electrode drive circuit structure figure of embodiment 4 of the present utility model.
Figure 10 is the Control timing sequence figure of the gate driver circuit of embodiment 4 of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but embodiment of the present utility model is not limited thereto.
Embodiment 1
Fig. 1 is the multistage gate driver circuit schematic diagram of the present embodiment, and gate driver circuit comprises multiple driver elements of cascade.As shown in Figure 2, each driver element comprises transistor T101 ~ T115 and electric capacity C101 ~ C102;
The grid of transistor T103, the grid of transistor T104 are connected with clock cable CLK1 respectively; The drain electrode of transistor T3 is connected with power lead VDD; The source electrode of transistor T3 is connected with the drain electrode of transistor T4; The source electrode of transistor T104 is connected with the drain electrode of transistor T105, the drain electrode of transistor T111, the first end of electric capacity C102, the grid of transistor T108, the grid of transistor T110 respectively; The grid of transistor T105, the grid of transistor T106 are connected with signal input part VIN respectively; The source electrode of transistor T105 is connected with the drain electrode of transistor T106; The source electrode of transistor T106 is connected with the source electrode of second source line VSSL, transistor T111, the source electrode of transistor T113, second end of electric capacity C102, the source electrode of transistor T108, the source electrode of transistor T114 respectively;
The grid of transistor T101, the grid of transistor T102 are connected with clock cable CLK2 respectively; The drain electrode of transistor T101 is connected with input end VIN; The source electrode of transistor T101 is connected with the drain electrode of transistor T102, the drain electrode of transistor T112 respectively; The source electrode of transistor T102 is connected with the drain electrode of transistor T113, the grid of transistor T107, the first end of electric capacity C101 respectively;
The drain electrode of transistor T107 is connected with the source electrode of transistor T112, clock cable CLK3 respectively; The source electrode of transistor T107 is connected with the drain electrode of electric capacity C101 second end, transistor T108, the grid of transistor T112, the grid of transistor T109, the drain electrode of transistor T114 respectively, and tie point is as the output terminal COUT of cascaded-output level;
The drain electrode of transistor T109 is connected with power lead VDD; The source electrode of transistor T109 is connected with the drain electrode of OUT, transistor T115, the drain electrode of transistor T110; The source electrode of transistor T110 is connected with the source electrode of transistor T115, the 3rd power lead VSS respectively; The grid of transistor T113 is connected with the grid of transistor T114, the grid of transistor T115, initialize signal line init respectively.
From description above, the output module of each driver element of gate driver circuit of the flat-panel monitor of the present embodiment comprises cascaded-output level and output stage; Described cascaded-output level is connected with AC signal line, is driven by AC signal; Described output stage is connected with direct current signal line, is driven by direct current signal; Described cascaded-output level is connected with the output stage of the driver element of next stage; The capable pixel of output signal Direct driver of output stage; Fig. 3 is shown in by the schematic diagram of output module; Described control end, using the output signal of cascaded-output level as input signal, controls the on off state of output stage.
The course of work of the present embodiment is as follows:
(1) initialization of gate driver circuit: initialize signal line init is the initialization control line of the gate driver circuit of driver element at different levels, be connected with the grid of T113, T114 and T115, the initialization of T113 control P point, T114 controls the initialization of the output terminal COUT of cascade output stage, the initialization of T115 pipe control output end OUT.Before there is no vision signal, initialize signal line init is high level, CLK1, CLK2, CLK3 are low level, T113, T114, T115 conducting, P point and COUT are pulled down to VSSL, OUT is pulled down to VSS, and T107, T109 pipe at different levels is turned off, and cascaded-output signal and output signal maintain VSSL and VSS; Initialize signal line init keeps low level in the course of work of gate driver circuit.
(2) the grid integrated circuits course of work:
Initialize signal line init becomes low level, and CLK1 control line is high level, opens T103, T104; CLK2 and CLK3 control line is low level, T101, T102 is turned off; VIN is low level, T105, T106 is turned off; Power vd D is to the charging of A point, and charge storage, at storage capacitors C102, makes T108, T110 conducting; T101, T102, T107 keep turning off; Output stage, the output signal of cascaded-output level and the output end signal of output stage export respectively and are: VSSL and VSS; T109, T111, T112 grid is all connected with COUT, and therefore T109, T111, T112 turn off;
CLK2 is high level, opens T101 and T102; CLK1 and CLK3 control line is low level, turns off T103 and T104; VIN is high level, opens T105 and T106, and VIN signal is stored in one end P point place of the first memory capacitance C101 simultaneously, makes T107 conducting; A point is discharged to the second negative level VSSL by T105 and T106, and T108, T110 are turned off, and COUT exports the low level corresponding with CLK3 signal control line, and T109 pipe continues to keep off state, and OUT continues to export VSS;
CLK3 is high level, CLK1 and CLK2 control line is low level, turns off T101, T102, T103 and T104 pipe; Input signal is low level, turns off T105 and T106 pipe, and T108 and T110 pipe keeps turning off, T107 pipe maintenance conducting, and COUT is along with the change of CLK3 signal, and saltus step becomes high level, and P point becomes higher level due to the coupling effect of electric capacity C1; Due to COUT high level, the conducting of T109 pipe, output signal level is VDD.
CLK1 is high level, CLK2 and CLK3 is low level, and input signal VIN is low level, and A point charges to VDD, makes T108, T110 conducting, COUT and OUT exports as low level; When CLK2 control line is high level, CLK1 and CLK3 is low level, and P point is discharged into low level, T105 and T107 pipe is turned off, COUT and OUT keeps exporting as low level, waits for that next VIN signal is come in, just produces the shift signal of high level.
The drain electrode of above-mentioned T109 pipe is connected with direct supply VDD, the drain electrode of T107 pipe is connected with alternating current drive signal CLK3, in the whole grid integrated circuits course of work, the drain electrode of T109 pipe is be connected with direct supply all the time, avoid the dynamic power consumption be connected with alternating current drive signal, considerably reduce the power consumption of grid integrated circuits.
The high level of CLK1, CLK2, CLK3 of the present embodiment is higher than VDD, ensures that T109 pipe has enough capable transport VDD.
Fig. 4 is the Control timing sequence figure of the multistage gate driver circuit of the present embodiment, the output signal that in figure, OUT (1) is first order driver element, the output signal of OUT (2) second level driver element.
Embodiment 2
The gate driver circuit of the present embodiment comprises multiple driver elements of cascade, and as shown in Figure 5, each driver element of each driver element comprises transistor T201 ~ T216 and electric capacity C201 ~ C202;
The grid of transistor T203, the grid of transistor T204 are connected with the first clock cable CLK1 respectively; The drain electrode of transistor T203 is connected with the first power lead VDD; The source electrode of transistor T203 is connected with the drain electrode of transistor T204; The source electrode of transistor T204 is connected with the drain electrode of transistor T205, the drain electrode of transistor T211, the first end of electric capacity C202, the grid of transistor T208, the grid of transistor T210 respectively; The grid of transistor T205, the grid of transistor T206 are connected with input end VIN respectively; The source electrode of transistor T205 is connected with the drain electrode of transistor T206; The source electrode of transistor T206 is connected with the source electrode of second source line VSSL, transistor T211, the source electrode of transistor T213, second end of electric capacity C202, the source electrode of transistor T208, the source electrode of transistor T214, the source electrode of transistor T216 respectively;
The grid of transistor T201, the grid of transistor T202 are connected with second clock signal wire CLK2 respectively; The drain electrode of transistor T201 is connected with input end VIN; The source electrode of transistor T201 is connected with the drain electrode of the drain electrode of transistor T202, transistor T212; The source electrode of transistor T202 is connected with the drain electrode of transistor T213, the grid of transistor T207, the first end of electric capacity C201 respectively;
The drain electrode of transistor T207 is connected with transistor T212 source electrode, the 3rd clock cable CLK3 respectively; The drain electrode of the source electrode of transistor T207 and second end of electric capacity C201, transistor T208, the grid of transistor T212, the grid of transistor T209, the drain electrode of transistor T214, the grid of transistor T216 are connected, as the output terminal COUT of cascaded-output level;
The drain electrode of transistor T209 is connected with the drain electrode of power lead VDD, transistor T215, the grid of transistor T215 respectively; The source electrode of transistor T209 is connected with the output terminal OUT of output stage, the drain electrode of transistor T210, the drain electrode of transistor T210 respectively; Transistor T210 source electrode is connected with the 3rd power lead VSS; Transistor T210 grid is connected with the source electrode of transistor T215, the drain electrode of transistor T216 respectively; The grid of transistor T213, the grid of transistor T214 are connected with initialize signal line init respectively.
The grid of the transistor T10 of the present embodiment adopts non-gate control, not gate be input as COUT, can realize oem character set type of drive, the concrete course of work is as follows:
(1) initialize signal line init is the initialization control line of the gate driver circuit of driver element at different levels, be connected with the grid of T213, T214, the initialization of T213 and T214 control P point and COUT respectively, the non-gate control that the initialization of OUT is made up of T213 and T214.Before there is no vision signal, init high level, CLK1, CLK2, CLK3 are low level, the conducting of T215 pipe, P point and COUT are pulled down to VSSL, and T207 pipe at different levels is turned off, because cascaded-output signal is low level, the not gate that T213 and T214 is formed exports high level, the conducting of T210 pipe, and output signal OUT is pulled down to VSS.Init keeps low level in the grid integrated circuits course of work.
(2) the grid integrated circuits course of work.Init becomes low level, and CLK1 is high level, opens T203, T204; CLK2 and CLK3 is low level, T201, T202 is turned off; VIN is low level, T205, T206 is turned off; Power vd D is to the charging of A point, and charge storage, at storage capacitors C202, makes T208 conducting; T201, T202, T207 turn off; COUT and OUT exports respectively and is: VSSL and VSS; COUT is low level, and make the conducting of T210 pipe, T209, T211, T212 grid is all connected with COUT, and therefore T209, T211, T212 turn off.CLK1 becomes low level, now CLK2 and CLK3 or low level state, and P point remains low level, and A point remains high level, makes output stage signal be VSS.
CLK2 is high level, opens T201 and T202; CLK1 and CLK3 is low level, turns off T203 and T204; VIN is high level, opens T205 and T206, and VIN signal is stored in one end P point place of the first memory capacitance C201 simultaneously, makes T207 conducting; A point is discharged to the second negative level VSSL by T205 and T206, and T208 is turned off, and COUT exports the low level corresponding with CLK3, and T209 pipe continues to keep off state, and T210 pipe keeps conducting, and output signal OUT continues to export VSS.CLK2 is low level, now CLK1 and CLK3 or low level state, and P point remains high level, and A point remains low level, and COUT is that VSSL, OUT export as VSS.
CLK3 is high level, CLK1 and CLK2 is low level, turns off T201, T202, T203 and T204 pipe; Input signal is low level, turns off T205 and T206 pipe, and T208 and T210 pipe keeps turning off, T7 pipe maintenance conducting, and COUT is along with the change of CLK3 signal, and saltus step becomes high level, and P point becomes higher level due to the coupling effect of electric capacity C201; Due to COUT high level, the conducting of T209 pipe, T210 pipe turns off, and output signal level is VDD.When CLK3 becomes low level, CLK1 and CLK2 maintains low level, and now P point also maintains this high level, and T7 maintains conducting, makes COUT become VSSL, and T209 pipe turns off, the conducting of T210 pipe, exports VSS.
Fig. 6 is the Control timing sequence figure of the multistage gate driver circuit of the present embodiment, the output signal that in figure, OUT (1) is first order driver element, the output signal of OUT (2) second level driver element.The output waveform of the every one-level of multistage gate driver circuit of the present embodiment, across the time of a recurrence interval, therefore can realize oem character set type of drive, be applicable to the display screen of higher ppi.
Embodiment 3
The gate driver circuit of the present embodiment comprises multiple driver elements of cascade, and as shown in Figure 7, each driver element of each driver element comprises each driver element and comprises transistor T301 ~ T313 and the first electric capacity;
The drain electrode of transistor T303 is connected with the first power lead VDD; The grid of transistor T303, transistor T301 grid, the grid of transistor T302, the source electrode of transistor T304 are connected with the first clock cable CLK1 respectively; The source electrode of transistor T303, the drain electrode of transistor T304, the drain electrode of transistor T310, the grid of transistor T306 are connected with the grid of transistor T308 respectively; The grid of transistor T304, the source electrode of transistor T302, the drain electrode of transistor T311, the grid of transistor T305 are connected with the first end of the first electric capacity respectively;
The drain electrode of transistor T301 is connected with input end VIN; The source electrode of transistor T301 is connected with the drain electrode of transistor T302, the drain electrode of transistor T309 respectively;
The source electrode of transistor T309, the drain electrode of transistor T305 are connected with second clock signal wire CLK2; The drain electrode of the source electrode of transistor T305, the second end of the first electric capacity, transistor T306, the grid of transistor T309, the drain electrode of transistor T312 are connected with the grid of transistor T307 respectively; Being connected with second source line VSSL respectively of the source electrode of the source electrode of transistor T311, the source electrode of transistor T310, transistor T306, transistor T312 source electrode; The grid of transistor T310 is the output terminal COUT of cascaded-output level;
The drain electrode of transistor T307 is connected with the first power lead VDD; The drain electrode of the source electrode of transistor T307, the drain electrode of transistor T308, transistor T313 is connected with the output terminal OUT of output stage respectively; The source electrode of transistor T308, the source electrode of transistor T313 are connected with the 3rd power lead VSS respectively; The grid of the grid of transistor T311, the grid of transistor T312, transistor T313 connects initialize signal init respectively.
Fig. 8 is the Control timing sequence figure of the multistage gate driver circuit of the present embodiment, the output signal that in figure, OUT (1) is first order driver element, the output signal of OUT (2) second level driver element.
In the present embodiment, the high level of CLK1 and CKL2 is higher than the VDD in circuit.
The present embodiment only adopts two clock cables, and make circuit structure more simple, peripheral driver is simpler.
Embodiment 4
The gate driver circuit of the present embodiment comprises multiple driver elements of cascade, and as shown in Figure 9, each driver element comprises each driver element and comprises transistor T401 ~ T414 and electric capacity C401;
The drain electrode of transistor T403 is connected with the first power lead VDD; The grid of transistor T403, the grid of transistor T401, the grid of transistor T402, the source electrode of transistor T404 are connected with clock signal clk 1 respectively; The drain electrode of the source electrode of transistor T403, the drain electrode of transistor T404, transistor T410 is connected with the grid of transistor T406 respectively; The grid of transistor T404, the source electrode of transistor T402, the drain electrode of transistor T411, the grid of transistor T405 are connected with the first end of electric capacity C401 respectively;
The drain electrode of transistor T401 is connected with input end VIN; The source electrode of transistor T401 is connected with the drain electrode of transistor T402, the drain electrode of transistor T409 respectively;
The source electrode of transistor T409, the drain electrode of transistor T405 are connected with clock cable CLK2 respectively; The drain electrode of the drain electrode of the source electrode of transistor T405, second end of electric capacity C401, transistor T406, the grid of transistor T409, transistor T412, the grid of transistor T407, the grid of transistor T414 are connected with the output terminal COUT of cascaded-output level respectively; The source electrode of the source electrode of transistor T411, the source electrode of transistor T410, transistor T406, the source electrode of transistor T412 are connected with second source line VSSL respectively; The grid of transistor T410 connects the output terminal COUT of cascaded-output level; Grid, the transistor T412 grid of transistor T411 connect initialize signal line init respectively;
The drain electrode of the drain electrode of transistor T407, the grid of transistor T413, transistor T413 is connected with the first power lead VDD; The source electrode of transistor T407, the drain electrode of transistor T408 are connected with the output terminal OUT of output stage respectively; The grid of transistor T408, the source electrode of transistor T413 drain with transistor T414 respectively and are connected; The source electrode of transistor T414, the source electrode of transistor T408 are connected with the 3rd power lead VSS.
In the present embodiment, the high level of CLK1 and CKL2 is higher than the VDD in circuit.
Figure 10 is the Control timing sequence figure of the multistage gate driver circuit of the present embodiment, the output signal that in figure, OUT (1) is first order driver element, the output signal of OUT (3) third level driver element.Originally be embodied as the improvement of embodiment 3, adopt non-gate control T10 to manage, the mode of the bilateral driving of odd even can be realized.
Source electrode in above-described embodiment, drain electrode can be exchanged.
Above-described embodiment is the utility model preferably embodiment; but embodiment of the present utility model is not limited by the examples; change, the modification done under other any does not deviate from Spirit Essence of the present utility model and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection domain of the present utility model.
Claims (10)
1. the low-power consumption output module of the gate driver circuit of flat-panel monitor, comprises the output module of multiple driver elements of cascade, it is characterized in that, the output module of each driver element comprises cascaded-output level, output stage and control end; Described cascaded-output level is connected with AC signal line, is driven by AC signal; Described output stage is connected with direct current signal line, is driven by direct current signal; Described cascaded-output level is connected with the output stage of the driver element of next stage; The capable pixel of output signal Direct driver of output stage; Described control end, using the output signal of cascaded-output level as input signal, controls the on off state of output stage.
2. the gate driver circuit of flat-panel monitor, comprises multiple driver elements of cascade, it is characterized in that, comprises low-power consumption output module according to claim 1.
3. the gate driver circuit of flat-panel monitor according to claim 2, is characterized in that, each driver element comprises the first ~ the 15 transistor and the first ~ the second electric capacity;
The grid of third transistor, the grid of the 4th transistor are connected with the first clock cable CLK1 respectively; Second electrode of third transistor is connected with the first power lead VDD; First electrode of third transistor and the second Electrode connection of the 4th transistor; First electrode of the 4th transistor is connected with the second electrode of the 5th transistor, the second electrode of the 11 transistor, the first end of the second electric capacity, the grid of the 8th transistor, the grid of the tenth transistor respectively; The grid of the 5th transistor, the grid of the 6th transistor are connected with signal input part VIN respectively; First electrode of the 5th transistor and the second Electrode connection of the 6th transistor; First electrode of the 6th transistor respectively with the first electrode, the first electrode of the 13 transistor, the second end of the second electric capacity, the first electrode of the 8th transistor, first Electrode connection of the 14 transistor of second source line VSSL, the 11 transistor;
The grid of the first transistor, the grid of transistor seconds are connected with second clock signal wire CLK2 respectively; Second electrode of the first transistor is connected with input end VIN; First electrode of the first transistor respectively with the second electrode of transistor seconds, the second Electrode connection of the tenth two-transistor; First electrode of transistor seconds is connected with the second electrode of the 13 transistor, the grid of the 7th transistor, the first end of the first electric capacity respectively;
Second electrode of the 7th transistor is connected with the first electrode of the tenth two-transistor, the 3rd clock cable CLK3 respectively; First electrode of the 7th transistor respectively with the second electrode, the grid of the tenth two-transistor, the grid of the 9th transistor, second Electrode connection of the 14 transistor of the first electric capacity second end, the 8th transistor, tie point is as the output terminal COUT of cascaded-output level;
Second electrode of the 9th transistor is connected with the first power lead VDD; First electrode of the 9th transistor and the output terminal OUT of driver element, the second electrode of the 15 transistor, the second Electrode connection of the tenth transistor; First electrode of the tenth transistor is connected with the first electrode of the 15 transistor, the 3rd power lead VSS respectively; The grid of the 13 transistor is connected with the grid of the 14 transistor, the grid of the 15 transistor, initialize signal line init respectively.
4. the gate driver circuit of flat-panel monitor according to claim 3, is characterized in that, described first electrode is source electrode, and the second electrode is drain electrode; Or
Second electrode is source electrode, and the first electrode is drain electrode.
5. the gate driver circuit of flat-panel monitor according to claim 2, is characterized in that, each driver element comprises the first ~ the 16 transistor and the first ~ the second electric capacity;
The grid of third transistor, the grid of the 4th transistor are connected with the first clock cable CLK1 respectively; Second electrode of third transistor is connected with the first power lead VDD; First electrode of third transistor and the second Electrode connection of the 4th transistor; First electrode of the 4th transistor is connected with the second electrode of the 5th transistor, the second electrode of the 11 transistor, the first end of the second electric capacity, the grid of the 8th transistor, the grid of the tenth transistor respectively; The grid of the 5th transistor, the grid of the 6th transistor are connected with input end VIN respectively; First electrode of the 5th transistor and the second Electrode connection of the 6th transistor; First electrode of the 6th transistor respectively with the first electrode, the first electrode of the 13 transistor, the second end of the second electric capacity, the first electrode of the 8th transistor, the first electrode of the 14 transistor, first Electrode connection of the 16 transistor of second source line VSSL, the 11 transistor;
The grid of the first transistor, the grid of transistor seconds are connected with second clock signal wire CLK2 respectively; Second electrode of the first transistor is connected with input end VIN; Second Electrode connection of the first electrode of the first transistor and the second electrode of transistor seconds, the tenth two-transistor; First electrode of transistor seconds is connected with the second electrode of the 13 transistor, the grid of the 7th transistor, the first end of the first electric capacity respectively;
Second electrode of the 7th transistor is connected with the tenth two-transistor first electrode, the 3rd clock cable CLK3 respectively; Second electrode of the first electrode of the 7th transistor and the second end of the first electric capacity, the 8th transistor, the grid of the tenth two-transistor, the grid of the 9th transistor, the second electrode of the 14 transistor, the grid of the 16 transistor are connected, as the output terminal COUT of cascaded-output level;
Second electrode of the 9th transistor is connected with the first power lead VDD, the second electrode of the 15 transistor, the grid of the 15 transistor respectively; First electrode of the 9th transistor respectively with output terminal OUT, the second electrode of the tenth transistor, second Electrode connection of the tenth transistor of driver element; First electrode of the tenth transistor is connected with the 3rd power lead VSS; The grid of the tenth transistor respectively with the first electrode of the 15 transistor, the second Electrode connection of the 16 transistor; The grid of the 13 transistor, the grid of the 14 transistor are connected with initialize signal line init respectively.
6. the gate driver circuit of flat-panel monitor according to claim 5, is characterized in that,
Described first electrode is source electrode, and the second electrode is drain electrode; Or
Second electrode is source electrode, and the first electrode is drain electrode.
7. the gate driver circuit of flat-panel monitor according to claim 2, is characterized in that, each driver element comprises each driver element and comprises the first ~ the 13 transistor and the first electric capacity;
Second electrode of third transistor is connected with the first power lead VDD; The grid of third transistor, first crystal tube grid, the grid of transistor seconds, the first electrode of the 4th transistor are connected with the first clock cable CLK1 respectively; First electrode of third transistor, the second electrode of the 4th transistor, the second electrode of the tenth transistor, the grid of the 6th transistor are connected with the grid of the 8th transistor respectively; The grid of the 4th transistor, the first electrode of transistor seconds, the second electrode of the 11 transistor, the grid of the 5th transistor are connected with the first end of the first electric capacity respectively;
Second electrode of the first transistor is connected with input end VIN; First electrode of the first transistor respectively with the second electrode of transistor seconds, the second Electrode connection of the 9th transistor;
First electrode of the 9th transistor, the second electrode of the 5th transistor are connected with second clock signal wire CLK2; Second electrode of the second electrode of the first electrode of the 5th transistor, the second end of the first electric capacity, the 6th transistor, the grid of the 9th transistor, the tenth two-transistor is connected with the grid of the 7th transistor respectively; Being connected with second source line VSSL respectively of first electrode of the first electrode of the 11 transistor, the first electrode of the tenth transistor, the 6th transistor, the tenth two-transistor first electrode; The grid of the tenth transistor is the output terminal COUT of cascaded-output level;
Second electrode of the 7th transistor is connected with the first power lead VDD; First electrode of the 7th transistor, the second electrode of the 8th transistor, the second electrode of the 13 transistor are connected with the output terminal OUT of driver element respectively; First electrode of the 8th transistor, the first electrode of the 13 transistor are connected with the 3rd power lead VSS respectively; The grid of the 11 transistor, the grid of the tenth two-transistor, the grid of the 13 transistor connect initialize signal init respectively.
8. the gate driver circuit of flat-panel monitor according to claim 7, is characterized in that,
Described first electrode is source electrode, and the second electrode is drain electrode; Or
Second electrode is source electrode, and the first electrode is drain electrode.
9. the gate driver circuit of flat-panel monitor according to claim 2, is characterized in that, each driver element comprises each driver element and comprises the first ~ the 14 transistor and the first electric capacity;
Second electrode of third transistor is connected with the first power lead VDD; The grid of the grid of third transistor, the grid of the first transistor, transistor seconds, the first electrode of the 4th transistor are connected with clock signal clk 1 respectively; Second electrode of the first electrode of third transistor, the second electrode of the 4th transistor, the tenth transistor is connected with the grid of the 6th transistor respectively; The grid of the 4th transistor, the first electrode of transistor seconds, the second electrode of the 11 transistor, the grid of the 5th transistor are connected with the first end of the first electric capacity respectively;
Second electrode of the first transistor is connected with input end VIN; First electrode of the first transistor respectively with the second electrode of transistor seconds, the second Electrode connection of the 9th transistor;
First electrode of the 9th transistor, the second electrode of the 5th transistor are connected with clock cable CLK2 respectively; Second electrode of the first electrode of the 5th transistor, the second end of the first electric capacity, the 6th transistor, the grid of the 9th transistor, the second electrode of the tenth two-transistor, the grid of the 7th transistor, the grid of the 14 transistor are connected with the output terminal COUT of cascaded-output level respectively; First electrode of the 11 transistor, the first electrode of the tenth transistor, the first electrode of the 6th transistor, the first electrode of the tenth two-transistor are connected with second source line VSSL respectively; The grid of the tenth transistor connects the output terminal COUT of cascaded-output level; Grid, the tenth two-transistor grid of the 11 transistor connect initialize signal line init respectively;
Second electrode of the 7th transistor, the grid of the 13 transistor, the second electrode of the 13 transistor are connected with the first power lead VDD; First electrode of the 7th transistor, the second electrode of the 8th transistor are connected with the output terminal OUT of driver element respectively; The grid of the 8th transistor, the first electrode of the 13 transistor respectively with the 14 transistor second Electrode connection; First electrode of the 14 transistor, the first electrode of the 8th transistor are connected with the 3rd power lead VSS.
10. the gate driver circuit of flat-panel monitor according to claim 9, is characterized in that, described first electrode is source electrode, and the second electrode is drain electrode; Or
Second electrode is source electrode, and the first electrode is drain electrode.
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| CN201420256515.3U CN204066681U (en) | 2014-05-19 | 2014-05-19 | The gate driver circuit of flat-panel monitor and low-power consumption output module thereof |
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| CN201420256515.3U CN204066681U (en) | 2014-05-19 | 2014-05-19 | The gate driver circuit of flat-panel monitor and low-power consumption output module thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104008717A (en) * | 2014-05-19 | 2014-08-27 | 华南理工大学 | Grid drive circuit of flat-panel display and low-power-consumption output module thereof |
| CN107134246A (en) * | 2017-05-18 | 2017-09-05 | 华南理工大学 | A kind of drive element of the grid and row gated sweep driver and its driving method |
-
2014
- 2014-05-19 CN CN201420256515.3U patent/CN204066681U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104008717A (en) * | 2014-05-19 | 2014-08-27 | 华南理工大学 | Grid drive circuit of flat-panel display and low-power-consumption output module thereof |
| CN104008717B (en) * | 2014-05-19 | 2016-05-04 | 华南理工大学 | The gate driver circuit of flat-panel monitor and low-power consumption output module thereof |
| CN107134246A (en) * | 2017-05-18 | 2017-09-05 | 华南理工大学 | A kind of drive element of the grid and row gated sweep driver and its driving method |
| CN107134246B (en) * | 2017-05-18 | 2023-09-26 | 华南理工大学 | Gate driving unit, row gate scanning driver and driving method thereof |
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