CN105931601A - Drive circuit unit, driving method thereof and row grid driving integrated circuit - Google Patents
Drive circuit unit, driving method thereof and row grid driving integrated circuit Download PDFInfo
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- CN105931601A CN105931601A CN201610504990.1A CN201610504990A CN105931601A CN 105931601 A CN105931601 A CN 105931601A CN 201610504990 A CN201610504990 A CN 201610504990A CN 105931601 A CN105931601 A CN 105931601A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
Abstract
The invention discloses a drive circuit unit, a driving method thereof and a row grid driving integrated circuit, wherein the row grid driving integrated circuit is formed by a power supply, a clock portion and an N-grade cascade grid driving portion, each grade of the grid driving portion comprises a first drive circuit unit, a second drive circuit unit and a third drive circuit unit, and each drive circuit unit comprises an input module, an inverter module, a buffer memory module, a transmission module and a driving output module. In the output modules, the dynamic coupling power consumption of the circuit is substantially reduced by using dc source driving large-size film transistors. The circuit driving only employs low-level clock signals, high voltage after capacitance bootstrap coupling drives the grids of output transistors, and full amplitude output of the voltage is realized.
Description
Technical field
The present invention relates to the row gated sweep field of active matrix light-emitting flat-panel monitor, be specifically related to a kind of drive circuit unit and driving method thereof and row grid-driving integrated circuit.
Background technology
In flat display field, active active illuminating display is the most all the technology of main flow, and the circuit of the driving row and column pixel being integrated on display pannel is the core technology of active active illuminating display.In traditional drive scheme design, need special chip is fitted on panel the driving carrying out each row each row pixel by COG technique, in recent years, development along with technology, utilize transistor to be directly integrated drive circuit in display floater to replace driving chip, it is possible to reduce additional technique, reduce cost, particularly apply and in flexible display panels, it is possible to increase the stability of device and reliability.Row gated sweep integrated circuit is integrated in the grid in order to drive the transistor controlling data-signal write in image element circuit line by line of display floater side, opens it so that data write, and is turned off so that data latch.
Emerging oxide thin film transistor is the popular research object of IC-components in recent years.Application oriented oxide semiconductor element is all N-type, and has the advantages that threshold voltage is negative value.Traditional novel row turntable driving integrated circuit is to utilize clock signal to drive output transistor mostly, but the parasitic capacitance of output transistor is the biggest, because its size sufficiently large just will can have suitable driving force, therefore, the Dynamic Coupling power consumption of circuit is the biggest.Along with the development of movable equipment technology, having higher requirement low-power consumption Display Technique, the power consumption reducing row integrated drive electronics is of great importance to improving Consumer's Experience.Additionally, above-mentioned drive scheme is it is generally required to the clock signal drive circuit of two kinds of low level types, integrated circuit peripheral drives design comparison trouble.Although and the line integrated circuit power dissipation ratio of some other dc source driving output transistor is relatively low, but the high voltage drive transistor gate after coupling can not be utilized, drive output voltage not high enough.
Summary of the invention
In order to overcome shortcoming that prior art exists with not enough, primary and foremost purpose of the present invention is to provide a kind of drive circuit unit, utilizes dc source to drive large-sized output transistor, thus reduces the power consumption of circuit.
Another object of the present invention is to provide the driving method of a kind of drive circuit unit, uses a kind of low level clock signal to drive, and can utilize the driving method of high drive output transistor gates after coupling simultaneously.
Third object of the present invention is to provide a kind of row grid-driving integrated circuit.
The present invention adopts the following technical scheme that
A kind of drive circuit unit, including input module, inverter modules, cache module, transfer module, driving output module, the first power input port VDD, second source input port VSS, the 3rd power input port VSSL, the first clock input port CLK1, second clock input port CLK2, the 3rd clock input port CLK3, the first output port COUT, the second output port OUT and triggering signal port IN；
Described input module is made up of the first transistor and transistor seconds, the drain electrode of described the first transistor and transistor seconds is connected with triggering signal port IN, the grid of the first transistor and the first clock input port CLK1 connect, the grid of described transistor seconds and the 3rd clock input port CLK3 connect, and the source electrode of described transistor seconds and the source electrode of the first transistor are connected as storage electric charge M node；
Described inverter modules is made up of third transistor and the 4th transistor, the drain electrode of described third transistor is connected with the first power input port VDD, the grid of third transistor and the first clock input port CLK1 connect, the source electrode of described third transistor and the drain electrode of the 4th transistor connect and compose anti-phase output node QB, the source electrode of described 4th transistor and the first clock input port CLK1 connect, and the grid of described 4th transistor is connected with cache module output node Q；
Described cache module is made up of the five, the six, the 7th and the 8th transistor and the first electric capacity, the drain electrode of described 5th transistor is connected with second clock input port CLK2, one end of the grid of the 5th transistor, the grid of the 6th transistor and the first electric capacity is all connected with storage electric charge M node, and the source electrode of described 6th transistor, the drain electrode of the 7th transistor are connected with cache module output node Q with the other end of the first electric capacity；The described grid of the 7th transistor and the grid of the 8th transistor are connected with reverse output node QB, and the drain electrode of described 8th transistor is connected with the 3rd power input port VSSL；
Described transfer module is by the 9th transistor, tenth transistor, 11st transistor and the second electric capacity are constituted, the described drain electrode of the 9th transistor and the drain electrode of the 11st transistor are connected with the 3rd clock input port CLK3, the grid of the 9th transistor and one end of the second electric capacity are connected with output node Q, the source electrode of the 9th transistor, the other end of the second electric capacity, the source electrode of the tenth transistor and the grid of the 11st transistor are connected with the first output port COUT respectively, the grid of the tenth transistor is connected with reverse output node QB, the drain electrode of the tenth transistor is connected with the 3rd power input port VSSL, the source electrode of described 5th transistor, the drain electrode of the 6th transistor, the source electrode of the 7th transistor and the source electrode of the source electrode of the 8th transistor and the 11st transistor connect；
Described output module is made up of the tenth two-transistor and the 13rd transistor, the drain electrode of described tenth two-transistor is connected with the first power input port VDD, the grid of described tenth two-transistor is connected with output node Q, the source electrode of described tenth two-transistor and the source electrode of the 13rd transistor are connected as the second output port OUT, the drain electrode of described 13rd transistor is connected with second source input port VSS, and the grid of described 13rd transistor is connected with anti-phase output node QB.
A kind of row grid-driving integrated circuit, power supply and clock part and N level the raster data model part cascaded is constituted, and described N is natural number, and every one-level raster data model part is made up of first, second and third drive circuit unit；
Described power supply and clock portion are divided and are included three clock pin, three DC voltage lead-in wires and trigger pulse lead-in wire VIN, described three clock pin are specially the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3, and described three DC voltages lead-in wire is respectively the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL；
Specifically it is connected as:
First power input port VDD of each drive circuit unit, second source input port VSS, the 3rd power input port VSSL are connected with the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL of clock part with power supply respectively；
Wherein, the triggering signal port IN of the first drive circuit unit of first order raster data model part is connected with triggering pulse lead-in wire VIN；
First output port COUT of the first drive circuit unit and the start pulse signal port IN of the second drive circuit unit connects, first output port COUT of described second drive circuit unit and the start pulse signal port IN of the 3rd drive circuit unit connects, and the first output port COUT of described 3rd drive circuit unit is connected with the start pulse signal port IN of the first drive circuit unit of next stage raster data model part；
In every one-level raster data model part:
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described first drive circuit unit is connected with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described second drive circuit unit is connected with the 3rd clock pin CK3, the first clock pin CK1 and second clock lead-in wire CK2 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described 3rd drive circuit unit respectively with second clock go between CK1, the first clock pin CK1 and the 3rd clock pin CK3.
A kind of row grid-driving integrated circuit, including being symmetrically distributed in display both sides for the odd-numbered line grid-driving integrated circuit driving display line number to be odd number, and for the even number line grid-driving integrated circuit driving display line number to be even number；
The raster data model part that described odd-numbered line grid-driving integrated circuit and even number line grid-driving integrated circuit are cascaded by power supply and clock part and N level is constituted, described N is natural number, and every one-level raster data model part is made up of first, second and third drive circuit unit；
Described power supply and clock portion are divided and are included three clock pin, three DC voltage lead-in wires and trigger pulse lead-in wire VIN, described three clock pin are specially the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3, and described three DC voltages lead-in wire is respectively the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL；
In odd-numbered line grid-driving integrated circuit and even number line grid-driving integrated circuit, the first power input port VDD of each drive circuit unit, second source input port VSS, the 3rd power input port VSSL are connected with the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL of clock part with power supply respectively；
Wherein, the triggering signal port IN of the first drive circuit unit of first order raster data model part is connected with triggering pulse lead-in wire VIN；
First output port COUT of the first drive circuit unit and the start pulse signal port IN of the second drive circuit unit connects, first output port COUT of described second drive circuit unit and the start pulse signal port IN of the 3rd drive circuit unit connects, and the first output port COUT of described 3rd drive circuit unit is connected with the start pulse signal port IN of the first drive circuit unit of next stage raster data model part；
Wherein, odd-numbered line grid-driving integrated circuit:
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described first drive circuit unit is connected with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described second drive circuit unit is connected with the 3rd clock pin CK3, the first clock pin CK1 and second clock lead-in wire CK2 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described 3rd drive circuit unit respectively with second clock go between CK1, the first clock pin CK1 and the 3rd clock pin CK3；
Wherein, in even number line grid-driving integrated circuit:
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described first drive circuit unit is connected with second clock lead-in wire CK2, the 3rd clock pin CK3 and the first clock pin CK1 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described second drive circuit unit draws with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock respectively
Line CK3 connects；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described 3rd drive circuit unit respectively with the 3rd clock pin CK3, the first clock pin CK1 and second clock go between CK2.
The driving method of a kind of drive circuit unit, comprises the steps:
In following, high level is high level corresponding to the first DC voltage lead-in wire VD, and the first low level is low level corresponding to the second DC voltage lead-in wire VS, and the second low level is low level corresponding to the 3rd DC voltage lead-in wire VL；
Charging: triggering signal port IN and input a high level signal, the first clock input port CLK1 becomes high level, and the first transistor is opened, the charging of M node becomes high level, and electric charge is stored in the first electric capacity；
Caching: trigger signal port IN and input a low level, first clock input port CLK1 becomes low level, the first transistor, third transistor are turned off, simultaneously, second clock becomes high level, node Q is electrically charged, and becomes high level, and electric charge is stored in the second electric capacity, 4th transistor is opened, node QB is discharged, and becomes low level, by the gate turn-off of the seven, the eight, ten and 13 transistors, nine, the ten two-transistors are opened, first output port COUT output low level, the second output port OUT starts precharge, and voltage starts slowly to rise；
Output: the 3rd clock input port CLK3 becomes high level, transistor seconds is opened, M point charge is released, become low level, 5th, six transistors are turned off, second clock input port CLK2 becomes low level, 3rd clock input port CLK3 is driven through the 9th transistor to the first output port COUT charging, first output port COUT exports high level, the high level of the 3rd clock input port feeds back to source electrode and the drain electrode of the 6th transistor of the 5th transistor by the 11st transistor, the drain electrode of the 7th transistor and the source electrode of the 8th transistor, suppression node Q charge leakage, and node Q voltage opens the 9th transistor and the tenth two-transistor, second output port OUT is fully charged to high level, drive the grid of peripheral display screen matrix circuit；
Reset: the first clock input port CLK1 becomes high level, 3rd clock input port CLK3 becomes low level, nine, the ten two-transistors are turned off, seven, the eight, ten, 13 transistors are opened, Q point charge is released, becoming low level, the first output port COUT and the second output port OUT exports the first low-voltage and the second low-voltage respectively.Then this state is continued until that trigger signal becomes high level next time.
Beneficial effects of the present invention:
(1) the row cutting integrated circuit of the present invention uses multiple backfeed loop holding circuits stable, utilizes the large-size crystals pipe of direct voltage drive output module, thus is substantially reduced the Dynamic Coupling power consumption of circuit, is conducive to improving the Consumer's Experience of display device；
(2) driving method of the present invention utilizes pipeline-type clock driver circuit, have only to utilize a kind of low level clock signal to drive whole circuit simultaneously, external drive is required low, the high level after electric capacity bootstrapping coupling can be utilized inside circuit to drive the grid of output transistor, thus realize the Full-swing output of voltage；
(3) circuit can apply the display in monolateral driving to drive in specification, the display in bilateral driving can also be applied to drive in specification, application flexible design, apply in bilateral driving, the waveform of circuit output has half phrase overlap, image element circuit precharge operation can be given, improve display quality.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the row grid-driving integrated circuit of the embodiment of the present invention 1；
Fig. 2 is the circuit diagram of present invention driver circuit unit；
Fig. 3 is the working waveform figure of present invention driver circuit unit；
Fig. 4 is the working waveform figure of the embodiment of the present invention 1；
Fig. 5 is the circuit diagram of the row grid-driving integrated circuit of the embodiment of the present invention 2.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment 1
As shown in Figure 2, a kind of drive circuit unit of the present invention, including input module, inverter modules, cache module, transfer module, driving output module, the first power input port VDD, second source input port VSS, the 3rd power input port VSSL, the first clock input port CLK1, second clock input port CLK2, the 3rd clock input port CLK3, the first output port COUT, the second output port OUT and triggering signal port IN；
Described input module 201 is made up of the first transistor T1 and transistor seconds T2, the drain electrode of described the first transistor and transistor seconds is connected with triggering signal port IN, the grid of the first transistor and the first clock input port CLK1 connect, the grid of described transistor seconds and the 3rd clock input port CLK3 connect, and the source electrode of described transistor seconds and the source electrode of the first transistor are connected as storage electric charge M node；
Described inverter modules 202 is made up of third transistor T3 and the 4th transistor T4, the drain electrode of described third transistor T3 is connected with the first power input port VDD, the grid of third transistor and the first clock input port CLK1 connect, the source electrode of described third transistor and the drain electrode of the 4th transistor T4 connect and compose anti-phase output node QB, the source electrode of described 4th transistor and the first clock input port CLK1 connect, and the grid of described 4th transistor is connected with cache module output node Q；
Described cache module 203 is made up of the five, the six, the 7th and the 8th transistor and the first electric capacity, the drain electrode of described 5th transistor is connected with second clock input port CLK2, one end of the grid of the 5th transistor T5, the grid of the 6th transistor T6 and the first electric capacity C1 is all connected with storage electric charge M node, and the described source electrode of the 6th transistor, the drain electrode of the 7th transistor T7 are connected with cache module output node Q with the first electric capacity other end；The described grid of the 7th transistor T7 and the grid of the 8th transistor T8 are connected with reverse output node QB, and the drain electrode of described 8th transistor T8 is connected with the 3rd power input port VSSL；
Described transfer module 204 is by the 9th transistor T9, tenth transistor T10, 11st transistor T11 and the second electric capacity C2 is constituted, the described drain electrode of the 9th transistor and the drain electrode of the 11st transistor are connected with the 3rd clock input port CLK3, the grid of the 9th transistor T9 and one end of the second electric capacity are connected with output node Q, the source electrode of the 9th transistor, the other end of the second electric capacity, the source electrode of the tenth transistor and the grid of the 11st transistor are connected with the first output port COUT respectively, the grid of the tenth transistor is connected with reverse output node QB, the drain electrode of the tenth transistor is connected with the 3rd power input port VSSL, the source electrode of described 5th transistor, the drain electrode of the 6th transistor, the source electrode of the 7th transistor and the drain electrode of the 8th transistor are connected with the source electrode of the 11st transistor；
Described output module 205 is made up of the tenth two-transistor T12 and the 13rd transistor T13, the drain electrode of described tenth two-transistor T12 is connected with the first power input port VDD, the grid of described tenth two-transistor is connected with output node Q, the source electrode of described tenth two-transistor T12 and the source electrode of the 13rd transistor are connected as the second output port OUT, the drain electrode of described 13rd crystal T13 pipe is connected with second source input port VSS, and the grid of described 13rd transistor is connected with anti-phase output node QB.
As it is shown on figure 3, the driving method of a kind of drive circuit unit, comprise the steps:
In following, high level is high level corresponding to the first DC voltage lead-in wire VD, and the first low level is low level corresponding to the second DC voltage lead-in wire VS, and the second low level is low level corresponding to the 3rd DC voltage lead-in wire VL；
Charging: triggering signal port IN and input a high level signal, the first clock input port CLK1 becomes high level, and the first transistor is opened, the charging of M node becomes high level, and electric charge is stored in the first electric capacity；
Caching: trigger signal port IN and input a low level, first clock input port CLK1 becomes low level, the first transistor, third transistor are turned off, simultaneously, second clock becomes high level, node Q is electrically charged, and becomes high level, and electric charge is stored in the second electric capacity, 4th transistor is opened, node QB is discharged, and becomes low level, by the gate turn-off of the seven, the eight, ten and 13 transistors, nine, the ten two-transistors are opened, first output port COUT output low level, the second output port OUT starts precharge, and voltage starts slowly to rise；
Output: the 3rd clock input port CLK3 becomes high level, transistor seconds is opened, M point charge is released, become low level, 5th, six transistors are turned off, second clock input port CLK2 becomes low level, 3rd clock input port CLK3 is driven through the 9th transistor to the first output port COUT charging, first output port COUT exports high level, the high level of the 3rd clock input port feeds back to source electrode and the drain electrode of the 6th transistor of the 5th transistor by the 11st transistor, the drain electrode of the 7th transistor and the source electrode of the 8th transistor, suppression node Q charge leakage, and node Q voltage opens the 9th transistor and the tenth two-transistor, second output port OUT is fully charged to high level, drive the grid of peripheral display screen matrix circuit；
Reset: the first clock input port CLK1 becomes high level, 3rd clock input port CLK3 becomes low level, nine, the ten two-transistors are turned off, seven, the eight, ten, 13 transistors are opened, Q point charge is released, becoming low level, COUT and OUT node exports the first low-voltage and the second low-voltage respectively.Then this state is continued until that trigger signal becomes high level next time.
As shown in Figure 1, the row grid-driving integrated circuit being made up of drive circuit unit of the present invention, the raster data model part cascaded by power supply and clock part 104 and N level is constituted, described N is natural number, and every one-level raster data model part is made up of first, second and third drive circuit unit 101-103；
Described power supply and clock portion are divided and are included three clock pin, three DC voltage lead-in wires and trigger pulse lead-in wire VIN, described three clock pin are specially the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3, described three DC voltages lead-in wire is respectively the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL, three DC voltages lead-in wire is the driving DC voltage of different magnitude of voltage, and clock signal is that frequency is identical from voltage but impulse phase is different；
Specifically it is connected as:
First power input port VDD of each drive circuit unit, second source input port VSS, the 3rd power input port VSSL are connected with the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL of clock part with power supply respectively, and the triggering signal port IN of the first drive circuit unit of first order raster data model part is connected with triggering pulse lead-in wire VIN；
First output port COUT of the first drive circuit unit 101 and start pulse signal port IN of the second drive circuit unit connects, first output port COUT of described second drive circuit unit and the start pulse signal port IN of the 3rd drive circuit unit connects, and the first output port COUT of described 3rd drive circuit unit is connected with the start pulse signal port IN of the first drive circuit unit of next stage raster data model part；
In every one-level raster data model part:
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described first drive circuit unit 101 is connected with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described second drive circuit unit 102 is connected with the 3rd clock pin CK3, the first clock pin CK1 and second clock lead-in wire CK2 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described 3rd drive circuit unit 103 respectively with second clock go between CK1, the first clock pin CK1 and the 3rd clock pin CK3.
It is illustrated in figure 4 the working waveform figure of this row grid-driving integrated circuit, is driven the image element circuit of display screen by output pulse signal step by step.
Embodiment 2
As shown in Figure 5, row grid-driving integrated circuit is constituted by the drive circuit unit of the present invention, including being symmetrically distributed in display both sides for the odd-numbered line grid-driving integrated circuit driving display line number to be odd number, and for the even number line grid-driving integrated circuit driving display line number to be even number；
The raster data model part that described odd-numbered line grid-driving integrated circuit and even number line grid-driving integrated circuit are cascaded by power supply and clock part and N level is constituted, described N is natural number, and every one-level raster data model part is made up of first, second and third drive circuit unit；
Described power supply and clock portion are divided and are included three clock pin, three DC voltage lead-in wires and trigger pulse lead-in wire VIN, described three clock pin are specially the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3, and described three DC voltages lead-in wire is respectively the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL；
In odd-numbered line grid-driving integrated circuit and even number line grid-driving integrated circuit, first power input port VDD of each drive circuit unit, second source input port VSS, the 3rd power input port VSSL are connected with the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd DC voltage lead-in wire VL of clock part with power supply respectively, and the triggering signal port IN of the first drive circuit unit of first order raster data model part is connected with triggering pulse lead-in wire VIN；
First output port COUT of the first drive circuit unit and the start pulse signal port IN of the second drive circuit unit connects, first output port COUT of described second drive circuit unit and the start pulse signal port IN of the 3rd drive circuit unit connects, and the first output port COUT of described 3rd drive circuit unit is connected with the start pulse signal port IN of the first drive circuit unit of next stage raster data model part；
Wherein, odd-numbered line grid-driving integrated circuit:
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described first drive circuit unit is connected with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described second drive circuit unit is connected with the 3rd clock pin CK3, the first clock pin CK1 and second clock lead-in wire CK2 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described 3rd drive circuit unit respectively with second clock go between CK2, the first clock pin CK1 and the 3rd clock pin CK3；
Wherein, in even number line grid-driving integrated circuit:
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described first drive circuit unit is connected with second clock lead-in wire CK2, the 3rd clock pin CK3 and the first clock pin CK1 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described second drive circuit unit is connected with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock pin CK3 respectively；
First clock input port CLK1, second clock input port CLK2 and the 3rd clock input port CLK3 of described 3rd drive circuit unit respectively with the 3rd clock pin CK3, the first clock pin CK1 and second clock go between CK2.
In the present embodiment, circuit connecting mode drives the image element circuit of display screen by output pulse signal step by step.
The present invention in the output module, utilizes dc source to drive large-sized thin film transistor (TFT), is substantially reduced the Dynamic Coupling power consumption of circuit.Circuit drives drives only with the clock signal of a kind of low level type, and can utilize the grid of the high voltage drive output transistor after electric capacity bootstrapping coupling, it is possible to realize the Full-swing output of voltage.Circuit can be flexibly applied to the display of monolateral driving and bilateral driving and drive in design, applies in bilateral driving, and the waveform of circuit output has half phrase overlap, can give image element circuit precharge operation, improves display quality.
Above-described embodiment is the present invention preferably embodiment; but embodiments of the present invention are also not restricted by the embodiments; the change made under other any Spirit Essence without departing from the present invention and principle, modify, substitute, combine, simplify; all should be the substitute mode of equivalence, within being included in protection scope of the present invention.
Claims (4)
1. a drive circuit unit, it is characterised in that include input module, inverter modules, caching mould
Block, transfer module, driving output module, the first power input port VDD, second source input port VSS,
3rd power input port VSSL, the first clock input port CLK1, second clock input port CLK2, the 3rd time
Clock input port CLK3, the first output port COUT, the second output port OUT and triggering signal port IN；
Described input module is made up of the first transistor and transistor seconds, described the first transistor and the second crystalline substance
The drain electrode of body pipe is connected with triggering signal port IN, the grid of the first transistor and the first clock input port CLK1
Connecting, the grid of described transistor seconds and the 3rd clock input port CLK3 connect, described transistor seconds
The source electrode of source electrode and the first transistor is connected as storage electric charge M node；
Described inverter modules is made up of third transistor and the 4th transistor, the drain electrode of described third transistor
Being connected with the first power input port VDD, the grid of third transistor and the first clock input port CLK1 connect,
The source electrode of described third transistor and the drain electrode of the 4th transistor connect and compose anti-phase output node QB, and described
The source electrode of four transistors and the first clock input port CLK1 connect, the grid of described 4th transistor and caching mould
Block output node Q connects；
Described cache module is made up of the five, the six, the 7th and the 8th transistor and the first electric capacity, and described
The drain electrode of five transistors is connected with second clock input port CLK2, the grid of the 5th transistor, the 6th transistor
Grid and one end of the first electric capacity be all connected with storage electric charge M node, the source electrode of described 6th transistor,
The drain electrode of the 7th transistor is connected with cache module output node Q with the other end of the first electric capacity；Described 7th
The grid of transistor and the grid of the 8th transistor are connected with reverse output node QB, described 8th transistor
Drain electrode is connected with the 3rd power input port VSSL；
Described transfer module is made up of the 9th transistor, the tenth transistor, the 11st transistor and the second electric capacity,
The described drain electrode of the 9th transistor and the drain electrode of the 11st transistor are connected with the 3rd clock input port CLK3, the
The grid of nine transistors and one end of the second electric capacity are connected with output node Q, the source electrode of the 9th transistor,
The grid of the other end of two electric capacity, the source electrode of the tenth transistor and the 11st transistor respectively with the first output
Mouth COUT connects, and the grid of the tenth transistor is connected with reverse output node QB, the drain electrode of the tenth transistor
Be connected with the 3rd power input port VSSL, the source electrode of described 5th transistor, the drain electrode of the 6th transistor,
The source electrode of the 7th transistor and the source electrode of the source electrode of the 8th transistor and the 11st transistor connect；
Described output module is made up of the tenth two-transistor and the 13rd transistor, described tenth two-transistor
Drain electrode is connected with the first power input port VDD, and the grid of described tenth two-transistor is with output node Q even
Connecing, the source electrode of described tenth two-transistor and the source electrode of the 13rd transistor are connected as the second output port
OUT, the drain electrode of described 13rd transistor is connected with second source input port VSS, described 13rd crystal
The grid of pipe is connected with anti-phase output node QB.
2. the row grid-driving integrated circuit being made up of the drive circuit unit described in claim 1, its
It is characterised by,
The raster data model part cascaded by power supply and clock part and N level is constituted, and described N is natural number, often
One-level raster data model part is made up of first, second and third drive circuit unit；
Described power supply and clock portion are divided and are included three clock pin, three DC voltage lead-in wires and trigger pulse drawing
Line VIN, described three clock pin are specially the first clock pin CK1, second clock lead-in wire CK2 and the 3rd
Clock pin CK3, described three DC voltages lead-in wire is respectively the first DC voltage lead-in wire VD, the second direct current
Voltage lead VS and the 3rd DC voltage lead-in wire VL；
Specifically it is connected as:
First power input port VDD of each drive circuit unit, second source input port VSS, the 3rd
Power input port VSSL respectively with the first DC voltage lead-in wire VD, the second direct current of power supply and clock part
Voltage lead wires VS and the 3rd DC voltage lead-in wire VL connects；
Wherein, the triggering signal port IN of the first drive circuit unit of first order raster data model part and triggering
Pulse lead-in wire VIN connects；
First output port COUT of the first drive circuit unit and the triggering pulse letter of the second drive circuit unit
Number port IN connects, the first output port COUT of described second drive circuit unit and the 3rd drive circuit
The start pulse signal port IN of unit connects, the first output port COUT of described 3rd drive circuit unit
It is connected with the start pulse signal port IN of the first drive circuit unit of next stage raster data model part；
In every one-level raster data model part:
First clock input port CLK1, the second clock input port CLK2 of described first drive circuit unit and
Three clock input port CLK3 draw with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock respectively
Line CK3 connects；
First clock input port CLK1, the second clock input port CLK2 of described second drive circuit unit and
Three clock input port CLK3 draw with the 3rd clock pin CK3, the first clock pin CK1 and second clock respectively
Line CK2 connects；
First clock input port CLK1, the second clock input port CLK2 of described 3rd drive circuit unit and
Three clock input port CLK3 draw with second clock lead-in wire CK1, the first clock pin CK1 and the 3rd clock respectively
Line CK3.
3. one kind by the row grid-driving integrated circuit described in claim 1, it is characterised in that include symmetry
It is distributed in display both sides for the odd-numbered line grid-driving integrated circuit driving display line number to be odd number, and
For the even number line grid-driving integrated circuit driving display line number to be even number；
Described odd-numbered line grid-driving integrated circuit and even number line grid-driving integrated circuit are by power supply and clock
The raster data model part of part and the cascade of N level is constituted, and described N is natural number, every one-level raster data model part
It is made up of first, second and third drive circuit unit；
Described power supply and clock portion are divided and are included three clock pin, three DC voltage lead-in wires and trigger pulse drawing
Line VIN, described three clock pin are specially the first clock pin CK1, second clock lead-in wire CK2 and the 3rd
Clock pin CK3, described three DC voltages lead-in wire is respectively the first DC voltage lead-in wire VD, the second direct current
Voltage lead VS and the 3rd DC voltage lead-in wire VL；
In odd-numbered line grid-driving integrated circuit and even number line grid-driving integrated circuit, each drive circuit
First power input port VDD of unit, second source input port VSS, the 3rd power input port VSSL
Straight with the first DC voltage lead-in wire VD, the second DC voltage lead-in wire VS and the 3rd of clock part with power supply respectively
Stream voltage lead VL connects；
Wherein, the triggering signal port IN of the first drive circuit unit of first order raster data model part and triggering
Pulse lead-in wire VIN connects；
First output port COUT of the first drive circuit unit and the triggering pulse letter of the second drive circuit unit
Number port IN connects, the first output port COUT of described second drive circuit unit and the 3rd drive circuit
The start pulse signal port IN of unit connects, the first output port COUT of described 3rd drive circuit unit
It is connected with the start pulse signal port IN of the first drive circuit unit of next stage raster data model part；
Wherein, odd-numbered line grid-driving integrated circuit:
First clock input port CLK1, the second clock input port CLK2 of described first drive circuit unit and
Three clock input port CLK3 draw with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock respectively
Line CK3 connects；
First clock input port CLK1, the second clock input port CLK2 of described second drive circuit unit and
Three clock input port CLK3 draw with the 3rd clock pin CK3, the first clock pin CK1 and second clock respectively
Line CK2 connects；
First clock input port CLK1, the second clock input port CLK2 of described 3rd drive circuit unit and
Three clock input port CLK3 draw with second clock lead-in wire CK1, the first clock pin CK1 and the 3rd clock respectively
Line CK3；
Wherein, in even number line grid-driving integrated circuit:
First clock input port CLK1, the second clock input port CLK2 of described first drive circuit unit and
Three clock input port CLK3 draw with second clock lead-in wire CK2, the 3rd clock pin CK3 and the first clock respectively
Line CK1 connects；
First clock input port CLK1, the second clock input port CLK2 of described second drive circuit unit and
Three clock input port CLK3 draw with the first clock pin CK1, second clock lead-in wire CK2 and the 3rd clock respectively
Line CK3 connects；
First clock input port CLK1, the second clock input port CLK2 of described 3rd drive circuit unit and
Three clock input port CLK3 draw with the 3rd clock pin CK3, the first clock pin CK1 and second clock respectively
Line CK2.
4. the driving method of a kind of drive circuit unit realized described in claim 1, it is characterised in that
Comprise the steps:
In following, high level is high level corresponding to the first DC voltage lead-in wire VD, and the first low level is the
Low level corresponding to two DC voltage lead-in wire VS, the second low level is corresponding to the 3rd DC voltage lead-in wire VL
Low level；
Charging: triggering signal port IN and input a high level signal, the first clock input port CLK1 becomes
High level, the first transistor is opened, and the charging of M node becomes high level, and electric charge is stored in the first electric capacity；
Caching: triggering signal port IN and input a low level, the first clock input port CLK1 becomes low electricity
Flat, the first transistor, third transistor are turned off, and meanwhile, second clock becomes high level, node Q quilt
Charging, becomes high level, and electric charge is stored in the second electric capacity, and the 4th transistor is opened, node QB
It is discharged, becomes low level, by the gate turn-off of the seven, the eight, ten and 13 transistors, the nine, the 12
Transistor is opened, the first output port COUT output low level, and the second output port OUT starts preliminary filling
Electricity, voltage starts slowly to rise；
Output: the 3rd clock input port CLK3 becomes high level, is opened by transistor seconds, M point charge
Being released, become low level, the five, the six transistors are turned off, and second clock input port CLK2 becomes
Low level, the 3rd clock input port CLK3 is driven through the 9th transistor and fills to the first output port COUT
Electricity, the first output port COUT exports high level, and the high level of the 3rd clock input port is brilliant by the 11st
Body pipe feeds back to source electrode and the drain electrode of the 6th transistor of the 5th transistor, the drain electrode and the 8th of the 7th transistor
The source electrode of transistor, suppresses node Q charge leakage, and node Q voltage opens the 9th transistor and the tenth
Two-transistor, the second output port OUT is fully charged to high level, drives peripheral display screen matrix circuit
Grid；
Reset: the first clock input port CLK1 becomes high level, and the 3rd clock input port CLK3 becomes low
Level, the nine, the ten two-transistors are turned off, the seven, the eight, ten, 13 transistors be opened, Q point electricity
Lotus is released, and becomes low level, and the first output port COUT and the second output port OUT node are the most defeated
Going out the first low-voltage and the second low-voltage, then this state is continued until that trigger signal becomes high electricity next time
Flat.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106356034A (en) * | 2016-11-21 | 2017-01-25 | 武汉华星光电技术有限公司 | Drive circuit, array substrate and liquid crystal display |
| CN109243357A (en) * | 2018-11-12 | 2019-01-18 | 中国科学院微电子研究所 | The driving circuit and method of picture element scan |
| CN109285505A (en) * | 2018-11-02 | 2019-01-29 | 北京大学深圳研究生院 | A kind of shift register cell, gate driving circuit and display device |
| CN110800039A (en) * | 2019-09-17 | 2020-02-14 | 京东方科技集团股份有限公司 | GOA unit circuit, driving method, GOA circuit and display device |
| JP2020520038A (en) * | 2017-05-04 | 2020-07-02 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Shift register unit, control method thereof, gate drive circuit, and display device |
| CN113470578A (en) * | 2020-03-31 | 2021-10-01 | 北京小米移动软件有限公司 | Display driving module, display panel and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100245301A1 (en) * | 2009-03-27 | 2010-09-30 | Beijing Boe Optoelectronics Technology Co., Ltd. | Gate drive device for a liquid crystal display |
| CN103187040A (en) * | 2011-12-30 | 2013-07-03 | 海蒂斯技术有限公司 | Shift register and gate driving circuit using the same |
| CN103745680A (en) * | 2013-06-19 | 2014-04-23 | 友达光电股份有限公司 | Shift register module and control method thereof |
| CN103927972A (en) * | 2013-12-05 | 2014-07-16 | 华南理工大学 | Grid drive unit, grid scanning driver and driving method of grid scanning driver |
| CN103943058A (en) * | 2014-04-28 | 2014-07-23 | 华南理工大学 | Line grid scanner and drive method thereof |
| CN205900070U (en) * | 2016-06-28 | 2017-01-18 | 华南理工大学 | Drive circuit unit and gate drive integrated circuit that goes |
-
2016
- 2016-06-28 CN CN201610504990.1A patent/CN105931601B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100245301A1 (en) * | 2009-03-27 | 2010-09-30 | Beijing Boe Optoelectronics Technology Co., Ltd. | Gate drive device for a liquid crystal display |
| CN103187040A (en) * | 2011-12-30 | 2013-07-03 | 海蒂斯技术有限公司 | Shift register and gate driving circuit using the same |
| CN103745680A (en) * | 2013-06-19 | 2014-04-23 | 友达光电股份有限公司 | Shift register module and control method thereof |
| CN103927972A (en) * | 2013-12-05 | 2014-07-16 | 华南理工大学 | Grid drive unit, grid scanning driver and driving method of grid scanning driver |
| CN103943058A (en) * | 2014-04-28 | 2014-07-23 | 华南理工大学 | Line grid scanner and drive method thereof |
| CN205900070U (en) * | 2016-06-28 | 2017-01-18 | 华南理工大学 | Drive circuit unit and gate drive integrated circuit that goes |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106356034A (en) * | 2016-11-21 | 2017-01-25 | 武汉华星光电技术有限公司 | Drive circuit, array substrate and liquid crystal display |
| JP2020520038A (en) * | 2017-05-04 | 2020-07-02 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Shift register unit, control method thereof, gate drive circuit, and display device |
| CN109285505A (en) * | 2018-11-02 | 2019-01-29 | 北京大学深圳研究生院 | A kind of shift register cell, gate driving circuit and display device |
| CN109243357A (en) * | 2018-11-12 | 2019-01-18 | 中国科学院微电子研究所 | The driving circuit and method of picture element scan |
| CN109243357B (en) * | 2018-11-12 | 2021-11-12 | 中国科学院微电子研究所 | Driving circuit and method for pixel scanning |
| CN110800039A (en) * | 2019-09-17 | 2020-02-14 | 京东方科技集团股份有限公司 | GOA unit circuit, driving method, GOA circuit and display device |
| CN110800039B (en) * | 2019-09-17 | 2021-10-08 | 京东方科技集团股份有限公司 | GOA unit circuit, driving method, GOA circuit and display device |
| CN113470578A (en) * | 2020-03-31 | 2021-10-01 | 北京小米移动软件有限公司 | Display driving module, display panel and electronic equipment |
| CN113470578B (en) * | 2020-03-31 | 2022-06-17 | 北京小米移动软件有限公司 | Display driving module, display panel and electronic equipment |
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