CN204046415U - The quick startup control circuit of converter - Google Patents

Abstract

The utility model relates to a kind of quick startup control circuit of converter, and it is characterized in that, described circuit comprises benchmaring unit, sample holding unit, amplifier, modulating unit, output unit and control unit; The first input end input feedback voltage of described control unit, the second input is connected with the output of described benchmaring unit, and the first output is connected with described amplifier with described sample holding unit respectively; The input input supply voltage of described benchmaring unit; The input of described sample holding unit inputs described feedback voltage, and its output is connected with described amplifier; The output of described amplifier is connected with described modulating unit, and the output of described modulating unit is connected with described output unit.The utility model is not changing non-essential resistance and electric capacity, under keeping the prerequisite of less quiescent dissipation and very fast toggle speed, increases up duration, ensures the normal startup of AC/DC converter.

Description

The quick startup control circuit of converter

Technical field

The utility model relates to integrated circuit fields, particularly relates to a kind of quick startup control circuit of converter.

Background technology

Along with the development of LED illumination technology, AC-DC LED driver needs to support higher power output, realizes higher control precision.Under the condition of equal technique, high-speed, high precision controls and larger driving force, and the operating current of driver itself all can be made to improve, and power consumption becomes large.If keep chip exterior start-up circuit power consumption constant, the start-up time of chip can extend greatly; If keep the small-startup time, then need to improve outside start-up circuit electric current, lower efficiency.

Fig. 1 is that the one of the interchange-DC converter of prior art realizes framework.As shown in Figure 1, the alternating voltage of input is carried out shaping by bridge rectifier, and the voltage after shaping is called busbar voltage, namely line voltage Vinsin (wt) is converted into exercisable voltage Vin|sin (wt) |.The auxiliary winding switching of transformer T1 is held to the FB of interchange-DC controller, and controller detects output voltage by FB end.Busbar voltage VM is by resistance R ₁be connected to electric capacity C ₁, meanwhile, auxiliary winding is by diode D ₁be connected to electric capacity C ₁.C ₁the vdd terminal of connection control device, provides power supply to controller.

Fig. 2 is the implementation of the interchange-DC controller of prior art.As shown in Figure 2, the input of controller connects VDD and feedback voltage FB respectively, exports DRV and connects power switch M1.Controller comprises benchmark & VDD detection module, sampling hold circuit, EA amplifier, PWM device and output unit Driver.

Benchmark & VDD detection module, for generation of reference voltage, detects vdd voltage, and whether produce other circuit of Enable signal controlling and work, this module current sinking is designated as I _q1.Sampling hold circuit carries out sampling to feedback signal FB and keeps, and gives EA amplifier and compares with reference voltage Vref, produce error amplification signal, then produces pwm switching signal driving power switch by PWM device, realizes loop and controls.Wherein, sampling hold circuit operating current is designated as I _q2, EA amplifier operation electric current is designated as I _q3, the operating current merging of PWM device and output Driver is designated as I _q4.

Fig. 3 is the startup waveform schematic diagram of the interchange-DC controller of prior art.As shown in Figure 3, the initial voltage of vdd voltage and FB voltage is all 0, and after switching on power, VDD rises from 0V, and now FB voltage is still 0, only has VM by R1 to C ₁charging, charging current is I _cHG, VDD rises to V from 0V _starttime be designated as t ₁.

$I_{\mathrm{CHG}}\≈\frac{\mathrm{VM}}{R_1}$

$t_1=\frac{C_1{V}_{\mathrm{start}}}{I_{\mathrm{CHG}}-I_{Q1}}\≈\frac{C_1{V}_{\mathrm{start}}}{\frac{\mathrm{VM}}{R_1}-I_{Q1}}$

For ensureing that circuit can start, usual VM/R ₁>>I _q1,

$t_1=R_1{C}_1\frac{V_{\mathrm{start}}}{\mathrm{VM}}$

When vdd voltage rises to V _startduring voltage, Enable signal becomes height, and sample holding unit, EA amplifier, PWM unit and driver output unit are started working, and DRV exports and produces pulse signal, exports energy, and FB voltage starts to rise.Before FB rises above vdd voltage, the I of AB two parts circuitry consumes _q1+ I _q2+ I _q3+ I _q4electric current completely by VDD electric capacity C ₁there is provided, vdd voltage declines.As shown in dotted portion in Fig. 3, if VDD drops to V _uVLOvoltage, Enable signal, by high step-down, can close sample holding unit, EA amplifier, PWM unit and driver output unit, and stops exporting, and needs to wait VDD again to rise to V _startcould work.VDD is by V _startdrop to V _uVLOrequired time is designated as t ₂; Chip consumes total current I _qtot:

I _Qtot＝I _Q1+I _Q2+I _Q3+I _Q4

$t_2=\frac{C_1(V_{\mathrm{start}}-V_{\mathrm{UVLO}})}{L_{\mathrm{Qtot}}-I_{\mathrm{CHG}}}$

Generally, toggle speed is faster wished in good design, therefore needs to reduce t ₁.And chip needs at t ₂in time, FB voltage is charged to V _uVLOabove, guarantee normally works.From formula, increase C ₁t can be increased ₂, but t ₁also can increase, vice versa.

Therefore, in order to realize higher control precision, need the sampling hold circuit of high-speed, high precision and high-precision EA amplifier.Under equal technique, performance (speed and precision) is one of general knowledge of Integrated circuit designers with the compromise of power consumption.I _q2, I _q3very large, therefore t ₂time can significantly shorten.On the other hand in order to drive larger load, reduce output voltage ripple, output capacitance also can increase, and causes FB voltage rise slack-off, needs the time more grown FB voltage could be charged to V _uVLOmore than for VDD powers.Two factor actings in conjunction, may cause chip cannot at t ₂in time, FB voltage is lifted to V _uVLOabove, chip will restart, and repeat said process, enter the endless loop and cisco unity malfunction that do not stop to restart.

For ensureing that the normal need of work of chip increases t ₂, can only rely on and increase C ₁electric capacity.And increase C ₁electric capacity may make t ₁time increases to unacceptable length.Shorten t ₁time is by increasing I _cHGnamely resistance R is reduced ₁realize.And R ₁on quiescent dissipation be VM ²/ R1, less R ₁larger quiescent dissipation can be consumed, the decrease in efficiency of interchange-DC converter can be made again.

Utility model content

The purpose of this utility model is keeping, under less quiescent dissipation and the very fast prerequisite started, increasing the normal startup that up duration ensures AC/DC converter.

For achieving the above object, the utility model provides a kind of quick startup control circuit of converter, and it is characterized in that, described circuit comprises benchmaring unit, sample holding unit, amplifier, modulating unit, output unit and control unit;

The first input end input feedback voltage of described control unit, the second input is connected with the output of described benchmaring unit, and the first output is connected with described amplifier with described sample holding unit respectively; The input input supply voltage of described benchmaring unit; The input of described sample holding unit inputs described feedback voltage, and its output is connected with described amplifier; The output of described amplifier is connected with described modulating unit, and the output of described modulating unit is connected with described output unit;

When described supply voltage reaches the first voltage, described feedback voltage is less than reference voltage, first enable signal is the first level, second enable signal is second electrical level, the comparative result of described feedback voltage and described reference voltage processes by described control unit, and the result after process delivers to described modulating unit.

Further, described control unit comprises comparator and logical block;

The first input end of described comparator inputs described reference voltage, and its second input inputs described feedback voltage, and its output connects the input of described logical block; The output of described logical block is connected with described amplifier with described sample holding unit respectively;

Described feedback voltage and described reference voltage compare, and give described logical block by comparative result, and described logical block processes described comparative result;

Described comparative result is within the very first time, and when described feedback voltage is less than described reference voltage, described second enable signal is described second electrical level; When described feedback voltage is greater than described reference voltage, described second enable signal is described first level;

When described comparative result is not within the very first time, then described feedback voltage is less than described reference voltage, and described second enable signal is described second electrical level.

Advantage of the present utility model: do not changing non-essential resistance and electric capacity, under keeping the prerequisite of less quiescent dissipation and very fast toggle speed, increases up duration, ensures the normal startup of AC/DC converter.

Accompanying drawing explanation

Fig. 1 is that the one of the interchange-DC converter of prior art realizes framework;

Fig. 2 is the implementation of the interchange-DC controller of prior art;

Fig. 3 is the startup waveform schematic diagram of the interchange-DC controller of prior art;

The structural representation of the quick startup control circuit of the converter that Fig. 4 provides for the utility model embodiment;

The startup waveform schematic diagram of the quick startup control circuit of the converter that Fig. 5 provides for the utility model embodiment;

Another structural representation of the quick startup control circuit of the converter that Fig. 6 provides for the utility model embodiment;

Fig. 7 is the feedback voltage waveform schematic diagram of the quick startup control circuit of the converter that the utility model embodiment provides.

Embodiment

Below by drawings and Examples, the technical solution of the utility model is described in further detail.

The structural representation of the quick startup control circuit of the converter that Fig. 4 provides for the utility model embodiment.As shown in Figure 4, comprise benchmaring unit, sample holding unit, amplifier, modulating unit, output unit, supply voltage and feedback voltage, also comprise control unit.Wherein, benchmaring unit is reference circuit & VDD and detects, control circuit A is control unit, sampling maintenance is sample holding unit, EA amplifier is amplifier, pulse width modulation (Pulse Width Modulation, PWM) modulator is modulating unit, output voltage port (Driver Output, DRV), Driver is output unit, feedback voltage (Feedback Voltage, FB), Enable signal is the first enable signal, Enable ₂signal is the second enable signal, reference voltage (Reference Voltage, Vref).

Reference circuit & VDD is also called benchmaring unit, and the electric current of benchmaring unit consumption is I _q1, the electric current of sample holding unit consumption is I _q2even if EA amplifier is amplifier, its electric current consumed is I _q3, PWM device is modulating unit, and its electric current consumed is I _q4, control circuit A is control unit, and its electric current consumed is I _q5.

The first input end input feedback voltage of control unit, the second input is connected with the output of benchmaring unit, and the first output is connected with amplifier with sample holding unit respectively; The input input supply voltage of benchmaring unit; The input input feedback voltage of sample holding unit, its output is connected with amplifier; The output of amplifier is connected with modulating unit, and the output of modulating unit is connected with described output unit;

Control unit receives the first enable signal that benchmaring unit produces, and the second enable signal that described control unit produces by its first output exports.

The startup waveform schematic diagram of the quick startup control circuit of the converter that Fig. 5 provides for the utility model embodiment.As shown in Figure 5, V _startvoltage is the first voltage, V _uVLOvoltage is the second voltage, I _qTOTfor the total current that chip consumes, the first level is high level, and second electrical level is low level, Vref ₂voltage is reference voltage.

In busbar voltage (rectified mains voltage, VM) by resistance R ₁to C ₁after charging, and be V when VDD rises to voltage _startafter, Enable signal becomes high level, and FB voltage is initially 0, Enable ₂signal is low level.Benchmark & VDD detection module, control circuit A, PWM device, output driver are started working, but sampling hold circuit and EA amplifier keep off position, not current sinking, and the total current of now chip consumption is I _q1+ I _q4+ I _q5.I _q5much smaller than I _q2+ I _q3, thus reduce the current drain in start-up course, time expand t ₂.

When FB voltage rise is to Vref ₂time, output voltage has exceeded voltage V _uVLO, now Enable2 voltage becomes height, and the sampling of chip keeps and EA amplifier is started working, and consumption total current is I _q1+ I _q2+ I _q3+ I _q4+ I _q5.

Another structural representation of the quick startup control circuit of the converter that Fig. 6 provides for the utility model embodiment.As shown in Figure 6, control unit comprises comparator and logical block.Wherein, CMP is comparator, and Logic is logical block.

The first input end input reference voltage of comparator, its second input input feedback voltage, its output connects the input of logical block; The output of logical block is connected with amplifier with sample holding unit respectively;

Feedback voltage and reference voltage compare, and give logical block by comparative result, and logical block compared result processes;

In order to avoid noise false triggering second enable signal on feedback voltage signal, logical block comprises sequence circuit compared result and processes, and when only having feedback voltage signal to stablize, comparative result is just effective.

Fig. 7 is the feedback voltage waveform schematic diagram of the quick startup control circuit of the converter that the utility model embodiment provides.As shown in Figure 7, the result of comparator is just effective within the valid window time, and the valid window time is the very first time, and the valid window time refers to that feedback voltage becomes high level from low level, and is reduced to reference voltage Vref gradually ₂a period of time.

(1) if the pulse duration of feedback voltage FB is very narrow and when not meeting the valid window time, then think that feedback voltage is lower than reference voltage Vref ₂, the second enable signal Enable ₂for low level.

(2) if detect in the valid window time that feedback voltage FB is lower than reference voltage Vref ₂time, the second enable signal Enable ₂for low level.

(3) if detect in the valid window time that feedback voltage FB is higher than reference voltage Vref ₂time, the second enable signal Enable ₂to latch for high level.

Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; be understood that; the foregoing is only embodiment of the present utility model; and be not used in restriction protection range of the present utility model; all within spirit of the present utility model and principle, any amendment made, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.

Claims (2)

1. a quick startup control circuit for converter, it is characterized in that, described circuit comprises benchmaring unit, sample holding unit, amplifier, modulating unit, output unit and control unit;

The first input end input feedback voltage of described control unit, the second input is connected with the output of described benchmaring unit, and the first output is connected with described amplifier with described sample holding unit respectively; The input input supply voltage of described benchmaring unit; The input of described sample holding unit inputs described feedback voltage, and its output is connected with described amplifier; The output of described amplifier is connected with described modulating unit, and the output of described modulating unit is connected with described output unit;

When described supply voltage reaches the first voltage, described feedback voltage is less than reference voltage, first enable signal is the first level, second enable signal is second electrical level, the comparative result of described feedback voltage and described reference voltage processes by described control unit, and the result after process delivers to described modulating unit.

2. the quick startup control circuit of converter according to claim 1, it is characterized in that, described control unit comprises comparator and logical block;

The first input end of described comparator inputs described reference voltage, and its second input inputs described feedback voltage, and its output connects the input of described logical block; The output of described logical block is connected with described amplifier with described sample holding unit respectively;

Described feedback voltage and described reference voltage compare, and give described logical block by comparative result, and described logical block processes described comparative result;

Described comparative result is within the very first time, and when described feedback voltage is less than described reference voltage, described second enable signal is described second electrical level; When described feedback voltage is greater than described reference voltage, described second enable signal is described first level;

When described comparative result is not within the very first time, then described feedback voltage is less than described reference voltage, and described second enable signal is described second electrical level.