CN204044535U - Standard time treating apparatus - Google Patents

Standard time treating apparatus Download PDF

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Publication number
CN204044535U
CN204044535U CN201420107148.0U CN201420107148U CN204044535U CN 204044535 U CN204044535 U CN 204044535U CN 201420107148 U CN201420107148 U CN 201420107148U CN 204044535 U CN204044535 U CN 204044535U
Authority
CN
China
Prior art keywords
interface
unit
serial ports
standard time
big dipper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201420107148.0U
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Chinese (zh)
Inventor
崔保健
周德海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
METERING TESTING CENTER UNIT 92493 OF PLA
Original Assignee
METERING TESTING CENTER UNIT 92493 OF PLA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by METERING TESTING CENTER UNIT 92493 OF PLA filed Critical METERING TESTING CENTER UNIT 92493 OF PLA
Priority to CN201420107148.0U priority Critical patent/CN204044535U/en
Application granted granted Critical
Publication of CN204044535U publication Critical patent/CN204044535U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model provides standard time treating apparatus.Be respectively equipped with the first Big Dipper signaling interface in the circuit board, the second Big Dipper interface, a GPS synchronizing signal interface, the 2nd GPS synchronizing signal interface and 10MHz input interface, and VCXO unit is housed; Also microprocessor unit is housed in the circuit board, silicon delay line, TDC measuring unit, D/A conversion unit and CPLD unit; Be provided with the first output serial ports and second in wiring board side and export serial ports.Compared with the utility model and cesium-beam atomic clock time determines, there is structure simple, time signal source easily, the advantage of low cost of manufacture.The suitable application of installation determined as the standard time.

Description

Standard time treating apparatus
Technical field
The utility model provides the device for the time of settling the standard, specifically standard time treating apparatus.
Background technology
At present, the standard time is widely used in trajectory measurement, static fixing field, provides accurately real-time locating information.
The confirmed standard time uses cesium-beam atomic clock usually, but cesium-beam atomic clock manufacturing cost is high, and difficulty is large.
Summary of the invention
Determine to overcome the existing standard time defect that difficulty is large, the utility model provides standard time treating apparatus.This device processes by extracting time reference signal from GPS and big-dipper satellite, the technical matters that the solution standard time is determined.
The scheme that technical solution problem of the present invention adopts is:
Be respectively equipped with the first Big Dipper signaling interface in the circuit board, the second Big Dipper interface, a GPS synchronizing signal interface, the 2nd GPS synchronizing signal interface and 10MHz input interface, and VCXO unit is housed;
Also microprocessor unit is housed in the circuit board, silicon delay line, TDC measuring unit, D/A conversion unit and CPLD unit;
Be provided with the first output serial ports and second in wiring board side and export serial ports.
Good effect, compared with the utility model and cesium-beam atomic clock time determines, has structure simple, time signal source easily, the advantage of low cost of manufacture.The suitable application of installation determined as the standard time.
Accompanying drawing explanation
Fig. 1 is the utility model circuit board structure figure
In figure, the 1, first Big Dipper signaling interface, 2. the second Big Dipper interface, 3. a GPS synchronizing signal interface, 4. the 2nd GPS synchronizing signal interface, 5.10MHz input interface, 6. VCXO unit, 7. microprocessor unit, 8. silicon delay line, 9.TDC measuring unit, 10. D/A conversion unit, 11.CPLD unit, 12. first export serial ports, and 13. second export serial ports.
Embodiment
According to the figure, be respectively equipped with the first Big Dipper signaling interface 1, second Big Dipper interface the 2, one GPS synchronizing signal interface the 3, two GPS synchronizing signal interface 4,10MHz input interface 5 in the circuit board, and VCXO unit 6 is housed;
In the circuit board microprocessor unit 7 is also housed, silicon delay line 8, TDC measuring unit 9, D/A conversion unit 10 and CPLD unit 11;
Be provided with the first output serial ports 12 and second in wiring board side and export serial ports 13.
Described 10MHz input interface, be the interface to circuit board input 10MHz pulse signal, object is for wiring board provides the pulse power.
Utility model works principle:
By the time signal of the first Big Dipper signaling interface, the second Big Dipper interface, a GPS synchronizing signal interface, the 2nd GPS synchronizing signal interface and VCXO unit input, after microprocessor unit process, delay disposal is carried out by silicon delay line, the time signal detected is after TDC measuring unit is measured, be input to D/A conversion unit conversion, the time signal after conversion exports serial ports and second by CPLD unit from first and exports the outside outputting standard time signal of serial ports.
Concise and to the point low theory is: the time signal coming from the Big Dipper and gps signal and VCXO unit, after microprocessor coupling processing, detects time reference signal, changes through chip measurement, and the time reference signal detected is exported by serial ports.For the determination of standard time.

Claims (1)

1. standard time treating apparatus, is characterized in that:
Be respectively equipped with the first Big Dipper signaling interface (1) in the circuit board, the second Big Dipper interface (2), a GPS synchronizing signal interface (3), the 2nd GPS synchronizing signal interface (4), 10MHz input interface (5), and VCXO unit (6) is housed;
Microprocessor unit (7) is also housed in the circuit board, silicon delay line (8), TDC measuring unit (9), D/A conversion unit (10) and CPLD unit (11);
Be provided with the first output serial ports (12) and second in wiring board side and export serial ports (13).
CN201420107148.0U 2014-03-10 2014-03-10 Standard time treating apparatus Expired - Fee Related CN204044535U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420107148.0U CN204044535U (en) 2014-03-10 2014-03-10 Standard time treating apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420107148.0U CN204044535U (en) 2014-03-10 2014-03-10 Standard time treating apparatus

Publications (1)

Publication Number Publication Date
CN204044535U true CN204044535U (en) 2014-12-24

Family

ID=52245183

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420107148.0U Expired - Fee Related CN204044535U (en) 2014-03-10 2014-03-10 Standard time treating apparatus

Country Status (1)

Country Link
CN (1) CN204044535U (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20141224

Termination date: 20160310

CF01 Termination of patent right due to non-payment of annual fee