CN203909431U - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN203909431U CN203909431U CN201420160470.XU CN201420160470U CN203909431U CN 203909431 U CN203909431 U CN 203909431U CN 201420160470 U CN201420160470 U CN 201420160470U CN 203909431 U CN203909431 U CN 203909431U
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Abstract
The utility model provides a display panel. The display panel comprises a source driver and a plurality of data lines, wherein the data lines are arranged in different layers in the thickness direction of an array substrate of the display panel, the source driver is connected with the data lines, the source driver comprises a driving module which provides a driving signal and a pre-charging module which is electrically connected with the driving module, and the pre-charging module is used for pre-charging storage capacitors corresponding to pixel electrodes connected with the data lines to enable initial capacitance of the storage capacitors corresponding to the pixel electrodes connected with the data lines in the different layers to be the same when data is written in. Correspondingly, the utility model further provides a display device. Compared with the prior art, the display panel and the display device have the advantage that the phenomenon of poor vertical lines can be simply and effectively reduced without conducting wiring design corresponding to the data lines in the different layers.
Description
Technical field
The utility model relates to field of liquid crystal display, particularly, relates to a kind of display panel and a kind of display device.
Background technology
At present, in order to simplify the design of display panels, conventionally grid is driven and is arranged on display panel inside, adopt GOA(gate on array) design of+double grid, as shown in Figure 1, many data lines are connected with source electrode driver.In actual applications, panel end data line is divided into two-layer distribution conventionally, odd lines and even lines are separately positioned on different layers, because the actual duration of charging of two-layer data line there are differences, make between different layers the electric capacity when memory capacitance of cabling starts data writing have larger difference, visually produce vertical line bad (V-Line phenomenon) thereby cause.
In order to address this problem, the method for available technology adopting is for specific panel, and the cabling being connected with data line by adjusting source electrode driver inside, to reduce the difference of the memory capacitance of cabling between different layers.The cabling design of this method need to be carried out corresponding change according to different panels, comparatively complicated in the time of large-scale application, and, because the area of source electrode driver itself is limited, cause cabling capable of regulating space little, thus vertical line bad to improve effect limited.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of display panel and display device, to reduce simply and effectively the generation of vertical line bad phenomenon.
To achieve these goals, as one side of the present utility model, a kind of display panel is provided, comprise source electrode driver and many data lines, many described data line is arranged in the different layers of thickness direction of the array base palte of described display panel, described source electrode driver is connected with described data line, described source electrode driver comprises provides the driver module of driving signal and the pre-charge module being electrically connected with this driver module, this pre-charge module is used to the corresponding memory capacitance precharge of pixel electrode that is connected with the described data line of different layers, the described data line that makes different layers is that the initial capacitance of the corresponding memory capacitance of the pixel electrode connected with this data line in the time of data writing is identical.
Preferably, described pre-charge module comprises register group, every layer of described data line is corresponding connected with a register in described register group, to control the time of the described data line of the different layers memory capacitance precharge corresponding as the pixel electrode connected with this data line, the described data line that makes different layers is that the initial capacitance of the corresponding memory capacitance of the pixel electrode connected with this data line in the time of data writing is identical.
Preferably, every described data line is connected with two row pixel electrodes, every row pixel electrode is connected with two grid lines, odd pixel electrode in every row pixel electrode is connected with in two described grid lines one, and the even pixel electrode in every row pixel electrode is connected with another in two described grid lines.
Preferably, odd data line in many described data lines is arranged on one deck of the thickness direction of described array base palte, even data line in many described data lines is arranged on another layer of the thickness direction of described array base palte, described register group comprises odd-numbered register and even numbered register, described odd-numbered register is connected with described odd data line, and described even numbered register is connected with described even data line.
As on the other hand of the present utility model, a kind of display device is provided, comprise display panel, described display panel is display panel provided by the utility model.
In the utility model, the described data line that described pre-charge module can be controlled different layers is the time of the memory capacitance precharge corresponding with this data line, initial capacitance during taking the data line that makes different layers as the memory capacitance data writing corresponding with this data line is identical, compared with prior art, do not need to carry out, designing with the corresponding cabling of different layers data line, can reduce simply and effectively the generation of vertical line bad phenomenon.
Brief description of the drawings
Accompanying drawing is to be used to provide further understanding of the present utility model, and forms a part for instructions, is used from explanation the utility model, but does not form restriction of the present utility model with embodiment one below.In the accompanying drawings:
Shown in Fig. 1 is the structural representation of existing display panel;
Shown in Fig. 2 is the structural representation of display panel provided by the utility model;
Shown in Fig. 3 is the electric capacitance change schematic diagram of memory capacitance in the utility model.
Shown in Fig. 4 is the sequential chart in the first embodiment provided by the utility model;
Shown in Fig. 5 is the sequential chart in the second embodiment provided by the utility model;
Shown in Fig. 6 is the sequential chart in the third embodiment provided by the utility model;
Shown in Fig. 7 is the sequential chart in the 4th kind of embodiment provided by the utility model;
Description of reference numerals
1: source electrode driver; 2: odd-numbered register; 3: even numbered register; S1, S2, S3, S4, S5, S6: data line; G1, G2, G3, G4, G5, G6: grid line.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the utility model, is not limited to the utility model.
As one side of the present utility model, a kind of display panel is provided, comprise source electrode driver and many data lines, many described data line is arranged in the different layers of thickness direction of the array base palte of described display panel, described source electrode driver is connected with described data line, wherein, described source electrode driver comprises provides the driver module of driving signal and the pre-charge module being electrically connected with this driver module, this pre-charge module is used to the corresponding memory capacitance precharge of pixel electrode that is connected with the described data line of different layers, the described data line that makes different layers is that the initial capacitance of the corresponding memory capacitance of the pixel electrode connected with this data line in the time of data writing is identical.
Under normal circumstances, pixel electrode and public electrode form memory capacitance, by described memory capacitance is charged, that is, and for described memory capacitance data writing, to realize demonstration.
In the utility model, described pre-charge module can be the time of the corresponding memory capacitance precharge of the pixel electrode connected with the described data line of different layers.; it is that the memory capacitance that this data line is corresponding is charged that the described data line of different layers can shift to an earlier date the different time; for example; in different layers; the data line that resistance is relatively little can shift to an earlier date the relatively short time and charge; the relatively large data line of resistance can shift to an earlier date the relatively long time and charge, thereby initial capacitance when to make the data line of different layers be the memory capacitance data writing corresponding with this data line is identical, thereby reduces the generation of vertical line bad phenomenon.
Described precharge is before to described memory capacitance data writing, and described memory capacitance is charged, and makes the electric capacity of described memory capacitance reach the required predetermined capacitance value of data writing.As shown in Figure 3, while being corresponding memory capacitance precharge by the relatively large data line of resistance, make memory capacitance corresponding to the relatively large data line of this resistance reach described predetermined capacitance value C
1required time t
2longer; While being corresponding memory capacitance precharge by the relatively little data line of resistance, make memory capacitance corresponding to data line that this resistance is relatively little reach described predetermined capacitance value C
1required time t
1shorter, write thereby can make the corresponding memory capacitance of data line of different resistance carry out data in identical electric capacity.
As a kind of embodiment of the present utility model, described pre-charge module can comprise register group, every layer of described data line is corresponding connected with a register in described register group, to control the time of the described data line of the different layers memory capacitance precharge corresponding as the pixel electrode connected with this data line, the described data line that makes different layers is that the initial capacitance of the corresponding memory capacitance of the pixel electrode connected with this data line in the time of data writing is identical.
Further, as shown in Figure 2, every described data line can be connected with two row pixel electrodes, every row pixel electrode is connected with two grid lines, odd pixel electrode in every row pixel electrode is connected with in two described grid lines one, and the even pixel electrode in every row pixel electrode is connected with another in two described grid lines.
Particularly, data line S1 is connected with secondary series pixel electrode with first row pixel electrode, and data line S2 is connected with the 4th row pixel electrode with the 3rd row pixel electrode, and data line S3 is connected with the 6th row pixel electrode with the 5th row pixel electrode, by that analogy; Grid line G1 and the first row first row pixel electrode, the first row the 3rd row pixel electrode, the first row the 5th row pixel electrode ... be connected, grid line G2 and the first row secondary series pixel electrode, the first row the 4th row pixel electrode, the first row the 6th row pixel electrode ... be connected, grid line G3 and the second row first row pixel electrode, the second row the 3rd row pixel electrode, the second row the 5th row pixel electrode ... be connected, by that analogy.Described " first row, secondary series, the 3rd row ... " sort successively with direction from left to right in Fig. 2, and described " the first row, the second row, the third line ... " sorts successively with top-down direction in Fig. 2.In the time that the gate drivers control grid line G1 being connected with grid line opens, the transistorized grid of the pixel cell being connected with grid line G1 is opened, source electrode driver is the memory capacitance data writing corresponding to pixel electrode of the first row first row by data line S1, be the memory capacitance data writing that the tertial pixel electrode of the first row is corresponding by data line S2, be the memory capacitance data writing corresponding to pixel electrode of the first row the 5th row by data line S3, by that analogy.When gate drivers control grid line G2 opens, the transistorized grid of the pixel cell being connected with grid line G2 is opened, source electrode driver is the memory capacitance data writing corresponding to pixel electrode of the first row secondary series by data line S1, be the memory capacitance data writing corresponding to pixel electrode of the first row the 4th row by data line S2, it is the memory capacitance data writing of the pixel electrode of the first row the 6th row by data line S3, by that analogy, grid line G3, G4 etc. open the transistorized grid of coupled each pixel cell successively.
Further, many described data line can be divided into two-layer setting at the thickness direction of described array base palte, wherein, odd data line (, Article 1 data line S1 shown in Fig. 2, Article 3 data line S3, Article 5 data line S5 etc.) be arranged on one deck of the thickness direction of described array base palte, even data line in many described data lines (, Article 2 data line S2 shown in Fig. 2, Article 4 data line S4, Article 6 data line S6 etc.) be arranged on described array base palte thickness direction another layer, described register group can comprise odd-numbered register 2 and even numbered register 3, odd-numbered register 2 is connected with described odd data line, even numbered register 3 is connected with described even data line.Odd-numbered register 2 can be controlled the time that described odd data line is the precharge of the corresponding memory capacitance of pixel electrode that is connected with this odd data line, and even numbered register 3 can be controlled the precharge time that described even data line is the corresponding memory capacitance of the pixel electrode that is connected with this even data line.For example, in the time that the resistance of described odd data line is less than the resistance of described even data line, by the control action of odd-numbered register 2 and even numbered register 3, making described odd data line is to be less than time of corresponding memory capacitance precharge the time that described odd data line is corresponding memory capacitance precharge, thereby make into the memory capacitance corresponding with odd data line with for the initial capacitance when the data writing is identical with memory capacitance corresponding to even data line, make like this into time of the memory capacitance data writing corresponding with described odd data line with for identical with the time of memory capacitance data writing corresponding to described even data line.
In order to realize above-mentioned control, odd-numbered register 2 can be by exporting in the different moment time of the different level signal control memory capacitance precharge corresponding with described odd data line, and described even numbered register 3 can be by exporting the precharge time of the different level signal control memory capacitance corresponding with described even data line in the different moment.Particularly, in the time of described driver module output high level, odd-numbered register 2 and the equal output low level of even numbered register 3, pre-charge process does not all start; In the time of described driver module output low level, odd-numbered register 2 for example, from the first moment (, t in Fig. 4
1moment) start to export high level, described odd data line starts to carry out precharge for the corresponding memory capacitance of the pixel electrode connected with this odd data line, and even numbered register 3 for example, from the second moment (, t in Fig. 4
3moment) start to export high level, described even data line starts to carry out precharge for the corresponding memory capacitance of the pixel electrode connected with this even data line.
It should be noted that, described the first moment does not represent the some time points on time shaft, but represents the state of odd-numbered register 2 while starting to export high level, same, state when described the second moment represents that even numbered register 3 starts to export high level.
As the first embodiment of the present utility model, in the time that the resistance of described odd data line is greater than the resistance of described even lines, as shown in Figure 4, described driver module can for example, from the 3rd moment (, the t shown in Fig. 4
1moment) start output low level, odd-numbered register 2 can for example, from (, the t shown in Fig. 4 of described the first moment
1moment) start to export high level, even numbered register 3 for example, from the second moment (t in, shown in Fig. 4
3moment) start to export high level., odd-numbered register 2 is exported high level when described driver module output low level; Described the second moment lags behind described the first moment.Making described odd data line is to be greater than time of corresponding memory capacitance precharge the time that described even data line is corresponding memory capacitance precharge, thereby makes into the time of the memory capacitance data writing corresponding with described odd data line with for identical with the time of memory capacitance data writing corresponding to described even data line.
As the second embodiment of the present utility model, in the time that the resistance of described odd data line is less than the resistance of described even data line, as shown in Figure 5, described driver module can for example, from the 3rd moment (, the t shown in Fig. 5
1moment) start output low level, odd-numbered register 2 can for example, from the first moment (, t shown in Fig. 5
2moment) start to export high level, even numbered register 3 for example, from the second moment (, t shown in Fig. 5
1moment) start to export high level.That is, described the 3rd moment and described the second moment maintain an equal level, and described the first moment lags behind described the second moment.Making described odd data line is to be less than time of corresponding memory capacitance precharge the time that described even data line is corresponding memory capacitance precharge, thereby makes into the time of the memory capacitance data writing corresponding with described odd data line with for identical with the time of memory capacitance data writing corresponding to described even data line.
Hold intelligiblely, in the time that the resistance of described odd data line equals the resistance of described even lines, described the first moment was maintained an equal level in described the second moment, that is, odd-numbered register 2 and described even numbered register 3 can start to export high level from synchronization.
The control to described precharge time for the ease of odd-numbered register 2 and even numbered register 3, described the first moment and described the second moment can all lag behind described the 3rd moment (as shown in Figure 6 and Figure 7).
As the third embodiment of the present utility model, in the time that the resistance of described odd data line is greater than the resistance of described even lines, as shown in Figure 6, described driver module for example, from the 3rd moment (, the t shown in Fig. 6
1moment) beginning output low level; Odd-numbered register 2 for example, from lagging behind the first moment (, t shown in Fig. 6 in the 3rd moment
2moment) start to export high level; Even numbered register 3 for example, from lagging behind the second moment (, t shown in Fig. 6 in the first moment
4moment) start to export high level.Making described odd data line is to be greater than time of the memory capacitance precharge corresponding with this odd data line the time that described even data line is the memory capacitance precharge corresponding with this even data line, thereby makes into the time of the memory capacitance data writing corresponding with described odd data line with for identical with the time of memory capacitance data writing corresponding to described even data line.
As the 4th kind of embodiment of the present utility model, in the time that the resistance of described odd data line is less than the resistance of described even lines, as shown in Figure 7, described driver module for example, from the 3rd moment (, the t shown in Fig. 7
1moment) beginning output low level; Even numbered register 3 for example, from lagging behind the second moment (, t shown in Fig. 7 in the 3rd moment
2moment) start to export high level; Odd-numbered register 2 for example, from lagging behind the first moment (, t shown in Fig. 7 in the second moment
3moment) start to export high level.Making described odd data line is time of the memory capacitance precharge corresponding with this odd data line to be less than the time of the memory capacitance precharge that described even data line is corresponding, thereby makes into the time of the memory capacitance data writing corresponding with described odd data line with for identical with the time of memory capacitance data writing corresponding to described even data line.
In actual applications, can be according to the resistance value of odd data line on concrete display panel and even data line, adjust the duration between described the first moment, the second moment and the 3rd moment.The utility model is not done concrete restriction to the value of described duration, as long as carry out after above-mentioned precharge processing according to described the first moment, the second moment and the 3rd moment, for the time of the memory capacitance data writing corresponding with described odd data line equals time of the memory capacitance data writing corresponding for described even data line.
As a kind of embodiment of the present utility model, duration between described the second moment and described the first moment is any one in 0s, 25s, 50s and 75s, and the duration that the one of the time lead in described the first moment and described the second moment lags behind described the 3rd moment is any one in 0s, 25s, 50s and 75s., the t in Fig. 4 to Fig. 7
1moment, t
2moment, t
3moment and t
4duration between moment is 25s.Hold intelligiblely, four moment (t are set
1moment, t
2moment, t
3moment and t
4moment) time, can there is embodiments different in 16, that is: described driver module is from t
1moment starts output low level, and odd-numbered register 2 is from t
2moment, t
2moment, t
3moment or t
4moment starts to export high level, and even numbered register 3 is from t
2moment, t
2moment, t
3moment or t
4moment starts to export high level.Similarly, when five moment (t are set
1moment, t
2moment, t
3moment, t
4moment and t
5moment) time, have 25 kinds of embodiments, by that analogy.The utility model only to wherein four kinds describe.Taking Fig. 4 as example, as the t in figure
1moment, t
2moment, t
3moment and t
4duration between moment, while being 25s, when this embodiment represents described driver module output low level, odd-numbered register 2 was exported high level, 50s afterwards, and even numbered register 3 starts to export high level.,, after memory capacitance precharge 50s corresponding to described odd data line, start the memory capacitance charging corresponding for described even data line.
In the utility model, odd-numbered register 2 is connected with described odd data line, to control the time of described odd data line as the memory capacitance precharge corresponding with this odd data line; Even numbered register 3 is connected with described even data line, and to control the time of described even data line as the memory capacitance precharge corresponding with this even data line, making odd data line and even data line is that time of corresponding memory capacitance data writing is identical.Compared with prior art, the utility model is the control to described precharge time by described register group, goes for different display panels, is convenient to large-scale production, and there is larger adjustment space precharge time, thereby can reduce simply and effectively the generation of vertical line bad phenomenon.
As on the other hand of the present utility model, a kind of display device is provided, this display device comprises display panel, wherein, described display panel is display panel provided by the utility model.
Be understandable that, above embodiment is only used to principle of the present utility model is described and the illustrative embodiments that adopts, but the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (5)
1. a display panel, comprise source electrode driver and many data lines, many described data line is arranged in the different layers of thickness direction of the array base palte of described display panel, described source electrode driver is connected with described data line, it is characterized in that, described source electrode driver comprises provides the driver module of driving signal and the pre-charge module being electrically connected with this driver module, this pre-charge module is used to the corresponding memory capacitance precharge of pixel electrode that is connected with the described data line of different layers, the described data line that makes different layers is that the initial capacitance of the corresponding memory capacitance of the pixel electrode connected with this data line in the time of data writing is identical.
2. display panel according to claim 1, it is characterized in that, described pre-charge module comprises register group, every layer of described data line is corresponding connected with a register in described register group, to control the time of the described data line of the different layers memory capacitance precharge corresponding as the pixel electrode connected with this data line, the described data line that makes different layers is that the initial capacitance of the corresponding memory capacitance of the pixel electrode connected with this data line in the time of data writing is identical.
3. display panel according to claim 1, it is characterized in that, every described data line is connected with two row pixel electrodes, every row pixel electrode is connected with two grid lines, odd pixel electrode in every row pixel electrode is connected with in two described grid lines one, and the even pixel electrode in every row pixel electrode is connected with another in two described grid lines.
4. according to the display panel described in any one in claims 1 to 3, it is characterized in that, odd data line in many described data lines is arranged on one deck of the thickness direction of described array base palte, even data line in many described data lines is arranged on another layer of the thickness direction of described array base palte, described register group comprises odd-numbered register and even numbered register, described odd-numbered register is connected with described odd data line, and described even numbered register is connected with described even data line.
5. a display device, comprises display panel, it is characterized in that, described display panel is the display panel described in any one in claim 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420160470.XU CN203909431U (en) | 2014-04-03 | 2014-04-03 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420160470.XU CN203909431U (en) | 2014-04-03 | 2014-04-03 | Display panel and display device |
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| CN203909431U true CN203909431U (en) | 2014-10-29 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154242A (en) * | 2017-06-19 | 2017-09-12 | 惠科股份有限公司 | The driving method and display panel of display panel |
| CN109377927A (en) * | 2018-11-05 | 2019-02-22 | Oppo（重庆）智能科技有限公司 | Driving method, driving circuit, display panel and storage medium |
| CN109509455A (en) * | 2018-12-25 | 2019-03-22 | 惠科股份有限公司 | Driving method, display device and the storage medium of display panel |
| CN109817146A (en) * | 2019-03-08 | 2019-05-28 | 京东方科技集团股份有限公司 | A kind of display panel, display device and driving method |
| WO2023065338A1 (en) * | 2021-10-22 | 2023-04-27 | 京东方科技集团股份有限公司 | Source driver circuit, source driving method, display device, and display driving method |
-
2014
- 2014-04-03 CN CN201420160470.XU patent/CN203909431U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154242A (en) * | 2017-06-19 | 2017-09-12 | 惠科股份有限公司 | The driving method and display panel of display panel |
| WO2018233040A1 (en) * | 2017-06-19 | 2018-12-27 | 惠科股份有限公司 | Display panel drive method and display panel |
| US11348546B2 (en) | 2017-06-19 | 2022-05-31 | HKC Corporation Limited | Display panel and driving method thereof |
| CN109377927A (en) * | 2018-11-05 | 2019-02-22 | Oppo（重庆）智能科技有限公司 | Driving method, driving circuit, display panel and storage medium |
| CN109377927B (en) * | 2018-11-05 | 2022-03-01 | Oppo（重庆）智能科技有限公司 | Driving method, driving circuit, display panel and storage medium |
| CN109509455A (en) * | 2018-12-25 | 2019-03-22 | 惠科股份有限公司 | Driving method, display device and the storage medium of display panel |
| CN109817146A (en) * | 2019-03-08 | 2019-05-28 | 京东方科技集团股份有限公司 | A kind of display panel, display device and driving method |
| CN109817146B (en) * | 2019-03-08 | 2023-02-28 | 京东方科技集团股份有限公司 | Display panel, display device and driving method |
| WO2023065338A1 (en) * | 2021-10-22 | 2023-04-27 | 京东方科技集团股份有限公司 | Source driver circuit, source driving method, display device, and display driving method |
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