CN203872050U - Current mode switch power supply control circuit - Google Patents
Current mode switch power supply control circuit Download PDFInfo
- Publication number
- CN203872050U CN203872050U CN201420315122.5U CN201420315122U CN203872050U CN 203872050 U CN203872050 U CN 203872050U CN 201420315122 U CN201420315122 U CN 201420315122U CN 203872050 U CN203872050 U CN 203872050U
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- buffer
- reference voltage
- comparator
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- switch power
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Abstract
A current mode switch power supply control circuit comprises a first comparator, a delay circuit and a driving logic circuit; two input ends of the first comparator are respectively connected with a first reference voltage and a current detection end; the driving logic circuit comprises an AND gate and a driving stage; two input ends of the AND gate of the driving logic circuit are respectively connected with an output end of the first comparator and an output end of a third buffer; the current mode switch power supply control circuit also comprises a instantaneous turn off circuit formed by a second comparator, a second reference voltage and a second NMOS pipe. The current mode switch power supply control circuit has a blanking function, and over current signals in a set scope can be shielded to automatically ensure the switch power supply to constantly work; when instantaneous heavy current comes, a power tube can be fast closed, so the switch power supply can more effectively and safely work.
Description
Technical field
The utility model relates to electronic circuit field, particularly, relates to a kind of current mode switch power control circuit.
Background technology
Along with the development of power technology, in electric power system, communication system, use more and more widely the power-supply devices such as Switching Power Supply, UPS.These equipment will detect voltage, the current signal of main circuit bar none.Current detection circuit is the requisite important component part of power-supply device normally.
Current source PWM (PWM) controller is in common voltage feedback PWM control ring inside, to have increased the controlling unit of current feedback, thereby except the function that comprises voltage type PWM controller, can also sense switch electric current or inductive current, realize the dicyclo of electric current and voltage and control.
Current regulator is by detecting the switch of power tube in current-controlled switch power supply, for eliminating the impact of high frequency clutter, particularly due at switch conduction or turn-off transient, the high-voltage oscillation that stray inductance produces, conventionally need to before and after switching over, arrange between blanking zone, i.e., in the time period between blanking zone, current limit is inoperative, the risk that in having brought when having improved control stability, significantly having reduced output voltage ripple between blanking zone, transient high-current burns power tube.
Utility model content
For overcoming existing current control circuit when arranging between blanking zone, bring transient high-current to burn the technological deficiency of power tube risk, the utility model discloses a kind of current mode switch power control circuit.
Current mode switch power control circuit, comprises the first comparator, and two inputs of described the first comparator connect respectively the first reference voltage and current detecting end;
Also comprise delay circuit and drive logical circuit, described driving logical circuit is by forming with door and driving stage, output described and door is connected the first buffer input of driving stage, and the output of described the first buffer connects into the PMOS of inverter form connection and the grid of a NMOS pipe; Described delay circuit comprises the second buffer and the 3rd buffer of series connection, the input of described the second buffer connects the output of the first comparator, the output of the second buffer connects delay capacitor, described driving logical circuit be connected respectively the output of the first comparator and the output of the 3rd buffer with two inputs of door;
Also comprise instantaneous breaking circuit, described instantaneous breaking circuit is by the second comparator, the second reference voltage and the 2nd NMOS pipe form, two inputs of described the second comparator connect respectively the second reference voltage and current detecting end, output connects the grid of the 2nd NMOS pipe, and the drain electrode of described the 2nd NMOS pipe is connected respectively the drain electrode of PMOS pipe and ground with source electrode;
Described the second reference voltage value is greater than the first reference voltage, and each buffer is not for changing the signal amplifier of incoming level logic state.
Concrete, described each buffer is that even number of inverters series connection forms.
Preferably, described the second buffer is operational amplifier.
Preferably, described reference voltage is produced by the first divider resistance, the second divider resistance and the 3rd divider resistance being connected in turn between internal electric source and ground wire by internal electric source, described the first reference voltage is taken out by the tie point of the second divider resistance and the 3rd divider resistance, described the second reference voltage is taken out by the tie point of the first divider resistance and the second divider resistance, and described internal electric source is the power supply of PMOS pipe simultaneously.
Current mode switch power control circuit described in the utility model, has blanking function, and the over-current signal by shielding in setting range, ensures that Switching Power Supply works on automatically; And when transient high-current interim, can quick closedown power tube, thus can make the more efficient and operation safely of Switching Power Supply.By the extremely low common separation device of use cost, significantly reduced manufacturing cost.
Accompanying drawing explanation
Fig. 1 is a kind of embodiment schematic diagram of the utility model;
Mark and corresponding parts title in accompanying drawing: IS-current detecting end, R1-the first divider resistance, R2-the second divider resistance, R3-the 3rd divider resistance, COMP1-the first comparator, COMP2 – the second comparator, B1-the first buffer, B2-the second buffer, B3-the 3rd buffer, C-delay capacitor, VCC-internal electric source, NAND-and logical circuit, P – PMOS pipe, N1-the one NMOS pipe, N2-the 2nd NMOS pipe, M-power tube, SW-output.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the utility model is done to detailed description further, but execution mode of the present utility model is not limited to this.
Current mode switch power control circuit described in the utility model, comprises the first comparator, and two inputs of described the first comparator connect respectively the first reference voltage and current detecting end; Also comprise delay circuit and drive logical circuit, described driving logical circuit is by forming with door and driving stage, output described and door is connected the first buffer input of driving stage, and the output of described the first buffer connects into the PMOS of inverter form connection and the grid of a NMOS pipe; Described delay circuit comprises the second buffer and the 3rd buffer of series connection, the input of described the second buffer connects the output of the first comparator, the output of the second buffer connects delay capacitor, described driving logical circuit be connected respectively the output of the first comparator and the output of the 3rd buffer with two inputs of door;
Also comprise instantaneous breaking circuit, described instantaneous breaking circuit is by the second comparator, the second reference voltage and the 2nd NMOS pipe form, two inputs of described the second comparator connect respectively the second reference voltage and current detecting end, output connects the grid of the 2nd NMOS pipe, and the drain electrode of described the 2nd NMOS pipe is connected respectively the drain electrode of PMOS pipe and ground with source electrode;
Described the second reference voltage value is greater than the first reference voltage, and each buffer is not for changing the signal amplifier of incoming level logic state.
During use, as shown in Figure 1, M pipe is the power tube in switch power supply topological structure, and SW end connects inductance or rectifier diode conventionally.Current detection signal is from the input of IS end, current detection signal should be the signal of analog voltage form, can be by being converted into analog voltage input after current sampling, with reference voltage comparison, when higher than reference voltage value, the reversion of comparator C OMP output signal, drive the logic setting of logical circuit will make power tube close, but the existence due to delay circuit, make to drive reversing with door and the direct-connected input end signal of comparator output terminal in logical circuit, but another input is reversion immediately not, but pass through the second buffer B2 to delay capacitor C charge or discharge, until reverse after the logic level threshold voltage of change in voltage arrival the 3rd buffer B3 on delay capacitor, for example, to general MOS device, threshold voltage is about 0.7 volt, the voltage on delay capacitor charges to higher than 0.7 volt or while being discharged to lower than 0.7 volt, the output signal reversion of the 3rd buffer.After gate signal reversion, by PMOS pipe and the NMOS pipe enhancing driving force of inverter type of attachment, base stage or the grid of driving power pipe M.
Between time delay, be black-out intervals, at black-out intervals, when transient high-current comes temporarily, the second comparator C OMP2 output voltage reversion, opens the 2nd NMOS pipe, drags down fast VA point voltage, and power tube is closed.Because this transient current is generally improper electric current, and do not answer the normal work, particularly aforesaid clutter waveform of disturbance current control loop should not cause instantaneous breaking circuit action, therefore the second reference voltage value should be higher than the first reference voltage.
Because each buffer does not all change the logic state of incoming level at output, and be only input signal to be carried out to maintenance or the amplification of driving force, therefore after the time delay of delay capacitor C, finally with door place, the logical signal of two inputs reaches unanimity, thereby makes and the reversion of door output level described herein and door, be the circuit structure of realization and logical operation, be not limited to only with realizing with door in gate.
Buffer is divided into two kinds of modes of Digital and analog, can be that even number of inverters series connection forms, but to the second buffer B2, being preferably operational amplifier forms, can accurately set the electric current to delay capacitor C charge or discharge, thereby coordinate with setting capacitance, realize more accurately controlling delay time.
For reference voltage, in integrated circuit structure, can utilize ripe circuit structure, for example band-gap reference produces, but in the utility model, for all adopting the object of discrete device, can adopt resistance series connection dividing potential drop to obtain from internal electric source VCC, the first reference voltage as shown in Figure 1, the second reference voltage passes through the first divider resistance R1 by internal electric source VCC, the second divider resistance R2 and the 3rd branch pressure voltage R3 produce, described internal electric source VCC is the power supply of PMOS pipe simultaneously, by the resistance tie point power taking from different, press, naturally realize the second reference voltage higher than the first reference voltage, the second reference voltage and the first reference voltage synchronously change simultaneously, above-mentioned design simplification system power supply, reduced cost, simultaneously because reference voltage is followed internal power source voltage variation, when internal power source voltage becomes large, reference voltage value raises, current-limiting points increases, this meets the current limliting rule of Switching Power Supply, for high input supply voltage, be generally used for driving heavier load, current-limiting points rises thereupon, realized to a certain extent the auto-compensation to current-limiting points.The equal proportion of the second reference voltage and the first reference voltage changes, and also meets the common Changing Pattern of two different current-limiting points voltages.
As mentioned above, can realize preferably the utility model.
Claims (4)
1. current mode switch power control circuit, comprises the first comparator, and two inputs of described the first comparator connect respectively the first reference voltage and current detecting end, it is characterized in that,
Also comprise delay circuit and drive logical circuit, described driving logical circuit is by forming with door and driving stage, output described and door is connected the first buffer input of driving stage, and the output of described the first buffer connects into the PMOS of inverter form connection and the grid of a NMOS pipe; Described delay circuit comprises the second buffer and the 3rd buffer of series connection, the input of described the second buffer connects the output of the first comparator, the output of the second buffer connects delay capacitor, described driving logical circuit be connected respectively the output of the first comparator and the output of the 3rd buffer with two inputs of door;
Also comprise instantaneous breaking circuit, described instantaneous breaking circuit is by the second comparator, the second reference voltage and the 2nd NMOS pipe form, two inputs of described the second comparator connect respectively the second reference voltage and current detecting end, output connects the grid of the 2nd NMOS pipe, and the drain electrode of described the 2nd NMOS pipe is connected respectively the drain electrode of PMOS pipe and ground with source electrode;
Described the second reference voltage value is greater than the first reference voltage, and each buffer is not for changing the signal amplifier of incoming level logic state.
2. current mode switch power control circuit according to claim 1, is characterized in that, described each buffer is that even number of inverters series connection forms.
3. current mode switch power control circuit according to claim 1, is characterized in that, described the second buffer is operational amplifier.
4. current mode switch power control circuit according to claim 1, it is characterized in that, described reference voltage is produced by the first divider resistance, the second divider resistance and the 3rd divider resistance being connected in turn between internal electric source and ground wire by internal electric source, described the first reference voltage is taken out by the tie point of the second divider resistance and the 3rd divider resistance, described the second reference voltage is taken out by the tie point of the first divider resistance and the second divider resistance, and described internal electric source is the power supply of PMOS pipe simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420315122.5U CN203872050U (en) | 2014-06-14 | 2014-06-14 | Current mode switch power supply control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420315122.5U CN203872050U (en) | 2014-06-14 | 2014-06-14 | Current mode switch power supply control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203872050U true CN203872050U (en) | 2014-10-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420315122.5U Expired - Fee Related CN203872050U (en) | 2014-06-14 | 2014-06-14 | Current mode switch power supply control circuit |
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| Country | Link |
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| CN (1) | CN203872050U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105511365A (en) * | 2016-01-27 | 2016-04-20 | 张恒雄 | Controller for automatic control |
-
2014
- 2014-06-14 CN CN201420315122.5U patent/CN203872050U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105511365A (en) * | 2016-01-27 | 2016-04-20 | 张恒雄 | Controller for automatic control |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141008 Termination date: 20180614 |