CN203871322U - Silicon through hole device applied to high speed broadband optical interconnection - Google Patents
Silicon through hole device applied to high speed broadband optical interconnection Download PDFInfo
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- CN203871322U CN203871322U CN201420038087.7U CN201420038087U CN203871322U CN 203871322 U CN203871322 U CN 203871322U CN 201420038087 U CN201420038087 U CN 201420038087U CN 203871322 U CN203871322 U CN 203871322U
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- silicon
- tsv
- interconnection
- deep hole
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 58
- 239000010703 silicon Substances 0.000 title claims abstract description 58
- 230000003287 optical effect Effects 0.000 title abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 47
- 239000004065 semiconductor Substances 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 21
- 239000012212 insulator Substances 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 abstract description 10
- 230000008878 coupling Effects 0.000 abstract description 4
- 238000010168 coupling process Methods 0.000 abstract description 4
- 238000005859 coupling reaction Methods 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 239000012774 insulation material Substances 0.000 abstract 4
- 238000009413 insulation Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000005530 etching Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 241000218202 Coptis Species 0.000 description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000005622 photoelectricity Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007363 ring formation reaction Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model discloses a silicon through hole device applied to high speed broadband optical interconnection. A wide ring is firstly etched on the device for filling an insulation material, silicon enclosed by the insulation ring is secondly etched to form a TSV deep hole, and finally the TSV deep hole is filled with metal and electrodes of a positive photonic element, so as to form interconnection. The wide ring improves the thickness of the insulation layer and facilitates insulation material filling operation, so that TSV parasitic capacitance is greatly reduced, and transmission of a high speed broadband signal is facilitated. The TSV is formed after filling the insulation material, so that a problem that in the conventional technology, the insulation material at the bottom part of the TSV is partially etched when the TSV is metalized is prevented, and caused technology problems are prevented. Then, the back surface of the device is more conveniently attached to the electrodes of the Wafer positive photonic element. The device is integrated with a CMOS element in the back surface and with a silicon photonic element in the positive surface, so that single-chip integration design of the photonic element achieves more freedom, and various light source coupling modes in the future are ensured.
Description
Technical field
The utility model relates to microelectronics technology, relates in particular to a kind of manufacture method and device thereof that is applied to the silicon via devices of high-speed wideband light interconnection.
Background technology
In optical-electric module, mainly comprise two parts: opticator chip and coupling and control circuit.Wherein, photon chip mainly includes source and passive two kinds.Active electrooptic modulator (modulator), the photodetector (photodetector) of mainly comprising, passive device is mainly some multiplex/demultiplex (mux, demux) and optical waveguide etc.Electrical chip is mainly concerned with the driving (Driver) of electrooptic modulator, the amplifier (amplifiers of trans-impedance amplifier TIA or limiting amplifier LA or other types) of photodetector, also have some other coupling and control circuit, such as clock recovery (CDR), go here and there and change (Serdes), switching circuit (Switches) etc.
First, in the field of silica-based light delivery module, newer technology is that silicon based photon device and electricity chip are both directly printed on silicon wafer by traditional cmos process at present, for example the CPAK100G optical module of Cisco, also has IBM to adopt 90nm COMS technique that electricity and opticator (the silicon based photon device except laser) are realized on sheet integrated.For the ripe COMS technique of this employing, complete the new technology of opticator, a lot of companies and research team think that in design and volume production, having variety of issue occurs, for example Intel just thinks, according to the development of Moore's Law, the process node of COMS will certainly be more and more less, and the declaration meeting of 14nm Broadwell of Intel oneself started to go into operation the first quarter in 2014.And for photonic device, its technique magnitude also rests on tens microns or hundreds of nanometer, the technique of this node is enough to guarantee that the performance of existing optics realizes.The two has determined optics and electricity partly to utilize COMS technique of the same race to complete in the unmatched development trend of process node, obviously improper, considers selection that neither be best from cost control.
Secondly, mostly this more common class optical-electric module is to be integrated on pcb board, by discrete optical chip and with it the electrical chip of correspondence by the mode of wire bonding and Flip-Chip, assemble respectively.Although wherein wire bonding mode is easy to assembly, but because the problems such as loss, in high-frequency high-speed system, obvious these defects of RC delay and inductive effect make its application limited, the length that need to shorten as far as possible wire bonding gold thread reduces loss, in the following hundred lucky Ethernets system that even Tbit transmits, be almost difficult to application.The mode of Flip-Chip is because adopt the mode of direct interconnection, can avoid significantly the loss of gold thread, but along with constantly dwindling of COMS chip technology node, and the circuit line width and the spacing difficulty that continue reduction PCB version are larger, the state of the art still rests on micron dimension, if the electrical chip that is packaging body is assembled on PCB substrate, obviously can increase cost and power consumption, be also unfavorable for that compact, miniaturization are integrated.
Coplanar assembling form for photonic device and the discrete paster of electronic device, a distribution that problem is exactly paster space must considering, requirement not only will be considered at the beginning of design at photon integrated chip outside the coupled mode and reserved corresponding space of light source, also need for the reserved suitable space of electricity chip, increase designer's design cost, be also unfavorable for the optimized design that photon is integrated.Another major issue is the how manufacturing process of compatible optical device and the coupling of conventional MOS device and metal line technique, do not affect silicon based photon device in advance under, realize the high-speed and high-density interconnection of photonic device and electronic chip.
Utility model content
The object of this part is to summarize some aspects of embodiment of the present utility model and briefly introduces some preferred embodiments.In this part and the application's specification digest and utility model title, may do a little simplification or omit to avoid the making object of this part, specification digest and utility model title fuzzy, and this simplification or omit can not be for limiting scope of the present utility model.
The problem existing in silicon via devices in view of above-mentioned and/or existing high-speed wideband light interconnection, has proposed the utility model.
Therefore, an object of the present utility model is to provide a kind of silicon via devices that is applied to high-speed wideband light interconnection, do not affect silicon based photon device in advance under, realize the high-speed and high-density interconnection of photonic device and electronic chip.
For solving the problems of the technologies described above, the utility model provides following technical scheme: a kind of silicon via devices that is applied to the interconnection of high-speed wideband light, comprise, realized the single chip integrated Semiconductor substrate of photonic device, described Semiconductor substrate has front and back, in described Semiconductor substrate, be provided with photonic device, described photonic device has contact zone, and described contact zone is connected with electrode; Insulating barrier, described insulating barrier is filled in dead ring and the back side of described Semiconductor substrate; TSV deep hole, described TSV deep hole is disposed with barrier layer, Seed Layer and conducting metal by TSV inner walls of deep holes to TSV deep hole center, its one end is connected with the first salient point with a RDL at the described back side, and the other end is connected with the electrode bottom edge in described front; The first electronic device and described the first salient point form and are electrically connected; The second electronic device and described the second salient point form and are electrically connected.
As a kind of preferred version that is applied to the silicon via devices of high-speed wideband light interconnection described in the utility model, wherein: described Semiconductor substrate is Silicon-On-Insulator wafer, described Silicon-On-Insulator wafer comprises top silicon layer, silicon substrate, and being arranged at the oxide insulating layer between described top silicon layer and described silicon substrate, described Silicon-On-Insulator wafer has the first interarea and the second interarea.
As a kind of preferred version that is applied to the silicon via devices of high-speed wideband light interconnection described in the utility model, wherein: described in be applied to the interconnection of high-speed wideband light silicon via devices also comprise, substrate, described substrate is connected with described the 3rd salient point.
As a kind of preferred version that is applied to the silicon via devices of high-speed wideband light interconnection described in the utility model, wherein: described dead ring forms prior to described TSV deep hole.
The utility model provides a kind of silicon via devices that is applied to the interconnection of high-speed wideband light, and compared with prior art, its beneficial effect is:
(1) save the independent manufacture of photon chip in optical-electric module, aim at respectively, installation step one by one; And then realization silicon based photon device monolithic integrated technique on SOI wafer;
(2) fully use the manufacture that CMOS technique completes electronic chip, and then significantly reduce photoelectricity and mix integrated cost;
(3) can reduce module size, increase the port density of optical network device, reduce power consumption;
(4) utilize TSV (Through-Silicon Via) technology, in the enterprising hole and connecting up again of working of the Silicon photonics wafer that completes the sub-device of the integrated active passive light of monolithic, for optical chip and control chip thereof provide very-short-reach electric interconnection, can improve integration density, reduce the impact of interconnection line on high-frequency high-speed;
(5) RDL on SOI wafer is more suitable for the advanced COMS electrical chip that assembly performance is higher, technology node constantly dwindles;
(6) on applicable sheet, photoelectricity three-dimensional is integrated; Realize supercomputing, the transmission of high-speed wideband signal.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1～Figure 10 is the schematic diagram of the product that obtains of each step of the manufacture method of a kind of silicon via devices that is applied to high-speed wideband light interconnection described in the utility model;
Figure 11 is the schematic diagram of the Semiconductor substrate of the utility model bonding wafer support plate;
Figure 12 is the schematic diagram after the Semiconductor substrate of the utility model attenuate bonding wafer support plate, compares with Figure 11, and the Semiconductor substrate thickness at the back side is thin described in Figure 12;
Figure 13 is the schematic flow sheet of the manufacture method of the utility model silicon via devices of being applied to high-speed wideband light interconnection.
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail.
A lot of details have been set forth in the following description so that fully understand the utility model, but the utility model can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization without prejudice to the utility model intension in the situation that, so the utility model is not subject to the restriction of following public specific embodiment.
Secondly, the utility model is described in detail in conjunction with schematic diagram, when the utility model embodiment is described in detail in detail; for ease of explanation; the profile that represents device architecture can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the utility model protection at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
The utility model proposes a kind of manufacture method 700 that is applied to the silicon via devices of high-speed wideband light interconnection, please refer to shown in Figure 13, this manufacture method comprises the steps:
Step 710, first provides one to complete the single chip integrated Semiconductor substrate of photonic device, and described Semiconductor substrate has front and back, is provided with photonic device on it, and described photonic device has contact zone, and described contact zone is connected with electrode.
Concrete, as shown in Figure 1, on photonic device 100 or contact zone 101 is around set, on contact zone 101, be connected with electrode 102.Described photonic device 100 comprises active device and/or passive device, can be silicon electrooptic modulator and/or germanium photodetector and/or array waveguide grating etc.
In this execution mode, Semiconductor substrate adopts Silicon-On-Insulator wafer, and it has comprised top silicon layer, silicon substrate, and be arranged at the oxide insulating layer between described top silicon layer and described silicon substrate.
Wherein, germanium photodetector active area is on the top of described top silicon layer, and array waveguide grating (AWG) and silicon electrooptic modulator are in top silicon layer manufacture.
Step 720, forms dead ring to the electrode bottom edge place in described front from described back-etching.
As shown in Figure 2, from the back side, through chemical wet etching, form idle loop, dead ring 200, and dead ring 200 passes straight through to positive electrode 102 bottom edge places.
Step 730, the inner and described back side fill insulant at described dead ring, makes in dead ring and the back side forms insulating barrier 300.
As shown in Figure 3, in this execution mode, pass through TEOS(tetra-ethyl-ortho-silicate) process deposits insulating barrier 300, with the back side and the filling dead ring 200 of the Semiconductor substrate that insulated.It is pointed out that depositing insulating layer 300 in this step, its filling mode TEOS(tetra-ethyl-ortho-silicate) be a kind of possible implementation, and should not be considered as the restriction to the utility model " depositing insulating layer 300 ".Wherein, the insulating material of described dead ring 200 interior fillings (insulating barrier 300 that deposition forms), should be a kind of material with good filling capacity and low K value.
Step 740, the inner circular part that the insulating barrier chemical wet etching from the back side falls described dead ring formation divides formation TSV deep hole until the electrode bottom edge place in described front.
As shown in Figure 4, the inner circular part being formed by dead ring 200 in upper step is given to chemical wet etching to be fallen, form TSV deep hole 400, the part etching away comprises that insulating material and the dead ring 200 on insulating barrier 300 corresponding to the inner circle part of dead ring 200 formation encircles silicon substrate, oxide insulating layer, top silicon layer and the top, passivation layer of enclosing successively, until positive electrode 102 bottom edge places.As it will be recognized by those skilled in the art that current TSV deep hole 400 is to be all connected with the electrode 102 of photonic device in front; But in fact also having another method, is exactly that TSV deep hole 400 can be connected with the ohmic contact of photonic device, i.e. formation interconnects with the Metal Contact in described Semiconductor substrate.In this execution mode, only with TSV deep hole 400, in front, illustrate with the mode that the electrode 102 of photonic device is connected, be not limited in this kind of mode.
Step 750, deposited barrier layer and Seed Layer successively on insulating barrier and in TSV deep hole, and in TSV deep hole filled conductive metal.
As shown in Fig. 5～Fig. 7, elder generation's deposited barrier layer 401 on insulating barrier 300, then on 401 surfaces, described barrier layer, deposit Seed Layer 402, last filled conductive metal 403 overleaf and in TSV deep hole 400, can select to fill up conducting metal 403 or not fill up conducting metal 403, in this execution mode, the conducting metal 403 of filling can be copper or tungsten etc.
Step 760, the conductive gold symbolic animal of the birth year in formation and described TSV deep hole is electrically connected overleaf a RDL and the first salient point, and the 2nd RDL and the second salient point, the 3rd RDL and the 3rd salient point.
As shown in Figure 8, etching is carried out in the barrier layer 401 at the back side and Seed Layer 402; Then, the described back side form with TSV deep hole 400 in conducting metal 403 RDL500 and the first salient point 501 that are electrically connected mutually, the 2nd RDL502 that can be connected with electronic device and the second salient point 503, and the 3rd RDL504 that can be connected with substrate and the 3rd salient point 505.
Step 770, is connected described the first salient point, the second salient point respectively with the first electronic device, the second electronic device.
As shown in Figure 9, by section, the back side, lose money instead of making money electrical chip, the first salient point 501, the second salient point 503 are connected with the first electronic device 600 and the second electronic device 601 respectively, complete the silicon via devices that is applied to the interconnection of high-speed wideband light.
Certainly, after the first salient point 501, the second salient point 503 are connected with the first electronic device 600 and the second electronic device 601 respectively, then the 3rd salient point 505 is connected with substrate 800, is accomplished to the assembling of substrate 800.As shown in figure 10.
In another embodiment, with reference to the manufacture method 700 that is applied to the silicon via devices of high-speed wideband light interconnection, at this, do not tire out and state one by one in the lump.In order to guarantee to add the thickness of having realized the single chip integrated Semiconductor substrate of photonic device man-hour, providing one to complete after the single chip integrated Semiconductor substrate of photonic device, first bonding wafer support plate 900 when being faced with, to guarantee whole thickness, Semiconductor substrate described in attenuate then, as shown in Figure 11, Figure 12, compare with Figure 11, the Semiconductor substrate thickness at the back side is thin described in Figure 12.And then through forming dead ring 200 to the techniques such as electrode bottom edge place in described front from described back-etching, until before described the first salient point 501, the second salient point 503 are connected with the first electronic device 600, the second electronic device 601 respectively, remove again interim bonding, remove wafer support plate 900, shown in Figure 8.Finally complete the manufacture of the silicon via devices that is applied to the interconnection of high-speed wideband light.
The utility model also provides a kind of silicon-based optical interconnection device, in one embodiment, referring to Fig. 1～Fig. 9, it has comprised, the integrated Semiconductor substrate of photonic device 100, described Semiconductor substrate has front and back, is provided with photonic device 100 in described Semiconductor substrate, described photonic device 100 has contact zone 101, and described contact zone 101 is connected with electrode 102; Insulating barrier 300, described insulating barrier 300 is filled in dead ring 200 and the back side of described Semiconductor substrate; TSV deep hole 400, and to TSV deep hole 400 centers, be disposed with barrier layer 401, Seed Layer 402 and conducting metal 403 by TSV deep hole 400 inwalls, its one end is connected with the first salient point 501 with a RDL500 at the described back side, and the other end is connected with electrode 102 bottom edge in described front; The first electronic device 600, and the first electronic device 600 forms and is electrically connected with described the first salient point 501; The second electronic device 601, and the second electronic device 601 forms and is electrically connected with described the second salient point 503.
In another embodiment, referring to Fig. 1～Figure 10, by the 3rd salient point 505, be connected with substrate 800, be accomplished to the assembling of substrate 800, therefore be applied to the silicon via devices of high-speed wideband light interconnection, also comprised substrate 800.
Semiconductor substrate can adopt and comprise top silicon layer, silicon substrate, and the silicon-on-insulator that is arranged at the oxide insulating layer between described top silicon layer and described silicon substrate.
As can be seen here, be different from conventional Via-last TSV technique, first etch TSV, then deposition of insulative material, more optionally etching away the insulating material bottom TSV, the electrode of finally filling metal and Wafer front photonic device in TSV forms interconnection; What the utility model adopted is first to etch wide ring with fill insulant, and then etching is insulated the silicon formation TSV deep hole that ring surrounds, and the electrode of finally filling metal and Wafer front photonic device in TSV deep hole forms interconnection.
The utility model adopts back side integrated CMOS device, and monolithic integrated multiple Si photonic device in front provides the larger degree of freedom, also guarantees that following light source coupled modes can have more selection to photon part monolithic Integrated design; And the formation of wide ring has increased the thickness of insulating barrier, be conducive to the filling of low-k material simultaneously, reduce so widely TSV parasitic capacitance, be conducive to the transmission of high-speed wideband signal; Simultaneously, TSV forms after filling insulating material, avoided need to when TSV metallizes, first optionally etching away the insulating material of TSV bottom and many technique difficult problems of bringing thus in traditional handicraft, be more conducive to be connected to from the back side electrode of Wafer front photonic device.
It should be noted that, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although the utility model is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the technical solution of the utility model, and not departing from the spirit and scope of technical solutions of the utility model, it all should be encompassed in the middle of claim scope of the present utility model.
Claims (4)
1. a silicon via devices that is applied to the interconnection of high-speed wideband light, is characterized in that: comprises,
Realized the single chip integrated Semiconductor substrate of photonic device, described Semiconductor substrate has front and back, in described Semiconductor substrate, is provided with photonic device, and described photonic device has contact zone, and described contact zone is connected with electrode;
Insulating barrier, described insulating barrier is filled in dead ring and the back side of described Semiconductor substrate;
TSV deep hole, described TSV deep hole is disposed with barrier layer, Seed Layer and conducting metal by TSV inner walls of deep holes to TSV deep hole center, its one end is connected with the first salient point with a RDL at the described back side, and the other end is connected with the electrode bottom edge in described front;
The first electronic device and described the first salient point form and are electrically connected;
The second electronic device and the second salient point form and are electrically connected.
2. the silicon via devices that is applied to high-speed wideband light interconnection according to claim 1, is characterized in that:
Described Semiconductor substrate is Silicon-On-Insulator wafer, described Silicon-On-Insulator wafer comprises top silicon layer, silicon substrate, and be arranged at the oxide insulating layer between described top silicon layer and described silicon substrate, described Silicon-On-Insulator wafer has the first interarea and the second interarea.
3. the silicon via devices that is applied to high-speed wideband light interconnection according to claim 1, is characterized in that: described in be applied to the interconnection of high-speed wideband light silicon via devices also comprise,
Substrate, described substrate is connected with the 3rd salient point.
4. the silicon via devices that is applied to the interconnection of high-speed wideband light according to claim 1, is characterized in that: described dead ring forms prior to described TSV deep hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420038087.7U CN203871322U (en) | 2014-01-21 | 2014-01-21 | Silicon through hole device applied to high speed broadband optical interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420038087.7U CN203871322U (en) | 2014-01-21 | 2014-01-21 | Silicon through hole device applied to high speed broadband optical interconnection |
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| CN203871322U true CN203871322U (en) | 2014-10-08 |
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| CN201420038087.7U Expired - Lifetime CN203871322U (en) | 2014-01-21 | 2014-01-21 | Silicon through hole device applied to high speed broadband optical interconnection |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103787264A (en) * | 2014-01-21 | 2014-05-14 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method applied to high-speed broadband optical interconnection TSV device and device thereof |
| CN111312676A (en) * | 2020-02-25 | 2020-06-19 | 杰华特微电子（杭州）有限公司 | Fan-out type packaging part and manufacturing method thereof |
-
2014
- 2014-01-21 CN CN201420038087.7U patent/CN203871322U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103787264A (en) * | 2014-01-21 | 2014-05-14 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method applied to high-speed broadband optical interconnection TSV device and device thereof |
| CN103787264B (en) * | 2014-01-21 | 2016-06-15 | 华进半导体封装先导技术研发中心有限公司 | The manufacture method of a kind of silicon via devices being applied to high-speed wideband light network and device thereof |
| CN111312676A (en) * | 2020-02-25 | 2020-06-19 | 杰华特微电子（杭州）有限公司 | Fan-out type packaging part and manufacturing method thereof |
| CN111312676B (en) * | 2020-02-25 | 2021-11-09 | 杰华特微电子股份有限公司 | Fan-out type packaging part and manufacturing method thereof |
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