CN105321929A - Three-dimensional photoelectric integrated structure and manufacturing method thereof - Google Patents
Three-dimensional photoelectric integrated structure and manufacturing method thereof Download PDFInfo
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- CN105321929A CN105321929A CN201510528257.9A CN201510528257A CN105321929A CN 105321929 A CN105321929 A CN 105321929A CN 201510528257 A CN201510528257 A CN 201510528257A CN 105321929 A CN105321929 A CN 105321929A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
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- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000013307 optical fiber Substances 0.000 claims abstract description 17
- 230000005622 photoelectricity Effects 0.000 claims description 35
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 19
- 229910052760 oxygen Inorganic materials 0.000 claims description 19
- 239000001301 oxygen Substances 0.000 claims description 19
- 239000011521 glass Substances 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 21
- 230000005693 optoelectronics Effects 0.000 abstract description 17
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- 239000010410 layer Substances 0.000 abstract 2
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 31
- 239000006185 dispersion Substances 0.000 description 7
- 238000000605 extraction Methods 0.000 description 4
- 230000035800 maturation Effects 0.000 description 4
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- 238000004377 microelectronic Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
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- 238000005265 energy consumption Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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Abstract
The invention discloses a three-dimensional photoelectric integrated structure and a manufacturing method thereof, wherein the three-dimensional photoelectric integrated structure comprises: an optoelectronic chip; rewiring the medium; an electronic device; the substrate, the said rewiring medium is fixed on the said substrate through the said solder ball; an optical fiber coupled with the photonic device. By arranging the multiple dielectric layers and arranging the interconnection metal wires in the multiple dielectric layers, the mature rewiring technology is adopted, the process is simple, the input and output interfaces are led out, the input and output interfaces can be flexibly distributed according to the requirement of subsequent integration, so that the interlayer interconnection is realized, the silicon through hole technology is avoided, the performance of a photonic chip is ensured, in addition, the optoelectronic device is arranged on the same side of the interconnection medium and the substrate, namely the optoelectronic device is interconnected by back-off, the transmission rate is improved, and the heat dissipation effect is improved.
Description
Technical field
The present invention relates to optoelectronic integrated technology field, particularly relate to a kind of three-dimensional photoelectricity integrated morphology and preparation method thereof.
Background technology
Silicon based photon device and the advantage such as complementary metal oxide semiconductors (CMOS) (CMOS) process compatible, size is little, communication band is transparent, large bandwidth, low delay, low energy consumption, low crosstalk, energy and microelectronic chip carry out mixing or single-chip integration.At present, silicon optoelectronic monolithic integrated circuit has realized highly integrated, and modulator and corresponding driving, waveguide device, detector and the corresponding amplifying circuit that receives all can realize single-chip integration.Because silicon itself is indirect gap semiconductor, luminous efficiency fails to reach current demand at a high speed, but a lot of methods of integration laser are verified.Silicon photon monolithic integrated circuit obtains in the field such as optical communication, light network and develops fast, and current silicon optoelectronic monolithic integrated circuit uses SOI substrate, adopts CMOS technology to process.
In order to realize the integrated of silicon light photoelectron monolithic and CPU and Memory or remaining ASIC.The concept of photoelectron SiP (systeminpackage) more extensively proposes, but how to realize both integrated, has a lot of solutions at present, carry recently more be 3D optoelectronic integrated technology.
But current 3D optoelectronic integrated technology exists following problem: one, use silicon through hole (TSV) Integration ofTechnology microelectronic chip on silicon optical chip, need a lot of silicon through hole holes, but current silicon through hole technology immature, affect photon chip performance; Two, for ensureing the normal work of microelectronic chip, need the RDL (redistributionlayer) of multilayer, in general complex process, opto-electronic device is more responsive to temperature simultaneously, integrated microelectronic chip on photon chip, heat radiation is also a difficult problem.
Summary of the invention
The application provides a kind of three-dimensional photoelectricity integrated morphology and preparation method thereof, solves integrated technology of the prior art and causes the poor performance of photon chip, complex process and the technical problem of heat dispersion difference.
The application provides a kind of three-dimensional photoelectricity integrated morphology, and described three-dimensional photoelectricity integrated morphology comprises:
Opto chip, comprise oxygen buried layer, top layer connected medium, top layer silicon, back-reflection grating, photonic device, described top layer silicon is arranged between described oxygen buried layer and described top layer connected medium, described photonic device is arranged in described top layer silicon, and the photonic device pad of described photonic device is arranged on described top layer connected medium;
Wired media again, be arranged on described opto chip, comprise multiple dielectric layer, be arranged in described dielectric layer and for be electrically connected described photonic device pad metal wire, be arranged at described in again in wired media away from the lower metallized salient point contacted on the surface of described opto chip and with metal wire, the soldered ball being arranged at described lower metallized salient point;
Electronic device, is arranged in the dielectric layer near described opto chip on described multiple dielectric layer, and electronic device pad and the described metal wire of described electronic device are in electrical contact;
Substrate, described wired media is again fixed on described substrate by described soldered ball;
Optical fiber, with described back-scattering light gate coupling.
Preferably, described optical fiber is arranged on described oxygen buried layer, and the bearing of trend of described optical fiber is identical with described back-reflection grating diffration direction.
Preferably, described optical fiber and described photonic device adopt grating coupled mode.
Preferably, described photonic device pad is consistent relative to the direction of described electronic device with described electronic device pad relative to the direction of described photonic device.
Preferably, described photonic device pad can be contrary relative to the direction of described electronic device with described electronic device pad relative to the direction of described photonic device.
The application also provides a kind of manufacture method of three-dimensional photoelectricity integrated morphology, and for making described three-dimensional photoelectricity integrated morphology, described manufacture method comprises:
Obtain described opto chip, the oxygen buried layer of described opto chip and top layer silicon are provided with substrate silicon;
Described electronic device is placed on described top layer connected medium;
Form wired media again, and described metal wire is buried in wired media again, the described lower metallized salient point that the surface that described wired media is again opposing with described opto chip contacts with described metal wire, be arranged at the described soldered ball of described lower metallized salient point;
Surface opposing with described opto chip in wired media again arranges interim bonding slide glass;
Remove described substrate silicon, then remove described interim bonding slide glass, cleaning, and be fixed on described substrate by described soldered ball;
Described optical fiber is fixed on described oxygen buried layer, obtains described three-dimensional photoelectricity integrated morphology.
The application's beneficial effect is as follows:
The three-dimensional photoelectricity integrated morphology of the application is by arranging multilayer dielectricity layer, and interconnect metallization lines is set in multilayer dielectricity layer, have employed the wiring technique again of this maturation, technique is simple, realize the extraction of input/output interface, can according to follow-up integrated needs, distribute input/output interface flexibly, thus achieve inter-level interconnects, and avoid employing silicon through hole technology, ensure that the performance of photon chip, in addition, described opto-electronic device is arranged at the same side of described connected medium and described substrate, namely described opto-electronic device is made to use back-off interconnection, not only improve transmission rate, and improve radiating effect, solve the poor performance that integrated technology of the prior art causes photon chip, complex process and the technical problem of heat dispersion difference.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described by the accompanying drawing used required in describing embodiment below, apparently, the accompanying drawing in the following describes is only some embodiments of the present invention.
Fig. 1 is the structural representation of a kind of three-dimensional photoelectricity integrated morphology of the application's better embodiment;
Fig. 2 is the manufacture method flow chart of three-dimensional photoelectricity integrated morphology in Fig. 1;
Fig. 3-11 is the manufacture method three-dimensional photoelectricity integrated morphology schematic flow sheet adopted in Fig. 2;
Figure 12 is the structural representation of a kind of three-dimensional photoelectricity integrated morphology of another execution mode of the application;
Figure 13 is the structural representation of a kind of three-dimensional photoelectricity integrated morphology of the another execution mode of the application;
The structural representation of Figure 14 the application a kind of three-dimensional photoelectricity integrated morphology of an execution mode again.
Embodiment
The embodiment of the present application, by providing a kind of three-dimensional photoelectricity integrated morphology and preparation method thereof, solves integrated technology of the prior art and causes the poor performance of photon chip, complex process and the technical problem of heat dispersion difference.
Technical scheme in the embodiment of the present application is for solving the problems of the technologies described above, and general thought is as follows:
A kind of three-dimensional photoelectricity integrated morphology, described three-dimensional photoelectricity integrated morphology comprises:
Opto chip, comprise oxygen buried layer, top layer connected medium, top layer silicon, back-reflection grating, photonic device, described top layer silicon is arranged between described oxygen buried layer and described top layer connected medium, described photonic device is arranged in described top layer silicon, and the photonic device pad of described photonic device is arranged on described top layer connected medium;
Wired media again, be arranged on described opto chip, comprise multiple dielectric layer, be arranged in described dielectric layer and for be electrically connected described photonic device pad metal wire, be arranged at described in again in wired media away from the lower metallized salient point contacted on the surface of described opto chip and with metal wire, the soldered ball being arranged at described lower metallized salient point;
Electronic device, is arranged in the dielectric layer near described opto chip on described multiple dielectric layer, and electronic device pad and the described metal wire of described electronic device are in electrical contact;
Substrate, described wired media is again fixed on described substrate by described soldered ball;
Optical fiber, is coupled with described back-reflection grating.
The three-dimensional photoelectricity integrated morphology of the application is by arranging multilayer dielectricity layer, and interconnect metallization lines is set in multilayer dielectricity layer, have employed the wiring technique again of this maturation, technique is simple, realize the extraction of input/output interface, can according to follow-up integrated needs, distribute input/output interface flexibly, thus achieve inter-level interconnects, and avoid employing silicon through hole technology, ensure that the performance of photon chip, in addition, described opto-electronic device is arranged at the same side of described connected medium and described substrate, namely described opto-electronic device is made to use back-off interconnection, not only improve transmission rate, and improve radiating effect, solve the poor performance that integrated technology of the prior art causes photon chip, complex process and the technical problem of heat dispersion difference.
In order to better understand technique scheme, below in conjunction with Figure of description and concrete execution mode, technique scheme is described in detail.
Embodiment one
Cause the poor performance of photon chip, complex process and the technical problem of heat dispersion difference to solve integrated technology of the prior art, the application provides a kind of three-dimensional photoelectricity integrated morphology.As shown in Figure 1, described three-dimensional photoelectricity integrated morphology comprises: opto chip, again wired media, electronic device 202 and 201, optical fiber 108 and substrate 401.
Opto chip comprises oxygen buried layer 104, top layer connected medium 105, top layer silicon 101, back-reflection grating 102, photonic device 103 and 107.Described top layer silicon 101 is arranged between oxygen buried layer 104 and top layer connected medium 105, and described photonic device 103 and 107 is arranged in top layer silicon 101, and the photonic device pad 106 of photonic device 103 and 107 is arranged on described top layer connected medium 105.
When described opto chip is fixed in wired media again.Described wired media again comprises multiple dielectric layer 301, be arranged in described dielectric layer 301 and for be electrically connected photonic device pad 106 metal wire 302, be arranged at again in wired media away from the lower metallized salient point (UBM, underbumpmetallization) 303 contacted on the surface of described opto chip and with metal wire 302, the soldered ball 304 that is arranged at lower metallized salient point 303.
Electronic device 202 and 201 is arranged in the dielectric layer near described opto chip on described multiple dielectric layer 301.The electronic device pad 203 of described electronic device 202 and 201 is in electrical contact with metal wire 302.
In the present embodiment, photonic device pad 106 is consistent relative to the direction of electronic device 201,202 with electronic device pad 203 relative to the direction of photonic device 103,107, in other embodiments, as shown in figures 12 and 14, photonic device pad 106 can be contrary relative to the direction of electronic device 201,202 with electronic device pad 203 relative to the direction of photonic device 103,107.
Optical fiber 108 is arranged on described oxygen buried layer 104, and for being coupled with described back-reflection grating, and the diffraction direction of described back-reflection grating 102 is identical with the bearing of trend of optical fiber 108.In other embodiments, as shown in Figure 13 and Figure 14, optical fiber 108 and opto chip also can adopt grating coupled mode.
Soldered ball 304 is fixed on substrate 401.
The three-dimensional photoelectricity integrated morphology of the application is by arranging multilayer dielectricity layer 301, and interconnect metallization lines 302 is set in multilayer dielectricity layer 301, have employed the wiring technique again of this maturation, technique is simple, realize the extraction of input/output interface, can according to follow-up integrated needs, distribute input/output interface flexibly, thus achieve inter-level interconnects, and avoid employing silicon through hole technology, ensure that the performance of photon chip, in addition, described opto-electronic device is arranged at the same side of described connected medium and described substrate, namely described opto-electronic device is made to use back-off interconnection, not only improve transmission rate, and improve radiating effect, solve the poor performance that integrated technology of the prior art causes photon chip, complex process and the technical problem of heat dispersion difference.
Embodiment two
Based on same inventive concept, the application also provides a kind of manufacture method of three-dimensional photoelectricity integrated morphology, and described manufacture method is for making the three-dimensional photoelectricity integrated morphology in embodiment one.As shown in Figure 2, described manufacture method comprises the following steps:
Step S110, as shown in Figure 3, obtains described opto chip, and opto chip comprises oxygen buried layer 104, top layer connected medium 105, top layer silicon 101, back-reflection grating 102, photonic device 103 and 107.Described top layer silicon 101 is arranged between oxygen buried layer 104 and top layer connected medium 105, and described photonic device 103 and 107 is arranged in top layer silicon 101, and the pin of photonic device 103 and 107 is through described top layer connected medium 105.The oxygen buried layer 104 of described opto chip is provided with substrate silicon 109.
Step S120, as shown in Figure 4, is placed on described top layer connected medium 105 by described electronic device 202 and 201, described electronic device 202 with 201 electronic device pad 106 can be relative or opposing with described top layer connected medium 105.
Step S130, as Fig. 5, Fig. 6 and Fig. 7, form wired media again, and in wired media again, bury metal wire 302, the lower metallized salient point 303 that surface opposing with described opto chip in wired media again contacts with metal wire 302, the soldered ball 304 being arranged at lower metallized salient point 303.Described wired media comprises multiple dielectric layer 301 again time, after needing to form first medium layer, bury metal wire 302 at first medium layer; Form second dielectric layer again, bury metal wire, until after dielectric layer formed, the lower metallized salient point 303 that the surface opposing with described opto chip contacts with metal wire 302, the soldered ball 304 being arranged at lower metallized salient point 303.
Step S140, as shown in Figure 8, surface opposing with described opto chip in wired media again arranges interim bonding slide glass.
Step S150, as shown in Fig. 9, Figure 10, Figure 11, is removed substrate silicon 109, then removes interim bonding slide glass, cleaning, and be fixed on substrate 401 by soldered ball 304.
Step S160, finally, is fixed on optical fiber 108 on oxygen buried layer 104, obtains described three-dimensional photoelectricity integrated morphology.
The manufacture method of the three-dimensional photoelectricity integrated morphology of the application is by arranging multilayer dielectricity layer 301, and interconnect metallization lines 302 is set in multilayer dielectricity layer 301, have employed the wiring technique again of this maturation, technique is simple, realize the extraction of input/output interface, can according to follow-up integrated needs, distribute input/output interface flexibly, thus achieve inter-level interconnects, and avoid employing silicon through hole technology, ensure that the performance of photon chip, in addition, described opto-electronic device is arranged at the same side of described connected medium and described substrate, namely described opto-electronic device is made to use back-off interconnection, not only improve transmission rate, and improve radiating effect, solve the poor performance that integrated technology of the prior art causes photon chip, complex process and the technical problem of heat dispersion difference.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (6)
1. a three-dimensional photoelectricity integrated morphology, is characterized in that, described three-dimensional photoelectricity integrated morphology comprises:
Opto chip, comprise oxygen buried layer, top layer connected medium, top layer silicon, back-reflection grating, photonic device, described top layer silicon is arranged between described oxygen buried layer and described top layer connected medium, described photonic device is arranged in described top layer silicon, and the photonic device pad of described photonic device is arranged on described top layer connected medium;
Wired media again, be arranged on described opto chip, comprise multiple dielectric layer, be arranged in described dielectric layer and for be electrically connected described photonic device pad metal wire, be arranged at described in again in wired media away from the lower metallized salient point contacted on the surface of described opto chip and with metal wire, the soldered ball being arranged at described lower metallized salient point;
Electronic device, is arranged in the dielectric layer near described opto chip on described multiple dielectric layer, and electronic device pad and the described metal wire of described electronic device are in electrical contact;
Substrate, described wired media is again fixed on described substrate by described soldered ball;
Optical fiber, is coupled with described back-reflection grating.
2. three-dimensional photoelectricity integrated morphology as claimed in claim 1, it is characterized in that, described optical fiber is arranged on described oxygen buried layer, and the bearing of trend of described optical fiber is identical with described back-reflection grating diffration direction.
3. three-dimensional photoelectricity integrated morphology as claimed in claim 1, is characterized in that, described optical fiber and described photonic device adopt grating coupled modes.
4. three-dimensional photoelectricity integrated morphology as claimed in claim 1, is characterized in that, described photonic device pad is consistent relative to the direction of described electronic device with described electronic device pad relative to the direction of described photonic device.
5. three-dimensional photoelectricity integrated morphology as claimed in claim 1, is characterized in that, described photonic device pad can be contrary relative to the direction of described electronic device with described electronic device pad relative to the direction of described photonic device.
6. a manufacture method for three-dimensional photoelectricity integrated morphology, for making the three-dimensional photoelectricity integrated morphology as described in claim arbitrary in claim 1-5, it is characterized in that, described manufacture method comprises:
Obtain described opto chip, the oxygen buried layer of described opto chip and top layer silicon are provided with substrate silicon;
Described electronic device is placed on described top layer connected medium;
Form wired media again, and described metal wire is buried in wired media again, the described lower metallized salient point that the surface that described wired media is again opposing with described opto chip contacts with described metal wire, be arranged at the described soldered ball of described lower metallized salient point;
Surface opposing with described opto chip in wired media again arranges interim bonding slide glass;
Substrate removes described substrate silicon, then removes described interim bonding slide glass, cleaning, and is fixed on described substrate by described soldered ball;
Described optical fiber is fixed on described oxygen buried layer, obtains described three-dimensional photoelectricity integrated morphology.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105807367A (en) * | 2016-05-27 | 2016-07-27 | 湖南大学 | Photoelectric integrated circuit based on graphene photoelectric devices |
| CN105842782A (en) * | 2016-05-05 | 2016-08-10 | 湖南大学 | Monolithic photoelectric integrated circuit adopting graphene photoelectric device |
| CN110310932A (en) * | 2019-07-16 | 2019-10-08 | 上海先方半导体有限公司 | A kind of integrated encapsulation structure and manufacturing method of optical chip and electrical chip |
| CN110828443A (en) * | 2019-11-13 | 2020-02-21 | 中国科学院微电子研究所 | Substrate-free photoelectric hybrid integrated structure and preparation method thereof |
| CN110892301A (en) * | 2017-04-27 | 2020-03-17 | 纽约州立大学研究基金会 | Wafer scale bonded active photonic interposer |
| CN111679615A (en) * | 2020-07-01 | 2020-09-18 | 无锡中微亿芯有限公司 | FPGA device internally integrating network-on-chip with different bit width connecting lines |
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| CN110892301A (en) * | 2017-04-27 | 2020-03-17 | 纽约州立大学研究基金会 | Wafer scale bonded active photonic interposer |
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| CN110828443A (en) * | 2019-11-13 | 2020-02-21 | 中国科学院微电子研究所 | Substrate-free photoelectric hybrid integrated structure and preparation method thereof |
| CN111679615A (en) * | 2020-07-01 | 2020-09-18 | 无锡中微亿芯有限公司 | FPGA device internally integrating network-on-chip with different bit width connecting lines |
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