CN203870946U - Line grid scanner - Google Patents
Line grid scanner Download PDFInfo
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- CN203870946U CN203870946U CN201420211953.8U CN201420211953U CN203870946U CN 203870946 U CN203870946 U CN 203870946U CN 201420211953 U CN201420211953 U CN 201420211953U CN 203870946 U CN203870946 U CN 203870946U
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Abstract
The utility model discloses a line grid scanner. The line grid scanner is formed by a power supply, a time sequential control module, an odd-numbered line grid driving array and a even-numbered line driving array; multiple feedback loops are used in grad driving unit circuits of the odd-numbered line grid driving array and of the even-numbered line driving array to restrain internal leaked current; and the line grid scanner is characterized by low power consumption and stable operation. According to the utility model, the line grid scanner performs driving by use of mixed duty-ratio timing-sequences of 25% and 37.5%, competitions and risks can be avoided; stability of circuits are maintained; and charging and discharging functions of an output port can be finished in the same transistor, so it is beneficial to reduction of occupied areas and delaying effects. Meanwhile, high-voltage driven large-size TFT after bootstrap in circuits are fully used in charging and discharging processes of line grids, so reaction speed is improved and high-frequency display is benefited.
Description
Technical field
The utility model relates to the row gated sweep technology of active matrix light emitting flat panel display, is specifically related to the driving circuit of row gated sweep device.
Background technology
Active active illuminating display is all the modern mainstream media showing all the time, and is integrated in driving row on display pannel and the circuit of row pixel is the core technology of active active illuminating display.Traditional dull and stereotyped driving circuit is by COG technique, special driving chip to be directly installed in display panel, in recent years, along with the development of FPD technology, utilize transistor direct integrated drive electronics in display panel to replace driving chip to become popular technology.Wherein, row gated sweep device be integrated in display panel side in order to drive line by line in image element circuit, control the transistorized grid that data-signal writes, open it so that data write, and closed so that data latch.Utilize integrated row gated sweep device can reduce commercial production cost, reduce dull and stereotyped area occupied, reduce the consume of signal transmission, improve the quality of flat pannel display.
Emerging oxide thin film transistor is the popular research object of integrated circuit (IC)-components in recent years.Application oriented oxide semiconductor element is all N-type, and has the advantages that threshold voltage is negative value.Can there is leakage current problem in the integrated traditional line-scan circuit of transistor device that utilization has positive threshold voltage value, affect the normal work of circuit.Most of novel line scanner IC interior inverter modules used can produce a DC loop from high voltage to low-voltage when output LOW voltage signal, this can consume a large portion energy, is unfavorable for the application of portable flat-panel monitor.In addition, most of line scanners need by two larger-size transistors, to be completed respectively to the charging and discharging function of grid, cause scanner to take panel Area comparison large.In addition, drive closely sequential may occur the danger of race hazard, reduce the reliability of circuit, and can not in electric discharge, utilize well the high voltage of inner bootstrapping to carry out driving transistors, can cause electric discharge to turn-off row grid not in time, be difficult to meet high resolving power and drive requirement.
Utility model content
The purpose of this utility model is to provide a kind of low-power consumption, has the row gated sweep device that multiple internal feedback suppresses node leakage function.
In order to achieve the above object, the utility model is by the following technical solutions:
A kind of row gated sweep device, comprise power supply and time-sequence control module, odd-numbered line grid drives array and even number line grid to drive array, described odd-numbered line grid drives array and even number line grid to drive array to be connected with time-sequence control module with power supply respectively, wherein power supply and time-sequence control module output signal comprise high voltage, the first low-voltage, the second low-voltage, the first clock, second clock, the 3rd clock, the 4th clock, the 5th clock, the 6th clock, the 7th clock, the 8th clock, first triggers clock and second triggers clock, the first to the 8th clock signal high level equates with high voltage, the first clock wherein, second clock, the 3rd clock, the low level of the 4th clock equates with the second low-voltage, the 5th clock, the 6th clock, the 7th clock, the low level of the 8th clock equates with the first low-voltage, wherein the first low-voltage is higher than the second low-voltage.
Preferably, described odd-numbered line grid drives array to be alternately connected to form by N level first grid driver element and N level the 3rd drive element of the grid, even number line grid drives array to be alternately connected to form by N level second grid driver element and N level the 4th drive element of the grid, and wherein N is natural number.
Preferably, first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all comprise the first clock input port, second clock input port, the 3rd clock input port, the first power port, second source mouth, the 3rd power port, signals collecting mouth, the first delivery outlet and the second delivery outlet, the first power port of each drive element of the grid is connected with high voltage, second source mouth is connected with the first low-voltage, the 3rd power port is connected with the second low-voltage, signals collecting mouth is connected with the first delivery outlet of adjacent upper level in array, the first delivery outlet is connected with the signals collecting mouth of adjacent next stage in array, the second delivery outlet is connected with row grid corresponding in display, in addition, the signals collecting mouth of the first order first grid driver element of odd-numbered line array is connected with the first triggering clock, the signals collecting mouth of the first order second grid driver element of even number line array is connected with the second triggering clock.
Preferably, the first clock input port of first grid driver element, second clock input port, the 3rd clock input port are connected with the first clock, the 3rd clock, the 7th clock of time-sequence control module with power supply respectively;
The first clock input port of second grid driver element, second clock input port, the 3rd clock input port are connected with second clock, the 4th clock, the 8th clock of time-sequence control module with power supply respectively;
The first clock input port of the 3rd drive element of the grid, second clock input port, the 3rd clock input port are connected with the 3rd clock, the first clock, the 5th clock of time-sequence control module with power supply respectively;
The first clock input port of the 4th drive element of the grid, second clock input port, the 3rd clock input port are connected with the 4th clock, second clock, the 6th clock of time-sequence control module with power supply respectively.
Preferably, first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all consist of signal acquisition module, inverter modules, inner output module and scanning output module;
Signal acquisition module consists of the first to the 4th transistor, the first transistor drain electrode is connected with signals collecting mouth, source electrode is connected with the drain electrode of transistor seconds, grid is connected with grid, the first clock input port of transistor seconds, the source electrode of transistor seconds is connected with the 3rd transistor drain, as collection signal memory node Q, the 3rd transistorized source electrode is connected with the 4th transistorized drain electrode, grid is connected with the 4th transistorized grid and phase inverter output node QB, and the 4th transistorized source electrode is connected with the 3rd power port;
Inverter modules consists of the 5th to the 7th transistor, the 5th transistor drain is connected with the first power port, grid is connected with the first clock input port, source electrode is connected with the 6th transistorized drain electrode, the 7th transistor drain, as anti-phase output node QB, the 6th transistor gate is connected with signals collecting mouth, and source electrode is connected with the 3rd power port, the 7th transistor gate is connected with the tenth transistor source, and drain electrode is connected with the 3rd power port.
Inner output module is by the 8th to the tenth transistor, the first memory capacitance forms, the 8th transistor drain and the tenth transistor drain, second clock input port is connected, grid is connected with collection signal storage Q, source electrode and the 9th transistorized drain electrode, the tenth transistorized grid, the first delivery outlet is connected, the 9th transistorized grid is connected with reverse output node QB, source electrode is connected with the 3rd power port, the tenth transistor source and the first transistor source electrode, transistor seconds drain electrode, the 3rd transistor source and the 4th transistor drain are connected, first memory capacitance one end is connected with collection signal memory node Q, the other end is connected with the first delivery outlet,
Scanning output module consists of the 11 and the tenth two-transistor, the 11 transistor drain is connected with the 3rd clock input port, grid is connected with collection signal memory point Q, source electrode drains with the tenth two-transistor, the second delivery outlet is connected, the tenth two-transistor grid is connected with anti-phase output node QB, and source electrode is connected with second source mouth.
Preferably, first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all consist of signal acquisition module, inverter modules, inner output module and scanning output module;
Signal acquisition module consists of the first to the 4th transistor, the first transistor drain electrode is connected with signals collecting mouth, source electrode is connected with the drain electrode of transistor seconds, grid is connected with grid, the first clock input port of transistor seconds, the source electrode of transistor seconds is connected with the 3rd transistor drain, as collection signal memory node Q, the 3rd transistorized source electrode is connected with the 4th transistorized drain electrode, grid is connected with phase inverter output node QB, the 4th transistorized grid is connected with second clock input port, and source electrode is connected with the first delivery outlet;
Inverter modules consists of the 5th and the 6th transistor, the 5th transistor drain is connected with the first power port, grid is connected with the first clock input port, source electrode is connected with the 6th transistorized drain electrode, as anti-phase output node QB, the 6th transistor gate is connected with collection signal memory node Q, and source electrode is connected with signals collecting mouth;
Inner output module is by the 7th to the 9th transistor, the first memory capacitance forms, the 7th transistor drain and the 9th transistor drain, second clock input port is connected, grid is connected with collection signal storage Q, source electrode and the 8th transistorized drain electrode, the 9th transistorized grid, the first delivery outlet is connected, the 8th transistorized grid is connected with reverse output node QB, source electrode is connected with the 3rd power port, the 9th transistor source and the first transistor source electrode, transistor seconds drain electrode, the 3rd transistor source and the 4th transistor drain are connected, first memory capacitance one end is connected with collection signal memory node Q, the other end is connected with the first delivery outlet,
Scanning output module consists of the tenth and the 11 transistor, the tenth transistor drain is connected with the 3rd clock input port, grid is connected with collection signal memory point Q, source electrode is connected with the 11 transistor drain, the second delivery outlet, the 11 transistor gate is connected with anti-phase output node QB, and source electrode is connected with second source mouth.
The utility model has following advantage and effect with respect to prior art:
(1) the inner novel invertor module of row driver circuits of the present utility model does not need to utilize the electric resistance partial pressure function of two TFT devices that low level output is provided, and the size of device can be done littlely, is conducive to reduce area.Meanwhile, the second novel invertor can be avoided flowing through TFT to the DC loop of low-voltage from high voltage, greatly reduces the power consumption of driver.
(2) driving method of the present utility model utilizes 37.5% dutycycle timing control signal acquisition module, inverter modules and inner output module, can avoid inside to occur race hazard situation, increase stability and the reliability of circuit, be conducive to realize high frequency and show.
(3) driving method of the present utility model utilizes 25% dutycycle sequential control scanning output module, the charging and discharging function to row gate line can be focused on to same TFT and complete, and has reduced the application of large scale TFT, is beneficial to minimizing area.Meanwhile, charging and discharging process all takes full advantage of the high voltage drive large scale TFT after inside circuit bootstrapping, reduces delay effect, is conducive to high frequency and shows.
Accompanying drawing explanation
Fig. 1 is the row gated sweep device structural drawing in the utility model embodiment.
Fig. 2 is a kind of circuit theory diagrams of every one-level driver element in the utility model embodiment 1.
Fig. 3 is the working waveform figure of Fig. 2 driver element in the utility model embodiment.
Fig. 4 is every another circuit theory diagrams of one-level driver element in the utility model embodiment 2.
Fig. 5 is the working waveform figure of Fig. 4 driver element in the utility model embodiment.
Fig. 6 is row gated sweep device working waveform figure in the utility model embodiment.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the utility model is described in further detail, but embodiment of the present utility model is not limited to this.
Embodiment 1
As shown in Figure 1, a kind of row gated sweep device, comprise power supply and time-sequence control module 10, odd-numbered line grid drives array 20 and even number line grid to drive array 30, wherein power supply and time-sequence control module output signal comprise high voltage VD, the first low-voltage VS, the second low-voltage VL, the first clock CK1, second clock CK2, the 3rd clock CK3, the 4th clock CK4, the 5th clock CK5, the 6th clock CK6, the 7th clock CK7, the 8th clock CK8, first triggers clock VI1 and second triggers clock VI2, the first high level to the 8th clock signal equates with high voltage VD, the first clock CK1 wherein, second clock CK2, the 3rd clock CK3, the low level of the 4th clock CK4 equates with the second low-voltage VL, the 5th clock CK5, the 6th clock CK6, the 7th clock CK7, the low level of the 8th clock CK8 equates with the first low-voltage VS, wherein the first low-voltage VS is higher than the second low-voltage VL.
Described odd-numbered line grid drives array 20 to be alternately connected to form by N level first grid driver element and N level second grid driver element, even number line grid drives array 30 to be alternately connected to form by N level second grid driver element and N level the 4th drive element of the grid, and wherein N is natural number.
Described first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all comprise the first clock input port CLK1L, second clock input port CLK2L, the 3rd clock input port CLK2, the first power port VDD, second source mouth VSS, the 3rd power port VSL, signals collecting mouth VI, the first delivery outlet COUT and the second delivery outlet OUT, the first power port VDD of each drive element of the grid is connected with high voltage VD, second source mouth VSS is connected with the first low-voltage VS, the 3rd power port VSL is connected with the second low-voltage VL, signals collecting mouth VI is connected with the first delivery outlet COUT of adjacent upper level in array, the first delivery outlet COUT is connected with the signals collecting mouth VI of adjacent next stage in array, the second delivery outlet OUT is connected with row grid corresponding in display, wherein, the signals collecting mouth VI of the first order first grid driver element of odd-numbered line array is connected with the first triggering clock VI1, the signals collecting mouth VI of the first order second grid driver element of even number line array is connected with the second triggering clock VI2.
The first clock input port CLK1L, the second clock input port CLK2L of described first grid driver element, the 3rd clock input port CLK2 are connected with the first clock CK1, the 3rd clock CK3, the 7th clock CK7 of time-sequence control module with power supply respectively;
The first clock input port CLK1L, the second clock input port CLK2L of described second grid driver element, the 3rd clock input port CLK2 are connected with second clock CK2, the 4th clock CK4, the 8th clock CK8 of time-sequence control module with power supply respectively;
The first clock input port CLK1L, the second clock input port CLK2L of the 3rd described drive element of the grid, the 3rd clock input port CLK2 are connected with the 3rd clock CK3, the first clock CK1, the 5th clock CK5 of time-sequence control module with power supply respectively;
The first clock input port CLK1L, the second clock input port CLK2L of the 4th described drive element of the grid, the 3rd clock input port CLK2 are connected with the 4th clock CK4, second clock CK2, the 6th clock CK6 of time-sequence control module with power supply respectively.
Described first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all consist of signal acquisition module, inverter modules, inner output module and scanning output module.
As shown in Figure 2, wherein a kind of drive element of the grid circuit structure is:
Signal acquisition module 41 consists of the first to the 4th transistor, the first transistor T1 drain electrode is connected with signals collecting mouth VI, source electrode is connected with the drain electrode of transistor seconds T2, the grid of grid and transistor seconds T2, the first clock input port CLK1L is connected, the source electrode of transistor seconds T2 is connected with the 3rd transistor T 3 drain electrodes, as collection signal memory node Q, the source electrode of the 3rd transistor T 3 is connected with the drain electrode of the 4th transistor T 4, grid is connected with grid and the phase inverter output node QB of the 4th transistor T 4, the source electrode of the 4th transistor T 4 is connected with the 3rd power port VSSL,
Inverter modules 42 consists of the 5th to the 7th transistor, the 5th transistor T 5 drain electrodes are connected with the first power port VDD, grid is connected with the first clock input port CL1L, source electrode is connected with drain electrode, the 7th transistor T 7 drain electrodes of the 6th transistor T 6, as anti-phase output node QB, the 6th transistor T 6 grids are connected with signals collecting mouth VI, and source electrode is connected with the 3rd power port VSSL, the 7th transistor T 7 grids are connected with the tenth transistor T 10 source electrodes, and drain electrode is connected with the 3rd power port VSSL.
Inner output module 43 is by the 8th to the tenth transistor, the first memory capacitance C1 forms, the 8th transistor T 8 drain electrodes and the tenth transistor T 10 drain electrodes, second clock input port CK2L is connected, grid is connected with collection signal storage Q, the drain electrode of source electrode and the 9th transistor T 9, the grid of the tenth transistor T 10, the first delivery outlet COUT is connected, the grid of the 9th transistor T 9 is connected with reverse output node QB, source electrode is connected with the 3rd power port VSSL, the tenth transistor T 10 source electrodes and the first transistor T1 source electrode, transistor seconds T2 drain electrode, the 3rd transistor T 3 source electrodes and the 4th transistor T 4 drain electrodes are connected, first memory capacitance C1 one end is connected with collection signal memory node Q, the other end is connected with the first delivery outlet COUT,
Scanning output module 44 consists of the 11 and the tenth two-transistor, the 11 transistor T 11 drain electrodes are connected with the 3rd clock input port CK2, grid is connected with collection signal memory point Q, source electrode drains with the tenth two-transistor T12, the second delivery outlet OUT is connected, the tenth two-transistor T12 grid is connected with anti-phase output node QB, and source electrode is connected with second source mouth VSS.
Incorporated by reference to Fig. 3 and Fig. 6.The pulse width of the first clock CK1, second clock CK2, the 3rd clock CK3, the 4th clock CK4 is identical, dutycycle is 50%, the pulse width of the 5th clock CK5, the 6th clock CK6, the 7th clock CK7, the 8th clock CK8 is identical, dutycycle is that the pulse width of 25%, the first clock CK1, second clock CK2, the 3rd clock CK3, the 4th clock CK4 is the twice of the pulse width of the 5th clock CK5, the 6th clock CK6, the 7th clock CK7, the 8th clock CK8.
For this drive element of the grid structure, as shown in Figure 3, every one-level drive element of the grid comprises the following steps:
Gather memory phase: as the t1 time period in Fig. 3.The first clock mouth CLK1L high input voltage VD, by the first transistor T1, transistor seconds T2 and the 5th transistor T 5 are opened, signals collecting mouth VI input high level signal VD, and be input to collection signal memory point Q, in the grid of the 6th transistor T 6 and the first memory capacitance C1, the 6th transistor T 6 is opened, oppositely output node QB becomes the second low-voltage VL, the 9th transistor T 9, the tenth transistor T 10 and the tenth two-transistor T12 are turned off, second clock mouth CLK2L and the 3rd clock mouth CLK2 input respectively the second low-voltage VL and the first low-voltage VS, the first delivery outlet COUT and the second delivery outlet OUT export respectively the second low-voltage VL and the first low-voltage VS, after 37.5% time clock period, the first clock signal clk 1L becomes the second low-voltage VL, and the first transistor T1, transistor seconds T2 and the 5th transistor T 5 are turn-offed, and signals collecting mouth VI inputs the second low-voltage VL.This stage experienced for 50% clock period T time.
Signal output stage: as the t2 time period in Fig. 3.Second clock mouth CLK2L high input voltage VD, boot strap due to the first capacitor C 1, the level saltus step of collection signal memory point Q is to approximate the original high level of twice, and the 8th transistor T 8 and the 11 transistor T 11 are fully opened, the first delivery outlet COUT output HIGH voltage VD; The tenth transistor T 10 is opened, second clock input port CLK2L high voltage is fed back to the grid of the first transistor T1 source electrode, transistor seconds T2 drain electrode, the 3rd transistor T 3 source electrodes, the 4th transistor T 4 drain electrodes and the 7th transistor T 7, the 7th transistor T 7 is opened, and oppositely output node QB stable maintenance is exported the second low-voltage VL; After 6.25% cycle length, the 3rd clock mouth CLK2 high input voltage VD, the second delivery outlet OUT output HIGH voltage VD; After 25% cycle length, the 3rd clock mouth CLK2 becomes the first low-voltage VS, and collection signal memory point Q maintains the high voltage after bootstrapping, and the second delivery outlet OUT exports the first low-voltage VS, and the electric charge of storing the grid of being expert at discharges by the 11 transistor T 11; After 6.25% cycle length, second clock mouth CLK2L inputs the second low-voltage VL, and collection signal memory point Q becomes the high voltage identical with the first stage, and the first delivery outlet COUT exports the second low-voltage VL.This stage experienced for 50% clock period T time.
Reset phase: as the t3 time period in Fig. 3.The first clock mouth CLK1L input high level signal VD, the first transistor T1, transistor seconds T2, the 5th transistor T 5 are opened, collection signal memory point Q becomes low level, oppositely output node QB becomes high level, the 8th transistor T the 8, the 11 transistor T 11 is turned off, the 9th transistor T 9, the tenth two-transistor T12 are opened, and the first delivery outlet COUT and the second delivery outlet OUT maintain respectively output the second low-voltage VL and the first low-voltage VS.This stage lasts till signals collecting mouth VI high input voltage next time.
Incorporated by reference to Fig. 1 and Fig. 6, odd-numbered line grid drives array and even number line grid to drive array alternately to export gate drive signal, and the grid of the interior image element circuit of driving display is line by line realized the Presentation Function of each two field picture of display.
Embodiment 2
The technical scheme of the present embodiment is except following technical characterictic, and other technologies feature is identical with embodiment 1:
As shown in Figure 4, the first grid driver element of another described structure, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all consist of signal acquisition module 51, inverter modules 52, inner output module 53 and scanning output module 54.Wherein:
Signal acquisition module 51 consists of the first to the 4th transistor, the first transistor T1 drain electrode is connected with signals collecting mouth VI, source electrode is connected with the drain electrode of transistor seconds T2, the grid of grid and transistor seconds T2, the first clock input port CLK1L is connected, the source electrode of transistor seconds T2 is connected with the 3rd transistor T 3 drain electrodes, as collection signal memory node Q, the source electrode of the 3rd transistor T 3 is connected with the drain electrode of the 4th transistor T 4, grid is connected with phase inverter output node QB, the grid of the 4th transistor T 4 is connected with second clock input port CLK2L, source electrode is connected with the first delivery outlet COUT,
Inverter modules 52 consists of the 5th and the 6th transistor, the 5th transistor T 5 drain electrodes are connected with the first power port VDD, grid is connected with the first clock input port CLK1L, source electrode is connected with the drain electrode of the 6th transistor T 6, as anti-phase output node QB, the 6th transistor T 6 grids are connected with collection signal memory node Q, and source electrode is connected with signals collecting mouth VI; The innovation work method of phase inverter is as follows:
Only have and input when high when the first clock mouth, acquisition node Q is input signal, when Q inputs the second low-voltage, the 6th transistor T 6 is turned off, output node QB is by the 5th transistor T 5 chargings, output HIGH voltage, when Q high input voltage, the 5th transistor T 5 and the 6th transistor T 6 are opened, synchronous signal acquisition port high input voltage, output node QB is output HIGH voltage still, only has the first clock mouth of working as to input the second low-voltage, after the 5th transistor T 5 is turned off, output node QB just exports the second low-voltage.Therefore the whole course of work does not produce DC current loop, greatly reduces power consumption
Inner output module 53 is by the 7th to the 9th transistor, the first memory capacitance C1 forms, the 7th transistor T 7 drain electrodes and the 9th transistor T 9 drain electrodes, second clock input port CLK2L is connected, grid is connected with collection signal storage Q, the drain electrode of source electrode and the 8th transistor T 8, the grid of the 9th transistor T 9, the first delivery outlet COUT is connected, the grid of the 8th transistor T 8 is connected with reverse output node QB, source electrode is connected with the 3rd power port VSL, the 9th transistor T 9 source electrodes and the first transistor T1 source electrode, transistor seconds T2 drain electrode, the 3rd transistor T 3 source electrodes and the 4th transistor T 4 drain electrodes are connected, first memory capacitance C1 one end is connected with collection signal memory node Q, the other end is connected with the first delivery outlet COUT,
Scanning output module 54 consists of the tenth and the 11 transistor, the tenth transistor T 10 drain electrodes are connected with the 3rd clock input port CLK2, grid is connected with collection signal memory point Q, source electrode is connected with the 11 transistor T 11 drain electrodes, the second delivery outlet OUT, the 11 transistor T 11 grids are connected with anti-phase output node QB, and source electrode is connected with second source mouth VSS.
Incorporated by reference to Fig. 5 and Fig. 6.The pulse width of the first clock CK1, second clock CK2, the 3rd clock CK3, the 4th clock CK4 is identical, dutycycle is 50%, the pulse width of the 5th clock CK5, the 6th clock CK6, the 7th clock CK7, the 8th clock CK8 is identical, dutycycle is 25%, the pulse width of the first clock CK1, second clock CK2, the 3rd clock CK3, the 4th clock CK4 is the twice of the pulse width of the 5th clock CK5, the 6th clock CK6, the 7th clock CK7, the 8th clock CK8
For above-mentioned driver element, as shown in Figure 5, every one-level drive element of the grid comprises the following steps:
Gather memory phase: as the t1 time period in Fig. 5.The first clock mouth CLK1L high input voltage VD, the first transistor T1, transistor seconds T2 and the 5th transistor T 5 are opened, signals collecting mouth VI input high level signal VD, and be input in the source electrode and the first memory capacitance C1 of collection signal memory point Q, the 6th transistor T 6, the 6th transistor T 6 is opened, oppositely output node QB maintains high voltage, second clock mouth CLK2L and the 3rd clock mouth CLK2 input respectively the second low-voltage VL and the first low-voltage VS, and the first delivery outlet COUT and the second delivery outlet OUT export respectively the second low-voltage VL and the first low-voltage VS; After 37.5% clock period T time, the first clock signal clk 1L becomes the second low electric VL and presses, the first transistor T1, transistor seconds T2 and the 5th transistor T 5 are turn-offed, signals collecting mouth VI inputs the second low-voltage VL, oppositely output node QB becomes the second low level VL, and the 3rd transistor T 3, the 8th transistor T 8 and the 11 transistor T 11 are turned off.This stage experienced for 50% clock period T time.
Signal output stage: as the t2 time period in Fig. 5.Second clock mouth CLK2L high input voltage VD, boot strap due to the first capacitor C 1, the level saltus step of collection signal memory point Q is to approximate the original high level of twice, and the 7th transistor T 7 and the tenth transistor T 10 are fully opened, the first delivery outlet COUT output HIGH voltage VD; The 9th transistor T 9 is opened, and second clock input port CLK2L high voltage is fed back to the first transistor T1 source electrode, transistor seconds T2 drain electrode, the 3rd transistor source T3 and the 4th transistor and leaks T4; After 6.25% clock period T time, the 3rd clock mouth CLK2 high input voltage VD, the second delivery outlet OUT output HIGH voltage VD; After 25% clock period T time, the 3rd clock mouth CLK2 becomes the first low-voltage VS, and collection signal memory point Q maintains the high voltage after bootstrapping, and the second delivery outlet OUT exports the first low-voltage VS, and the electric charge of storing the grid of being expert at discharges by the tenth transistor T 10; After 6.25% clock period T time, second clock mouth CLK2L inputs the second low-voltage VL, and collection signal memory point Q becomes the high voltage identical with the first stage, and the first delivery outlet COUT exports the second low-voltage VL.This stage experienced for 50% clock period T time.
Reset phase: as the t3 time period in Fig. 5.The first clock mouth CLK1L input high level signal VD, the first transistor T1, transistor seconds T2, the 5th transistor T 5 are opened, collection signal memory point Q becomes low level, oppositely output node QB becomes high level, the 7th transistor T 7, the tenth transistor T 10 are turned off, the 8th transistor T the 8, the 11 transistor T 11 is opened, and the first delivery outlet COUT and the second delivery outlet OUT maintain respectively output the second low-voltage VL and the first low-voltage VS.This stage lasts till signals collecting mouth VI high input voltage next time.
Above-described embodiment is preferably embodiment of the utility model; but embodiment of the present utility model is not restricted to the described embodiments; other any do not deviate from change, the modification done under Spirit Essence of the present utility model and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection domain of the present utility model.
Claims (6)
1. a row gated sweep device, it is characterized in that, comprise power supply and time-sequence control module, odd-numbered line grid drives array and even number line grid to drive array, described odd-numbered line grid drives array and even number line grid to drive array to be connected with time-sequence control module with power supply respectively, wherein power supply and time-sequence control module output signal comprise high voltage, the first low-voltage, the second low-voltage, the first clock, second clock, the 3rd clock, the 4th clock, the 5th clock, the 6th clock, the 7th clock, the 8th clock, first triggers clock and second triggers clock, the first to the 8th clock signal high level equates with high voltage, the first clock wherein, second clock, the 3rd clock, the low level of the 4th clock equates with the second low-voltage, the 5th clock, the 6th clock, the 7th clock, the low level of the 8th clock equates with the first low-voltage, wherein the first low-voltage is higher than the second low-voltage.
2. row gated sweep device according to claim 1, it is characterized in that, described odd-numbered line grid drives array to be alternately connected to form by N level first grid driver element and N level the 3rd drive element of the grid, even number line grid drives array to be alternately connected to form by N level second grid driver element and N level the 4th drive element of the grid, and wherein N is natural number.
3. row gated sweep device according to claim 2, it is characterized in that, first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all comprise the first clock input port, second clock input port, the 3rd clock input port, the first power port, second source mouth, the 3rd power port, signals collecting mouth, the first delivery outlet and the second delivery outlet, the first power port of each drive element of the grid is connected with high voltage, second source mouth is connected with the first low-voltage, the 3rd power port is connected with the second low-voltage, signals collecting mouth is connected with the first delivery outlet of adjacent upper level in array, the first delivery outlet is connected with the signals collecting mouth of adjacent next stage in array, the second delivery outlet is connected with row grid corresponding in display, in addition, the signals collecting mouth of the first order first grid driver element of odd-numbered line array is connected with the first triggering clock, the signals collecting mouth of the first order second grid driver element of even number line array is connected with the second triggering clock.
4. row gated sweep device according to claim 3, it is characterized in that, the first clock input port of first grid driver element, second clock input port, the 3rd clock input port are connected with the first clock, the 3rd clock, the 7th clock of time-sequence control module with power supply respectively;
The first clock input port of second grid driver element, second clock input port, the 3rd clock input port are connected with second clock, the 4th clock, the 8th clock of time-sequence control module with power supply respectively;
The first clock input port of the 3rd drive element of the grid, second clock input port, the 3rd clock input port are connected with the 3rd clock, the first clock, the 5th clock of time-sequence control module with power supply respectively;
The first clock input port of the 4th drive element of the grid, second clock input port, the 3rd clock input port are connected with the 4th clock, second clock, the 6th clock of time-sequence control module with power supply respectively.
5. row gated sweep device according to claim 2, it is characterized in that, first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all consist of signal acquisition module, inverter modules, inner output module and scanning output module;
Signal acquisition module consists of the first to the 4th transistor, the first transistor drain electrode is connected with signals collecting mouth, source electrode is connected with the drain electrode of transistor seconds, grid is connected with grid, the first clock input port of transistor seconds, the source electrode of transistor seconds is connected with the 3rd transistor drain, as collection signal memory node Q, the 3rd transistorized source electrode is connected with the 4th transistorized drain electrode, grid is connected with the 4th transistorized grid and phase inverter output node QB, and the 4th transistorized source electrode is connected with the 3rd power port;
Inverter modules consists of the 5th to the 7th transistor, the 5th transistor drain is connected with the first power port, grid is connected with the first clock input port, source electrode is connected with the 6th transistorized drain electrode, the 7th transistor drain, as anti-phase output node QB, the 6th transistor gate is connected with signals collecting mouth, and source electrode is connected with the 3rd power port, the 7th transistor gate is connected with the tenth transistor source, and drain electrode is connected with the 3rd power port;
Inner output module is by the 8th to the tenth transistor, the first memory capacitance forms, the 8th transistor drain and the tenth transistor drain, second clock input port is connected, grid is connected with collection signal storage Q, source electrode and the 9th transistorized drain electrode, the tenth transistorized grid, the first delivery outlet is connected, the 9th transistorized grid is connected with reverse output node QB, source electrode is connected with the 3rd power port, the tenth transistor source and the first transistor source electrode, transistor seconds drain electrode, the 3rd transistor source and the 4th transistor drain are connected, first memory capacitance one end is connected with collection signal memory node Q, the other end is connected with the first delivery outlet,
Scanning output module consists of the 11 and the tenth two-transistor, the 11 transistor drain is connected with the 3rd clock input port, grid is connected with collection signal memory point Q, source electrode drains with the tenth two-transistor, the second delivery outlet is connected, the tenth two-transistor grid is connected with anti-phase output node QB, and source electrode is connected with second source mouth.
6. row gated sweep device according to claim 2, it is characterized in that, first grid driver element, second grid driver element, the 3rd drive element of the grid and the 4th drive element of the grid all consist of signal acquisition module, inverter modules, inner output module and scanning output module;
Signal acquisition module consists of the first to the 4th transistor, the first transistor drain electrode is connected with signals collecting mouth, source electrode is connected with the drain electrode of transistor seconds, grid is connected with grid, the first clock input port of transistor seconds, the source electrode of transistor seconds is connected with the 3rd transistor drain, as collection signal memory node Q, the 3rd transistorized source electrode is connected with the 4th transistorized drain electrode, grid is connected with phase inverter output node QB, the 4th transistorized grid is connected with second clock input port, and source electrode is connected with the first delivery outlet;
Inverter modules consists of the 5th and the 6th transistor, the 5th transistor drain is connected with the first power port, grid is connected with the first clock input port, source electrode is connected with the 6th transistorized drain electrode, as anti-phase output node QB, the 6th transistor gate is connected with collection signal memory node Q, and source electrode is connected with signals collecting mouth;
Inner output module is by the 7th to the 9th transistor, the first memory capacitance forms, the 7th transistor drain and the 9th transistor drain, second clock input port is connected, grid is connected with collection signal storage Q, source electrode and the 8th transistorized drain electrode, the 9th transistorized grid, the first delivery outlet is connected, the 8th transistorized grid is connected with reverse output node QB, source electrode is connected with the 3rd power port, the 9th transistor source and the first transistor source electrode, transistor seconds drain electrode, the 3rd transistor source and the 4th transistor drain are connected, first memory capacitance one end is connected with collection signal memory node Q, the other end is connected with the first delivery outlet,
Scanning output module consists of the tenth and the 11 transistor, the tenth transistor drain is connected with the 3rd clock input port, grid is connected with collection signal memory point Q, source electrode is connected with the 11 transistor drain, the second delivery outlet, the 11 transistor gate is connected with anti-phase output node QB, and source electrode is connected with second source mouth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420211953.8U CN203870946U (en) | 2014-04-28 | 2014-04-28 | Line grid scanner |
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| CN201420211953.8U CN203870946U (en) | 2014-04-28 | 2014-04-28 | Line grid scanner |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943058A (en) * | 2014-04-28 | 2014-07-23 | 华南理工大学 | Line grid scanner and drive method thereof |
| CN108694895A (en) * | 2017-04-06 | 2018-10-23 | 敦泰电子股份有限公司 | Gate line driving circuit and display device including the same |
| CN111081722A (en) * | 2019-12-31 | 2020-04-28 | 广州新视界光电科技有限公司 | Array substrate row driving circuit and display device |
-
2014
- 2014-04-28 CN CN201420211953.8U patent/CN203870946U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943058A (en) * | 2014-04-28 | 2014-07-23 | 华南理工大学 | Line grid scanner and drive method thereof |
| CN103943058B (en) * | 2014-04-28 | 2017-04-05 | 华南理工大学 | A kind of row gated sweep device and its driving method |
| CN108694895A (en) * | 2017-04-06 | 2018-10-23 | 敦泰电子股份有限公司 | Gate line driving circuit and display device including the same |
| CN111081722A (en) * | 2019-12-31 | 2020-04-28 | 广州新视界光电科技有限公司 | Array substrate row driving circuit and display device |
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Granted publication date: 20141008 Effective date of abandoning: 20170405 |