CN203644373U - Grid driving unit and grid scanning driver - Google Patents
Grid driving unit and grid scanning driver Download PDFInfo
- Publication number
- CN203644373U CN203644373U CN201320799866.4U CN201320799866U CN203644373U CN 203644373 U CN203644373 U CN 203644373U CN 201320799866 U CN201320799866 U CN 201320799866U CN 203644373 U CN203644373 U CN 203644373U
- Authority
- CN
- China
- Prior art keywords
- grid
- clock
- wire
- lead
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The utility model discloses a grid driving unit and a grid scanning driver. The internal part of the grid driving unit employs the clock and a high level to control an internal inverter module to generate a low level signal, and employs a feedback structure and a double low level voltage to control the circuit, the circuit of the grid driving unit is capable of preventing a high level from flowing into a low level direct current loop through a transistor, thus the leakage current of a transistor can be inhibited effectively, and the power consumption is reduced, so that the grid driving unit is especially suitable for transistors with negative threshold values; by employing a single edge grid scanning driver which is composed of the grid driving unit, and a clock signal control with a duty ratio of 40%, a charging function and a discharging function of a signal output terminal are integrated in the same transistor, so that the structure is simplified and the power consumption is reduced; and by employing the single edge grid scanning driver which is composed of the grid driving unit, and a clock signal control with a duty ratio of 25%, and by taking full advantages of the symmetry of the screen, a narrow edge frame effect is achieved in a display screen with a high definition.
Description
Technical field
The utility model relates to the gated sweep Driving technique field of organic light emitting diode display, is specifically related to drive element of the grid and gated sweep driver.
Background technology
Active-matrix Organic Light Emitting Diode (Active Matrix Organic Light Emitting Diode, AMOLED) display is fast-developing a kind of novel display in recent years.Early stage AMOLED display apparatus grid line scanning driver is continued to use the type of drive of LCD, by COG technique, special driving chip is pressed in and above glass substrate, drives image element circuit.In recent years, due to the development of FPD technology, integrated grid Driving technique has caused very large interest in industrial community.Utilize the grid of integrated gated sweep driver drives display picture element circuit can reduce the utilization that drives chip, reduce production costs, can also reduce the consume of signal transmission, improve display quality.
The thin film transistor (TFT) that traditional gate scanning circuit adopts is all the transistor device with positive voltage value.The emerging transistor device with negative value, particularly novel oxide thin film transistor, be applied in traditional gate scanning circuit and there will be leakage current problem, affects the normal work of circuit.Also there is the transistor of normal conducting in the drive element of the grid circuit of traditional single type (full N-type or full P type), can cause very large energy consumption in the time of work.In addition, the charging and discharging function of most of gated sweep driver output ends is completed by two very large transistors respectively, and driver can only be integrated in a side of substrate, can take so very large display base plate area, cause substrate circuit to distribute asymmetric, the narrow frame effect that is unfavorable for display, is difficult to meet high-resolution circuit design requirement.
Utility model content
The shortcoming and deficiency that exist in order to overcome prior art, the utility model provides a kind of drive element of the grid and gated sweep driver.
The purpose of this utility model is to provide a kind of low-power consumption, structure to simplify, have internal feedback ability, is specially adapted to the drive element of the grid that threshold voltage is the thin film transistor (TFT) of negative value.
Another object of the present utility model is to provide a kind of and utilizes the preparation of above-mentioned drive element of the grid establishment at monolateral gated sweep driver and the driving method thereof with features such as structure is simplified, area occupied is little, low-power consumption of display base plate one side frame.
The utility model also have an object be to provide a kind of utilize that drive element of the grid described in the first utility model object sets up can prepare thering is low-power consumption, be suitable for bilateral gated sweep driver and the driving method thereof of the features such as high resolving power demonstration at the symmetrical both sides of display base plate frame.
The technical solution of the utility model:
A kind of drive element of the grid, comprises information acquisition module, internal inverters module, first signal output module and secondary signal output module;
Described signal acquisition module is made up of the first transistor and transistor seconds, and the drain electrode of described the first transistor is as the signals collecting port VI of drive element of the grid,
The source electrode of the first transistor is connected with the drain electrode of transistor seconds; The source electrode output collection signal Q of transistor seconds;
The grid of the first transistor is connected with the grid of transistor seconds, after being connected, is connected with the output terminal QB of internal inverters module as the first input end of clock mouth CLK1L of drive element of the grid or the grid of the first transistor and the grid of transistor seconds;
Described internal inverters module is made up of the 3rd transistor and the 4th transistor, and described the 3rd transistorized drain electrode is the first power input mouth VDD,
The 3rd transistorized grid is connected with the first input end of clock mouth; The 3rd transistorized source electrode is connected the exit point QB as internal inverters module with the 4th transistorized drain electrode,
Described the 4th transistorized grid is connected with the source electrode of transistor seconds, and described the 4th transistorized source electrode is connected with the first input end of clock mouth CLK1L;
Described first signal output module is made up of the 5th transistor, the 6th transistor, the 7th transistor and the first memory capacitance, and described the 5th transistorized drain electrode is connected with the 7th transistorized drain electrode, as the second clock input port CLK2L of drive element of the grid;
Described the 5th transistorized grid is connected with the source electrode of transistor seconds, and described the 5th transistorized source electrode is connected with the 6th transistorized drain electrode, the 7th transistorized grid, as first signal output port COUT;
Described the 6th transistorized grid is connected with internal inverters exit point QB; Described the 6th transistorized source electrode is as the second source input port VSSL of drive element of the grid;
Described the 7th transistorized source electrode is connected with the source electrode of the first transistor, the drain electrode of transistor seconds respectively, and described first memory capacitance one end is connected with transistor seconds source electrode, and the other end of the first memory capacitance is connected with first signal output port;
Described secondary signal output module is made up of the 8th transistor and the 9th transistor, and the 8th transistorized drain electrode is as the 3rd clock input port CLK2 of drive element of the grid,
The 8th transistorized grid is connected with the source electrode of transistor seconds, and the 8th transistorized source electrode is connected with the 9th transistorized drain electrode, as the secondary signal output port OUT of drive element of the grid;
Described the 9th transistorized grid is connected with internal inverters exit point, and described the 9th transistorized source electrode is as the 3rd power input mouth VSS of drive element of the grid.
The transistor of described drive element of the grid is N-type thin film transistor (TFT).
Described internal inverters module is controlled by the first clock input signal CLK1L, and provide low level output by the first input end of clock mouth CLK1L, be specially: when the first clock signal input terminal input high level, the source electrode output collection signal Q of transistor seconds is if high level, the output port QB point of internal inverters output high level, in the time that the first clock input signal CLK1L is input as low level, internal inverters output port QB point output low level;
If the source electrode of transistor seconds output collection signal Q point input low level, internal inverters output port QB point output high level so.
A kind of gated sweep driver, comprise the drive element of the grid of three power supply lead wires, four clock signals lead-in wire and the cascade of N level, described N is natural number, described three power supply lead wires are respectively first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL, and described four clock signals lead-in wire is respectively the first clock lead-in wire AL, second clock lead-in wire A, the 3rd clock lead-in wire BL and the 4th clock lead-in wire B;
The concrete overlapping mode of drive element of the grid of described N level cascade is as follows:
The first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS of drive element of the grid are connected with first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL respectively;
The input port VI of described every one-level drive element of the grid is connected with the first signal output port COUT of its upper level N-1 level drive element of the grid, wherein, the input port VI of first order drive element of the grid is as the trigger pulse input port of gated sweep driver;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of odd number is connected with the first clock lead-in wire AL; Its second clock input port CLK2L is connected with the 3rd clock lead-in wire BL, and its 3rd input end of clock mouth CLK2 is connected with the 4th clock lead-in wire B;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of even number is connected with the 3rd clock lead-in wire BL, its second clock input port CLK2L is connected with the first clock lead-in wire AL, its the 3rd input end of clock mouth CLK2 is connected with second clock lead-in wire A, wherein the first output port of power source voltage VDD> second source input port voltage VSS> the 3rd power input mouth voltage VSSL.
A kind of driving method of gated sweep driver, comprise the steps: following in, high level is first corresponding high level of lead-in wire VD, the first low level is second corresponding low level of lead-in wire VS, the second low level is the 3rd corresponding low level of lead-in wire VL, drive clock signal duty cycle 40%, cycle t1;
Signal acquisition stage: the first input end of clock mouth CLK1L input high level signal, signals collecting port VI gathers high level signal, and stores the first memory capacitance into by the first transistor and transistor seconds;
The 5th transistor and the 8th transistor are opened, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 input respectively the second low level and the first low level, first signal output port COUT and secondary signal output port OUT export respectively the second low level and the first low level, and described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element; After the 40%t1 time, the first input end of clock mouth CLK1L is input as the second low level, and internal inverters module output port QB becomes the second low level, and the 6th transistor and the 9th transistor are turned off, and this stage lasts till the 50%t1 moment;
Signal output stage: when second clock input port CLK2L and the 3rd clock input port CLK2 are input as high level, the first memory capacitance is because bootstrap effect saltus step is to be greater than first high level corresponding to lead-in wire VD, first signal output port COUT and secondary signal output port OUT output high level, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element; The 7th transistor turns, the high level signal of second clock input signal port CLK2L feeds back the tie point n of the first transistor and transistor seconds, maintains the high voltage of the first memory capacitance;
After the 90%t1 moment, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 are input as respectively the second low level signal and the first low level signal, the electric charge that is stored in first signal output port COUT and secondary signal output port OUT discharges by the 5th transistor and the 8th transistor respectively, first signal output port COUT and secondary signal output port OUT export respectively the second low level signal and the first low level signal, and this stage lasts till the 100%t1 moment;
Signal loitering phase: the first input end of clock mouth CLK1L is input as high level signal, the first transistor and transistor seconds are opened, the electric charge that is stored in the first memory capacitance is released, the output port QB output high level signal of internal inverters module, the 6th transistor and the 9th transistor are opened, maintain first signal output port COUT and secondary signal output port OUT exports respectively the second low level signal and the first low level signal, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, this stage is maintained to signals collecting port VI input high level signal next time.
A kind of gated sweep driver, comprise be symmetrically distributed in the image element circuit grid that display both sides are odd number for driving display line number odd gates scanner driver and
The even number gated sweep driver of the image element circuit grid that is even number for driving display line number;
Described odd gates scanner driver and even number gated sweep activation configuration are identical, include the drive element of the grid of three power supply lead wires, four clock signals lead-in wire and the cascade of N level, and described N is natural number;
Described three power supply lead wires are respectively first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL, and described four clock signals lead-in wire is respectively the first clock lead-in wire AL, second clock lead-in wire A, the 3rd clock lead-in wire BL and the 4th clock lead-in wire B;
Described each drive element of the grid comprises input port VI, the first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS, the first input end of clock mouth CLK1L, second clock input port CLK2L, the 3rd input end of clock mouth CLK2, first signal output port COUT and secondary signal output port OUT;
The concrete overlapping mode of drive element of the grid of described N level cascade is as follows:
The first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS of drive element of the grid are connected with first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL respectively;
The input port VI of described every one-level drive element of the grid is connected with the first signal output port COUT of its upper level N-1 level drive element of the grid, wherein, the input port VI of first order drive element of the grid is as the trigger pulse input port of gated sweep driver;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of odd number is connected with the first clock lead-in wire AL; Its second clock input port CLK2L is connected with the 3rd clock lead-in wire BL, and its 3rd input end of clock mouth CLK2 is connected with the 4th clock lead-in wire B;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of even number is connected with the 3rd clock lead-in wire BL, and its second clock input port CLK2L is connected with the first clock lead-in wire AL, and its 3rd input end of clock mouth CLK2 is connected with second clock lead-in wire A;
Wherein the first output port of power source voltage VDD> second source input port voltage VSS> the 3rd power input mouth voltage VSSL.
A kind of driving method of gated sweep driver, if the cycle is t2, the clock signal duty cycle 25% driving, in following: driving high level is first corresponding high level of lead-in wire VD, the first low level is second corresponding low level of lead-in wire VS, and the second low level is the 3rd corresponding low level of lead-in wire VL; Concrete steps are:
Signal input phase: the first input end of clock mouth CLK1L input high level signal, the high level signal of signal input port is input in the first memory capacitance by the first transistor and transistor seconds, the 5th transistor and the 8th transistor are opened, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 be input low level signal the first low level and the second low level respectively, the first output port COUT and the second output port OUT export respectively the second low level and the first low level, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, this stage lasts till the 25%t2 moment.
The signal lag stage: the first input end of clock mouth is inputted the second low level signal, the first transistor and transistor seconds are turned off, high level signal is stored in the first memory capacitance, internal inverters module output port QB exports the second low level, the 6th transistor and the 9th transistor are turn-offed, and this stage lasts till the 50%t2 moment;
Signal output stage: second clock input port CLK2L and the 3rd input end of clock mouth CLK2 input high level signal, the first memory capacitance is due to bootstrap effect, saltus step is to be greater than first voltage corresponding to lead-in wire VD, first signal output port COUT and secondary signal output port OUT output high level signal, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, the 7th transistor is switched on, the high level signal of second clock input port feeds back to the first transistor and transistor seconds junction, maintain the high level of the first memory capacitance, this stage lasts till the 75%t2 moment,
Signal discharges the stage: second clock input port CLK2L and the 3rd input end of clock mouth CLK2 input respectively the second low level signal and the first low level, the high level of charge of first signal output port COUT and secondary signal output port OUT discharges from the 5th transistor and the 8th transistor respectively, export respectively the second low level signal and the first low level signal, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, and this stage lasts till the 100%t2 moment;
Signal loitering phase: the first input end of clock mouth CLK1L input high level signal, the first memory capacitance electric charge is released, the 5th transistor and the 8th transistor are turned off, internal inverters module output port QB exports high level signal, the 6th transistor and the 9th transistor are opened, maintain first signal output port COUT and secondary signal output port OUT exports respectively the second low level signal and the first low level signal, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, this stage is continued until signal input port VI input high level signal next time.
The beneficial effects of the utility model:
(1) the new internal inverter modules of institute's utility model can coordinate clock to drive, and in the time of output LOW voltage, has avoided DC current loop, has very effectively reduced power consumption;
(2) grid driving power has adopted feedback device and two low level control circuit, effectively prevents that thin film transistor (TFT) leakage current from producing, and is specially adapted to the film transistor device that threshold voltage is negative value;
(3) monolateral gate drivers adopts 40% duty cycle clock to drive, and bilateral gate drivers adopts 25% duty cycle clock to drive.The charging and discharging function of signal output part can be concentrated on to same transistor and complete, reduce the application of large-area transistors, effectively in high resolution display, realize narrow frame effect.
Brief description of the drawings
Fig. 1 is the circuit structure diagram of the drive element of the grid in the utility model embodiment 1;
Fig. 2 is the circuit structure diagram of the drive element of the grid in the utility model embodiment 2;
Fig. 3 is the circuit structure diagram of the monolateral gated sweep driver of the utility model;
Fig. 4 is that circuit shown in Fig. 3 utilizes 40% duty cycle clock signal driver drive element of the grid to drive sequential chart;
Fig. 5 is the working waveform figure of circuit shown in Fig. 3;
Fig. 6 is the circuit structure diagram of the bilateral gated sweep driver of the utility model;
Fig. 7 is the driving sequential chart that circuit shown in Fig. 6 utilizes 25% duty cycle clock signal driver drive element of the grid;
Fig. 8 is the working waveform figure of circuit shown in Fig. 6.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the utility model is described in further detail, but embodiment of the present utility model is not limited to this.
As shown in Figure 1, a kind of drive element of the grid, comprises information acquisition module 110, internal inverters module 120, first signal output module 130 and secondary signal output module 140;
Described signal acquisition module 110 is made up of the first transistor T1 and transistor seconds T2, and the drain electrode of described the first transistor T1 is as the signals collecting port VI of drive element of the grid,
The source electrode of the first transistor T1 is connected with the drain electrode of transistor seconds T2; The source electrode output collection signal Q of transistor seconds T2;
The grid of the first transistor T1 is connected with the grid of transistor seconds T1, as the first input end of clock mouth CLK1L of drive element of the grid;
Described internal inverters module 120 is made up of the 3rd transistor T 3 and the 4th transistor T 4, and the drain electrode of described the 3rd transistor T 3 is the first power input mouth VDD,
The grid of the 3rd transistor T 3 is connected with the first input end of clock mouth CLK1L; The source electrode of the 3rd transistor T 3 is connected the output terminal QB as internal inverters module 120 with the drain electrode of the 4th transistor T 4,
The grid of described the 4th transistor T 4 is connected with the source electrode of transistor seconds T2, and the source electrode of described the 4th transistor T 4 is connected with the first input end of clock mouth CLK1L;
Described first signal output module 130 is made up of the 5th transistor T 5, the 6th transistor T 6, the 7th transistor T 7 and the first memory capacitance C1, the drain electrode of described the 5th transistor T 5 is connected with the drain electrode of the 7th transistor T 7, as the second clock input port CLK2L of drive element of the grid;
The grid of described the 5th transistor T 5 is connected with the source electrode of transistor seconds T2, and the source electrode of described the 5th transistor T 5 is connected with the drain electrode of the 6th transistor T 6, the grid of the 7th transistor T 7, as first signal output port COUT;
The grid of described the 6th transistor T 6 is connected with internal inverters exit point QB; The source electrode of described the 6th transistor T 6 is as the second source input port VSSL of drive element of the grid;
Described the 7th transistor T 7 is as internal feedback device, the source electrode of the 7th transistor T 7 is connected with the source electrode of the first transistor T1, the drain electrode of transistor seconds T2 respectively, described first memory capacitance C1 one end is connected with transistor seconds T2 source electrode, and the other end of the first memory capacitance C1 is connected with first signal output port COUT;
Described secondary signal output module 140 is made up of the 8th transistor T 8 and the 9th transistor T 9, and the drain electrode of the 8th transistor T 8 is as the 3rd clock input port CLK2 of drive element of the grid,
The grid of the 8th transistor T 8 is connected with the source electrode of transistor seconds T2, and the source electrode of the 8th transistor T 8 is connected with the drain electrode of the 9th transistor T 9, as the secondary signal output port OUT of drive element of the grid;
The grid of described the 9th transistor T 9 is connected with internal inverters exit point, and the source electrode of described the 9th transistor T 9 is as the 3rd power input mouth VSS of drive element of the grid, the wherein charging and discharging of the 8th transistor T 8 to secondary signal output port OUT.
Transistor in described driver element is N-type thin film transistor (TFT).
The internal inverters module of driver element is by the first clock signal control, and provides low level signal by it, is specially:
When the first clock signal clk 1L input high level, if transistor seconds source electrode output collection signal Q is low level, the 4th transistor T 4 is turned off, the 3rd transistor T 3 conductings, the output port QB output high level of internal inverters; If transistor seconds source electrode output collection signal Q is high level, the 3rd transistor T 3, the 4th transistor T 4 are all opened, the output port QB of internal inverters still exports high level, avoid conductive media loop, in the time that the first clock signal clk 1L input becomes low level, the 3rd transistor T 3 is turned off, and conductive media loop is cut off, and internal inverters output port QB is output as low level.
Wherein, the first output port of power source voltage VDD> second source input port voltage VSS> the 3rd power input mouth voltage VSSL in drive element of the grid.
As shown in Figure 3, a kind of gated sweep driver, be specially single side scan driver, comprise the drive element of the grid of three power supply lead wires, four clock signals lead-in wire and the cascade of N level, described N is natural number, described three power supply lead wires are respectively first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL, and described four clock signals lead-in wire is respectively the first clock lead-in wire AL, second clock lead-in wire A, the 3rd clock lead-in wire BL and the 4th clock lead-in wire B;
The concrete overlapping mode of drive element of the grid of described N level cascade is as follows:
The first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS of drive element of the grid are connected with first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL respectively;
The input port VI of described every one-level drive element of the grid is connected with the first signal output port COUT of its upper level N-1 level drive element of the grid, wherein, the input port VI of first order drive element of the grid is as the trigger pulse input port of gated sweep driver;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid 210 of odd number is connected with the first clock lead-in wire AL; Its second clock input port CLK2L is connected with the 3rd clock lead-in wire BL, and its 3rd input end of clock mouth CLK2 is connected with the 4th clock lead-in wire B;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid 220 of even number is connected with the 3rd clock lead-in wire BL, its second clock input port CLK2L is connected with the first clock lead-in wire AL, its the 3rd input end of clock mouth CLK2 is connected with second clock lead-in wire A, wherein the first output port of power source voltage VDD> second source input port voltage VSS> the 3rd power input mouth voltage VSSL.
The driving method of above-mentioned single side scan driver: as shown in Figure 4, in following, high level is first corresponding high level of lead-in wire VD, the first low level is second corresponding low level of lead-in wire VS, the second low level is the 3rd corresponding low level of lead-in wire VL, drive clock signal duty cycle 40%, cycle t1;
Signal acquisition stage: as the t11 time period in Fig. 4, the first input end of clock mouth CLK1L input high level signal, signals collecting port VI gathers high level signal, and stores the first memory capacitance into by the first transistor and transistor seconds;
The 5th transistor and the 8th transistor are opened, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 input respectively the second low level and the first low level, first signal output port COUT and secondary signal output port OUT export respectively the second low level and the first low level, and described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element; After the 40%t1 time, the first input end of clock mouth CLK1L is input as the second low level, internal inverters module output port QB becomes the second low level, the 6th transistor and the 9th transistor are turned off, that has avoided that traditional driving circuit internal inverters module generally produces flows to the current return of electronegative potential by noble potential, greatly reduce circuit power consumption, this stage lasts till the 50%t1 moment;
Signal output stage: as the t12 time period in Fig. 4, when second clock input port CLK2L and the 3rd clock input port CLK2 are input as high level, the first memory capacitance is because bootstrap effect saltus step is to be greater than first high level corresponding to lead-in wire VD, the 5th transistor T 5 and the 8th transistor T 8 are opened completely, first signal output port COUT and secondary signal output port OUT are lossless output high level, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element; The 7th transistor turns, the high level signal of second clock input signal port CLK2L feeds back the tie point n of the first transistor and transistor seconds, maintains the high voltage of the first memory capacitance; Avoid the leakage of capacitance charge, the normal work of holding circuit.
After the 90%t1 moment, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 are input as respectively the second low level signal and the first low level signal, the electric charge that is stored in first signal output port COUT and secondary signal output port OUT discharges by the 5th transistor and the 8th transistor respectively, first signal output port COUT and secondary signal output port OUT export respectively the second low level signal and the first low level signal, and this stage lasts till the 100%t1 moment;
Signal loitering phase: as the t13 time period in Fig. 4, the first input end of clock mouth CLK1L is input as high level signal, the first transistor and transistor seconds are opened, the electric charge that is stored in the first memory capacitance is released, the output port QB output high level signal of internal inverters module, the 6th transistor and the 9th transistor are opened, maintain first signal output port COUT and secondary signal output port OUT exports respectively the second low level signal and the first low level signal, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, this stage is maintained to signals collecting port VI input high level signal next time.
As shown in Figure 5, gated sweep driver is under the cooperation of trigger pulse and clock drives, and the grid of image element circuit in driving display line by line, realizes the Presentation Function of each two field picture of display.
As shown in Figure 6, a kind of gated sweep driver, is specially bilateral scanner driver, comprise be symmetrically distributed in the image element circuit grid that display both sides are odd number for driving display line number odd gates scanner driver 510 and
The even number gated sweep driver 520 of the image element circuit grid that is even number for driving display line number;
Described odd gates scanner driver and even number gated sweep activation configuration are identical, include the drive element of the grid of three power supply lead wires, four clock signals lead-in wire and the cascade of N level, and described N is natural number;
Described three power supply lead wires are respectively first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL,
As shown in Figure 6, four of described odd gates scanner driver clock signal lead-in wires are respectively the first clock lead-in wire AL1, second clock lead-in wire A1, the 3rd clock lead-in wire BL1 and the 4th clock lead-in wire B1;
Four clock signal lead-in wires of described even number gated sweep driver are respectively the first clock lead-in wire AL2, second clock lead-in wire A2, the 3rd clock lead-in wire BL2 and the 4th clock lead-in wire B2;
Described each drive element of the grid comprises input port VI, the first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS, the first input end of clock mouth CLK1L, second clock input port CLK2L, the 3rd input end of clock mouth CLK2, first signal output port COUT and secondary signal output port OUT;
Taking odd gates scanner driver as example, illustrate that the concrete overlapping mode of drive element of the grid of N level cascade is as follows:
The first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS of drive element of the grid are connected with first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL respectively;
The input port VI of described every one-level drive element of the grid is connected with the first signal output port COUT of its upper level N-1 level drive element of the grid, wherein, the input port VI of first order drive element of the grid is as the trigger pulse input port of gated sweep driver;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid 411 of odd number is connected with the first clock lead-in wire AL1; Its second clock input port CLK2L is connected with the 3rd clock lead-in wire BL1, and its 3rd input end of clock mouth CLK2 is connected with the 4th clock lead-in wire B1;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid 412 of even number is connected with the 3rd clock lead-in wire BL, its second clock input port CLK2L is connected with the first clock lead-in wire AL, and its 3rd input end of clock mouth CLK2 is connected with second clock lead-in wire A1;
Wherein the first output port of power source voltage VDD> second source input port voltage VSS> the 3rd power input mouth voltage VSSL.
The overlapping mode of the drive element of the grid of the N level cascade of described even number gated sweep driver is identical with odd gates scanner driver.
The driving method of bilateral scanner driver is: as shown in Figure 7, if the cycle of clock is t2, drive clock signal duty cycle 25%, in following: driving high level is first corresponding high level of lead-in wire VD, the first low level is second corresponding low level of lead-in wire VS, and the second low level is the 3rd corresponding low level of lead-in wire VL; Concrete steps are:
Signal input phase: as the t21 time period in Fig. 7, the first input end of clock mouth CLK1L input high level signal, the high level signal of signal input port is input in the first memory capacitance by the first transistor and transistor seconds, the 5th transistor and the 8th transistor are opened, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 be input low level signal the first low level and the second low level respectively, the first output port COUT and the second output port OUT export respectively the second low level and the first low level, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, this stage lasts till the 25%t2 moment.
The signal lag stage: as the t22 time period in Fig. 7, the first input end of clock mouth is inputted the second low level signal, the first transistor and transistor seconds are turned off, high level signal is stored in the first memory capacitance, internal inverters module output port QB exports the second low level, the 6th transistor and the 9th transistor are turn-offed, and this stage lasts till the 50%t2 moment;
Signal output stage: as the t23 time period in Fig. 7, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 input high level signal, the first memory capacitance is due to bootstrap effect, saltus step is to be greater than first voltage corresponding to lead-in wire VD, first signal output port COUT and secondary signal output port OUT output high level signal, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, the 7th transistor is switched on, the high level signal of second clock input port feeds back to the first transistor and transistor seconds junction, maintain the high level of the first memory capacitance, this stage lasts till the 75%t2 moment,
Signal discharges the stage: as t24 time phase in Fig. 7, second clock input port CLK2L and the 3rd input end of clock mouth CLK2 input respectively the second low level signal and the first low level, the high level of charge of first signal output port COUT and secondary signal output port OUT discharges from the 5th transistor and the 8th transistor respectively, export respectively the second low level signal and the first low level signal, thereby the input of signal charge and release are concentrated on a transistor and completed, avoid the application of multiple large-area transistors, save chip area, be conducive to realize the narrow frame effect of display screen.
Described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, and this stage lasts till the 100%t2 moment;
Signal loitering phase: as t25 time phase in Fig. 7, the first input end of clock mouth CLK1L input high level signal, the first memory capacitance electric charge is released, the 5th transistor and the 8th transistor are turned off, internal inverters module output port QB exports high level signal, the 6th transistor and the 9th transistor are opened, maintain first signal output port COUT and secondary signal output port OUT exports respectively the second low level signal and the first low level signal, described first signal output port COUT output signal is transferred to the signals collecting port VI of next stage driver element, this stage is continued until signal input port VI input high level signal next time.
As shown in Figure 8, in bilateral scanner driver, odd gates scanner driver is identical with the driving method of even-line interlace driver, the two alternately exports gate drive signal, and the grid of image element circuit in driving display is line by line realized the Presentation Function of each two field picture of display.
The present embodiment, as shown in Figure 2, in signal acquisition module 111, the grid of the first transistor T1 is connected with the output terminal QB of internal inverters module 120 after being connected with the grid of transistor seconds T2; Other features are identical with embodiment 1.
Above-described embodiment is preferably embodiment of the utility model; but embodiment of the present utility model is not limited by the examples; other any do not deviate from change, the modification done under Spirit Essence of the present utility model and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection domain of the present utility model.
Claims (5)
1. a drive element of the grid, is characterized in that, comprises information acquisition module, internal inverters module, first signal output module and secondary signal output module;
Described signal acquisition module is made up of the first transistor and transistor seconds, and the drain electrode of described the first transistor is as the signals collecting port VI of drive element of the grid,
The source electrode of the first transistor is connected with the drain electrode of transistor seconds; The source electrode output collection signal Q of transistor seconds;
The grid of the first transistor is connected with the grid of transistor seconds, after being connected, is connected with the output terminal QB of internal inverters module as the first input end of clock mouth CLK1L of drive element of the grid or the grid of the first transistor and the grid of transistor seconds;
Described internal inverters module is made up of the 3rd transistor and the 4th transistor, and described the 3rd transistorized drain electrode is the first power input mouth VDD,
The 3rd transistorized grid is connected with the first input end of clock mouth; The 3rd transistorized source electrode is connected the exit point QB as internal inverters module with the 4th transistorized drain electrode,
Described the 4th transistorized grid is connected with the source electrode of transistor seconds, and described the 4th transistorized source electrode is connected with the first input end of clock mouth CLK1L;
Described first signal output module is made up of the 5th transistor, the 6th transistor, the 7th transistor and the first memory capacitance, and described the 5th transistorized drain electrode is connected with the 7th transistorized drain electrode, as the second clock input port CLK2L of drive element of the grid;
Described the 5th transistorized grid is connected with the source electrode of transistor seconds, and described the 5th transistorized source electrode is connected with the 6th transistorized drain electrode, the 7th transistorized grid, as first signal output port COUT;
Described the 6th transistorized grid is connected with internal inverters exit point QB; Described the 6th transistorized source electrode is as the second source input port VSSL of drive element of the grid;
Described the 7th transistorized source electrode is connected with the source electrode of the first transistor, the drain electrode of transistor seconds respectively, and described first memory capacitance one end is connected with transistor seconds source electrode, and the other end of the first memory capacitance is connected with first signal output port;
Described secondary signal output module is made up of the 8th transistor and the 9th transistor, and the 8th transistorized drain electrode is as the 3rd clock input port CLK2 of drive element of the grid;
The 8th transistorized grid is connected with the source electrode of transistor seconds, and the 8th transistorized source electrode is connected with the 9th transistorized drain electrode, as the secondary signal output port OUT of drive element of the grid;
Described the 9th transistorized grid is connected with internal inverters exit point, and described the 9th transistorized source electrode is as the 3rd power input mouth VSS of drive element of the grid.
2. a kind of drive element of the grid according to claim 1, is characterized in that, the transistor of described drive element of the grid is N-type thin film transistor (TFT).
3. a kind of drive element of the grid according to claim 1, it is characterized in that, described internal inverters module is controlled by the first clock input signal CLK1L, and provide low level output by the first input end of clock mouth CLK1L, be specially: when the first clock signal input terminal input high level, the source electrode output collection signal Q of transistor seconds is if high level, the output port QB point of internal inverters output high level, in the time that the first clock input signal CLK1L is input as low level, internal inverters output port QB point output low level;
If the source electrode of transistor seconds output collection signal Q point input low level, internal inverters output port QB point output high level so.
4. the gated sweep driver being formed by the drive element of the grid described in claim 1-3 any one, it is characterized in that, comprise the drive element of the grid of three power supply lead wires, four clock signals lead-in wire and the cascade of N level, described N is natural number, described three power supply lead wires are respectively first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL, and described four clock signals lead-in wire is respectively the first clock lead-in wire AL, second clock lead-in wire A, the 3rd clock lead-in wire BL and the 4th clock lead-in wire B;
The concrete overlapping mode of drive element of the grid of described N level cascade is as follows:
The first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS of drive element of the grid are connected with first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL respectively;
The input port VI of described every one-level drive element of the grid is connected with the first signal output port COUT of its upper level N-1 level drive element of the grid, wherein, the input port VI of first order drive element of the grid is as the trigger pulse input port of gated sweep driver;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of odd number is connected with the first clock lead-in wire AL; Its second clock input port CLK2L is connected with the 3rd clock lead-in wire BL, and its 3rd input end of clock mouth CLK2 is connected with the 4th clock lead-in wire B;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of even number is connected with the 3rd clock lead-in wire BL, its second clock input port CLK2L is connected with the first clock lead-in wire AL, its the 3rd input end of clock mouth CLK2 is connected with second clock lead-in wire A, wherein the first output port of power source voltage VDD> second source input port voltage VSS> the 3rd power input mouth voltage VSSL.
5. the gated sweep driver being made up of the drive element of the grid described in claim 1-3 any one, is characterized in that, comprise be symmetrically distributed in the image element circuit grid that display both sides are odd number for driving display line number odd gates scanner driver and
The even number gated sweep driver of the image element circuit grid that is even number for driving display line number;
Described odd gates scanner driver and even number gated sweep activation configuration are identical, include the drive element of the grid of three power supply lead wires, four clock signals lead-in wire and the cascade of N level, and described N is natural number;
Described three power supply lead wires are respectively first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL, and described four clock signals lead-in wire is respectively the first clock lead-in wire AL, second clock lead-in wire A, the 3rd clock lead-in wire BL and the 4th clock lead-in wire B;
Described each drive element of the grid comprises input port VI, the first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS, the first input end of clock mouth CLK1L, second clock input port CLK2L, the 3rd input end of clock mouth CLK2, first signal output port COUT and secondary signal output port OUT;
The concrete overlapping mode of drive element of the grid of described N level cascade is as follows:
The first power input mouth VDD, second source input port VSSL, the 3rd power input mouth VSS of drive element of the grid are connected with first lead-in wire VD, second lead-in wire VS and the 3rd lead-in wire VL respectively;
The input port VI of described every one-level drive element of the grid is connected with the first signal output port COUT of its upper level N-1 level drive element of the grid, wherein, the input port VI of first order drive element of the grid is as the trigger pulse input port of gated sweep driver;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of odd number is connected with the first clock lead-in wire AL; Its second clock input port CLK2L is connected with the 3rd clock lead-in wire BL, and its 3rd input end of clock mouth CLK2 is connected with the 4th clock lead-in wire B;
Progression N is that the first input end of clock mouth CLK1L of the drive element of the grid of even number is connected with the 3rd clock lead-in wire BL, and its second clock input port CLK2L is connected with the first clock lead-in wire AL, and its 3rd input end of clock mouth CLK2 is connected with second clock lead-in wire A;
Wherein the first output port of power source voltage VDD> second source input port voltage VSS> the 3rd power input mouth voltage VSSL.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320799866.4U CN203644373U (en) | 2013-12-05 | 2013-12-05 | Grid driving unit and grid scanning driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320799866.4U CN203644373U (en) | 2013-12-05 | 2013-12-05 | Grid driving unit and grid scanning driver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203644373U true CN203644373U (en) | 2014-06-11 |
Family
ID=50875600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320799866.4U Withdrawn - After Issue CN203644373U (en) | 2013-12-05 | 2013-12-05 | Grid driving unit and grid scanning driver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203644373U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103927972A (en) * | 2013-12-05 | 2014-07-16 | 华南理工大学 | Grid drive unit, grid scanning driver and driving method of grid scanning driver |
| CN104992673A (en) * | 2015-07-23 | 2015-10-21 | 京东方科技集团股份有限公司 | Inverter, gate driving circuit and display device |
| CN108648705A (en) * | 2018-03-30 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driving circuit and display device |
| CN108711399A (en) * | 2018-05-29 | 2018-10-26 | 昆山国显光电有限公司 | Emission control driving circuit, emission control driver and organic light-emitting display device |
| CN111081722A (en) * | 2019-12-31 | 2020-04-28 | 广州新视界光电科技有限公司 | Array substrate row driving circuit and display device |
| US11574597B2 (en) | 2020-10-27 | 2023-02-07 | Boe Technology Group Co., Ltd. | Gate driving unit having node isolation |
| US11935484B2 (en) | 2020-10-23 | 2024-03-19 | Hefei Boe Joint Technology Co., Ltd. | Display panel and display apparatus |
-
2013
- 2013-12-05 CN CN201320799866.4U patent/CN203644373U/en not_active Withdrawn - After Issue
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103927972A (en) * | 2013-12-05 | 2014-07-16 | 华南理工大学 | Grid drive unit, grid scanning driver and driving method of grid scanning driver |
| CN103927972B (en) * | 2013-12-05 | 2016-03-02 | 华南理工大学 | Drive element of the grid and gated sweep driver and driving method thereof |
| CN104992673A (en) * | 2015-07-23 | 2015-10-21 | 京东方科技集团股份有限公司 | Inverter, gate driving circuit and display device |
| CN104992673B (en) * | 2015-07-23 | 2017-09-22 | 京东方科技集团股份有限公司 | A kind of phase inverter, gate driving circuit and display device |
| CN108648705A (en) * | 2018-03-30 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driving circuit and display device |
| CN108711399A (en) * | 2018-05-29 | 2018-10-26 | 昆山国显光电有限公司 | Emission control driving circuit, emission control driver and organic light-emitting display device |
| CN111081722A (en) * | 2019-12-31 | 2020-04-28 | 广州新视界光电科技有限公司 | Array substrate row driving circuit and display device |
| US11935484B2 (en) | 2020-10-23 | 2024-03-19 | Hefei Boe Joint Technology Co., Ltd. | Display panel and display apparatus |
| US11574597B2 (en) | 2020-10-27 | 2023-02-07 | Boe Technology Group Co., Ltd. | Gate driving unit having node isolation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203644373U (en) | Grid driving unit and grid scanning driver | |
| CN103927972B (en) | Drive element of the grid and gated sweep driver and driving method thereof | |
| JP6794579B2 (en) | GOA circuit | |
| CN103345941B (en) | Shift register cell and driving method, shift-register circuit and display device | |
| CN107464517A (en) | Driving method, drive device, display panel and the display device of display panel | |
| CN103617775B (en) | Shift register cell, gate driver circuit and display | |
| CN102402936B (en) | Gate drive circuit unit, gate drive circuit and display device | |
| CN104537991A (en) | Forward-reverse scanning gate drive circuit | |
| CN105609042B (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN102054427A (en) | Display device and driving method thereof | |
| CN105931601B (en) | A kind of drive circuit unit and its driving method and row grid-driving integrated circuit | |
| CN110459164A (en) | Pixel-driving circuit and display device | |
| CN205900070U (en) | Drive circuit unit and gate drive integrated circuit that goes | |
| CN103943058A (en) | Line grid scanner and drive method thereof | |
| CN103065584B (en) | Power source organic electroluminescence scanning drive device and drive method thereof | |
| CN110264948A (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN106297630B (en) | Scan drive circuit and flat display apparatus with the circuit | |
| CN102968956B (en) | Scanning driver for active organic electroluminescent display and driving method thereof | |
| CN107799070A (en) | Shift register, gate driving circuit, display device and grid drive method | |
| CN104464676B (en) | Clock generation circuit of liquid crystal display device and operation method thereof | |
| CN203849978U (en) | Scanning driver and organic light-emitting display employing same | |
| CN110060616A (en) | Shift register cell and its driving method, gate driving circuit | |
| CN107134246A (en) | A kind of drive element of the grid and row gated sweep driver and its driving method | |
| CN104252843A (en) | Pulse signal merging circuit, display panel and display device | |
| CN106328064B (en) | A kind of scan drive circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140611 Effective date of abandoning: 20160302 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |