CN203840365U - General 1553B communication full-duplex transceiver and device with transceiver - Google Patents
General 1553B communication full-duplex transceiver and device with transceiver Download PDFInfo
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- CN203840365U CN203840365U CN201420265691.3U CN201420265691U CN203840365U CN 203840365 U CN203840365 U CN 203840365U CN 201420265691 U CN201420265691 U CN 201420265691U CN 203840365 U CN203840365 U CN 203840365U
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Abstract
The utility model discloses a general 1553B communication full-duplex transceiver comprising an encoder and a transmitter which is connected with the encoder. The encoder receives first data transmitted into the data receiving end of the encoder and outputs a first biphasic unipolar digital signal and a first control signal from the output end of the encoder. The input end of the transmitter receives the first biphasic unipolar digital signal and the first control signal transmitted by the encoder and outputs a bipolar phase modulation signal from the data output end. A receiver receives second data transmitted into the data receiving end of the receiver and outputs a second biphasic unipolar digital signal from the output end. The input end of a decoder receives the second biphasic unipolar digital signal transmitted by the receiver and outputs parallel data and a control signal from the data output end of the decoder. The utility model also discloses a device with the aforementioned transceiver. The device comprises an isolation transformer. The primary coil of the isolation transformer is respectively connected with the data receiving end of the receiver and the data output end of the transmitter.
Description
Technical field
The utility model relates to a kind of bus data communicator, relates in particular to a kind of 1553B transceiver and has the device of this transceiver.
Background technology
1553B bus claims again MILSTD1553B bus, is that US military aims at a kind of information transmission bus standard that airborne equipment is formulated that flies, the agreement of namely equipment room transmission.1553B bus, because it has confirmability and transmits reliably, has very high real-time, is widely used in abroad aircraft, military vehicle and carrier-borne field.
Be the CAN bus communication of application mostly in boats and ships data communication field at present, CAN bus is widely used in ship domain with its superior function.But the drawback of CAN bus mainly contains 2: transmission bandwidth is large not; To signal, transmission can not ensure high real-time.
Naval vessel is a kind of technology of intensive electronic system set being carried out to informix and function synthesized with electronics synthesization.By the subsystem networking interface standard application taking 1553B as representative in the major trunk roads of electronic comprehensive system information exchange, between 1553 buses and existing bus (as CAN bus etc.), build a bridge block, make the information of different systems can be in real time, mutually exchange exactly.1553B bus interface is to realize the critical component of electronics synthesis, and complicated and harsh environment has proposed very high requirement for its real-time and reliability.
At present more external enterprises interface chip that be 1553B bus design specially, but price is very expensive, and need supporting their other chips ability collaborative works, has therefore greatly restricted 1553B communication bus the using and develop of field, naval vessel at home.
In addition, publication number is CN201821375U, open day is on May 4th, 2011, the Chinese patent literature that name is called " 1553B bus transmission circuit " also discloses a kind of 1553B bus transmission circuit, it comprises transtation mission circuit and two parts of receiving circuit, wherein transtation mission circuit comprises the filter circuit for removing signal noise, after filter circuit, connect two high-power MOS tubes that low-power level signal are converted to high-power signal, the slope of described high-power MOS tube grid voltage is required to control according to bus transfer rate by slew rate adjustment circuit; High-power MOS tube connects the isolating transformer of output HIGH voltage signal; Receiving circuit comprises the isolating transformer that high-voltage signal is become to low-voltage signal, and isolating transformer connects two voltage comparators, the reference voltage input voltage comparator of generating circuit from reference voltage output; Signal after voltage comparator is differentiated, through adaptive digital filtering circuit filtering noise, finally outputs to 1553B communication control module.
Summary of the invention
One of the purpose of this utility model is to provide a kind of general 1553B communication full-duplex transceiver, it can receive and meets the signal of 1553B bus protocol and be converted into universal signal for user, and the universal signal that user can also be provided is converted to and meets the signal of 1553B bus protocol and send.
Another object of the present utility model is to provide a kind of device with above-mentioned general 1553B communication full-duplex transceiver, it can receive from the signal of 1553B bus and be converted into universal signal for user, can also meet the signal of 1553B bus protocol and be sent to 1553B bus being converted to from user's universal signal.
In order to reach the object of above-mentioned utility model, the utility model provides a kind of general 1553B communication full-duplex transceiver, and it comprises:
Transtation mission circuit, described transtation mission circuit comprises encoder and the transmitter being connected with encoder; Wherein said encoder has data receiver and output, and encoder receives to transmit into the first data of its data receiver and from its output exports the first two-phase unipolarity digital signal and the first control signal; Described transmitter has input and data output end, and the first two-phase unipolarity digital signal of the input received code device transmission of transmitter and the first control signal are also exported bipolarity phase modulated signal from data output end;
Receiving circuit, described receiving circuit comprises receiver and the decoder being connected with receiver; Wherein receiver has data receiver and output, and receiver receives to transmit into the second data of its data receiver and from output exports the second two-phase unipolarity digital signal; Described decoder has input and data output end, and the input of decoder receives the second two-phase unipolarity digital signal of receiver transmission, and from its data output end output parallel data and control signal.
General 1553B communication full-duplex transceiver described in the utility model is for meeting the conversion between signal and the universal signal of 1553B bus protocol.Meet the signal of 1553B bus protocol conventionally from the isolating transformer being connected with 1553B bus, universal signal refers to be directly used in the signal of general-purpose chip, as FPGA, DSP and MCU etc., normally parallel data signal and control signal.In general 1553B communication full-duplex transceiver described in the utility model, the second data and bipolarity phase modulated signal are the signal that meets 1553B bus protocol, and the first data, parallel data and control signal are universal signal; Transmitter and receiver for two-phase unipolarity digital signal and described in meet the conversion between the signal of 1553B bus protocol, encoder is for the conversion between two-phase unipolarity digital signal and described universal signal, thereby described in realizing on the whole, meets the conversion between signal and the described universal signal of 1553B bus protocol.Specifically, the signal that meets 1553B bus protocol that decoder receives receiver is converted to universal signal, and encoder is converted to by universal signal the signal that meets 1553B bus protocol and sends to transmitter; Described control signal can comprise data effective index signal, order or condition indicative signal, effective payload data index signal and check errors index signal etc., and described the first data can comprise that it is that effective payload data signal, instruction transmission data are command word or status word signal etc. that parallel data, instruction send data; Described the first control signal can be the transmission useful signal sending for control signal.
Further, in general 1553B communication full-duplex transceiver described in the utility model, described encoder comprises the synchronous code multiplex circuit, manchester encoder and the serializer that connect successively along the transmission direction of data, and described serializer is exported described the first two-phase unipolarity digital signal and the first control signal.
Further, in above-mentioned general 1553B communication full-duplex transceiver, described encoder also comprises the first digit counter and verification maker, and described the first digit counter is connected with synchronous code multiplex circuit respectively with verification maker.
In such scheme, described synchronous code multiplex circuit receives the first data; Start bit counter in the time having parallel data transmission, under the control of digit counter, the check value that synchronous code multiplex circuit generates synchronous code, verification maker forms the concurrent frame structure that meets 1553B agreement together with parallel data, then through manchester encoder by the data processing of encoding, give afterwards the first two-phase unipolarity digital signal that parallel data is converted to serial by stringization circuit and export to transmitter, the first control signal that output sends for control signal is simultaneously to transmitter.
Further, in general 1553B communication full-duplex transceiver described in the utility model, described transmitter comprises the switching gate circuit and the signal amplification shaping circuit that connect successively along the transmission direction of data, and described signal amplification shaping circuit is exported described bipolarity phase modulated signal.
In such scheme, switching gate circuit in transmitter receives the first two-phase unipolarity digital signal and the first control signal from encoder, under the control of the first control signal, give signal amplification shaping circuit by the first two-phase unipolarity digital signal, the first two-phase unipolarity digital signal is converted to bipolarity phase modulated signal by signal shaping amplifier.
Further, in general 1553B communication full-duplex transceiver described in the utility model, described receiver comprises the signal limiter, subtraction device, filter and the comparison circuit that connect successively along the transmission direction of data, and described comparison circuit is exported described the second two-phase unipolarity digital signal.
In such scheme, signal limiter in receiver receives the second data and it is carried out to signal limitations processing, through subtraction device and filter, give comparison circuit by the bipolarity analogue data after phase demodulating afterwards, finally export the second two-phase unipolarity digital signal.
Further, in general 1553B communication full-duplex transceiver described in the utility model, described decoder comprises the change-over circuit, synchronous code testing circuit and the deserializer circuit that connect successively along the transmission direction of data, and second counter, described second counter is connected with synchronous code testing circuit and deserializer circuit respectively, and described second counter triggers to control deserializer circuit by synchronous code testing circuit.
Further, in above-mentioned general 1553B communication full-duplex transceiver, described decoder also comprises verification testing circuit, and described verification check circuit is connected with synchronous code testing circuit, so that the data of synchronous code testing circuit output are carried out to verification.
In such scheme, change-over circuit in decoder receives the second two-phase unipolarity digital signal and is converted into NRZ code, detect frame synchronization through synchronous code testing circuit afterwards, second counter is in the time that synchronous code testing circuit detects frame synchronization, start and control deserializer circuit, serial data is converted to parallel data output, exports control signal simultaneously.Whether verification testing circuit is correct for detection of the data check of synchronous code testing circuit output, if correctly, receives, and incorrect providing reported to the police and packet loss.
Accordingly, based on another object of the present utility model, the utility model has also proposed a kind of device with above-mentioned general 1553B communication full-duplex transceiver, and it comprises:
Described general 1553B communication full-duplex transceiver;
Isolating transformer, the primary coil of described isolating transformer is connected respectively with the data output end of the data receiver of receiver and transmitter.
The device with above-mentioned general 1553B communication full-duplex transceiver described in the utility model, its secondary coil by isolating transformer receives signal from 1553B bus, and by its primary coil, the 1553B bus signals after transformation is flowed to receiver as the second data; Its primary coil by isolating transformer receives bipolarity phase modulated signal from transmitter, and by its secondary coil, the bipolarity phase modulated signal after transformation is sent to 1553B bus.Device described in the utility model adopts transformer isolation mode to receive/send 1553B bus signals, is because direct-coupling is unfavorable for terminal fault isolation.Under direct coupling system, a terminal fault can cause the paralysis completely of whole bus network, explicitly points out not recommendation direct coupling system in 1553B bus protocol.
Further, device described in the utility model also comprises: terminal matching transformer, the primary coil of described terminal matching transformer is connected with the secondary coil of isolating transformer.
In such scheme, adding of terminal matching transformer is in order to extend the distance of 1553B bus to isolating transformer.In the situation that not adopting terminal matching transformer, 1553B bus to the length of cable of isolating transformer is no more than 0.3m conventionally, otherwise can cause serious signal attenuation.Add terminal matching transformer, terminal matching transformer to the length of cable of isolating transformer just can reach maximum 6m.
General 1553B communication full-duplex transceiver described in the utility model, it can receive and meets the signal of 1553B bus protocol and be converted into universal signal for user, and the universal signal that user can also be provided is converted to and meets the signal of 1553B bus protocol and send.Due to itself and user interface is universal signal, therefore its user interface is open, can provide abundant interface to use to FPGA, CPU and DSP, and then the communication issue of solution 1553B bus and other buses (as CAN bus), thereby can 1553B bus be that major trunk roads are realized naval vessel electronics synthesization, promote 1553B bus being widely used and developing of field, naval vessel and even civilian installation at home.
Similarly, the device with above-mentioned general 1553B communication full-duplex transceiver described in the utility model, it can receive from the signal of 1553B bus and be converted into universal signal for user, can also meet the signal of 1553B bus protocol and be sent to 1553B bus being converted to from user's universal signal.Owing to having adopted isolating transformer and terminal matching transformer, except thering is the beneficial effect of above-mentioned transceiver, also there is the adaptability of higher severe rugged environment.
In addition, general 1553B communication full-duplex transceiver described in the utility model and the device with this transceiver also have following advantages:
1) can be user provides 1553B bus for transmitting data, thereby solves the high problem of communication requirement of real time.
2) can be user 1553B networking solution is provided, can be used for bus control unit, remote terminal and bus monitor.
3) can be applicable in complicated and harsh environment, the performances such as wet-heat resisting, salt fog, mould, vibration and impact reach the requirement of 1553B specification completely, have real-time and reliability.
4) waveform of transmission reaches the requirement of waveform integrality, and common-mode rejection ratio is greater than 68db, and properties of product are better than existing import 1553B interface chip.
Brief description of the drawings
Fig. 1 is the structured flowchart of general 1553B communication full-duplex transceiver described in the utility model under a kind of execution mode.
Fig. 2 is the circuit diagram of the transmitter of general 1553B communication full-duplex transceiver described in the utility model under a kind of execution mode.
Fig. 3 is the circuit diagram of the receiver of general 1553B communication full-duplex transceiver described in the utility model under a kind of execution mode.
Fig. 4 is the structural representation of the device with general 1553B communication full-duplex transceiver described in the utility model under a kind of execution mode.
Fig. 5 is the structural representation of the device with general 1553B communication full-duplex transceiver described in the utility model under another kind of execution mode.
Fig. 6 is the partial detailed circuit diagram of Fig. 4.
Fig. 7 is transmitter and oscillogram corresponding to receiver of general 1553B communication full-duplex transceiver described in the utility model under a kind of execution mode.
Embodiment
The device of general 1553B of the present invention being communicated by letter full-duplex transceiver and having this transceiver below in conjunction with Figure of description and specific embodiment is further described in detail, but this explanation does not form the improper restriction for technical solution of the present invention.
Fig. 1 shows the structured flowchart of general 1553B communication full-duplex transceiver described in the utility model under a kind of execution mode.
As shown in Figure 1, the general 1553B communication full-duplex transceiver of the present embodiment comprises: transtation mission circuit and receiving circuit, and wherein, transtation mission circuit comprises transmitter and encoder, receiving circuit comprises receiver and decoder.Transmitter comprises signal amplification shaping circuit and switching gate circuit; Receiver comprises signal limiter, subtraction device, filter and comparator; Encoder comprises serializer, manchester encoder, synchronous code multiplex circuit, the first digit counter and verification maker; Decoder comprises change-over circuit, synchronous code testing circuit, deserializer circuit, second counter, verification check circuit; Between above-mentioned each circuit, device, be electrically connected by shown in Fig. 1.
In above-mentioned general 1553B communication full-duplex transceiver, transtation mission circuit can be converted to the first data the bipolarity phase modulated signal that can directly send to 1553B bus by isolating transformer, and receiving circuit can directly receive second data from 1553B bus of isolating transformer and be converted into parallel data and control signal.Specific works process is as follows:
For transtation mission circuit: user by encoder interfaces by first data transmission to the synchronous code multiplex circuit in encoder, these first data comprise the parallel data tx_dword[0:15 that user sends].In the time having parallel data transmission, start the first digit counter, under the control of the first digit counter, check value and parallel data tx_dword[0:15 that synchronous code multiplex circuit generates synchronous code, verification maker] together with form the concurrent frame structure of 1553B agreement, then through the manchester encoder processing of encoding, give stringization circuit conversion and be the first two-phase unipolarity digital signal DO0 and DO1 and the first control signal ST and export to transmitter; Switching gate circuit in transmitter receives the first two-phase unipolarity digital signal DO0 and DO1 and the first control signal ST from encoder, after processing, give signal amplification shaping circuit, signal shaping amplifier is converted to bipolarity phase modulated signal by T1 and T0 output by the first two-phase unipolarity digital signal DO0 and DO1.The signal of input coding device also comprises that sending data is effective payload data signal tx_dw, and sending data is command word or status word signal tx_csw, the clock signal enc_clk of encoder.Encoder is output coder busy signal tx_busy also, is used to indicate encoder and is in busy state, can not continue to receive next data.
For receiving circuit: the isolating transformer being connected with 1553B bus, the second data from 1553B bus are transferred to the signal limiter in receiver by R1 and R0, then pass through subtraction device and filter, give comparator by the bipolarity analog signal after phase demodulating, finally export the second two-phase unipolarity digital signal DI0 and DI1, two-phase unipolarity digital signal DI0 and DI1 are converted to NRZ code by change-over circuit in decoder, then detect frame synchronization by synchronous code testing circuit, synchronous code testing circuit connects deserializer circuit, second counter and verification check circuit, verification check circuit is mainly whether the data check of detection synchronous code testing circuit output is correct, if correctly, received, incorrect providing reported to the police and packet loss, second counter Main Function is in the time that synchronous code testing circuit detects frame synchronization, start corresponding second counter controls deserializer circuit, serial data is converted to parallel data rx_dword[0:15] output, for user.Decoder is also exported corresponding control signal simultaneously, comprises data effective index signal rx_dval, order or condition indicative signal rx_csw, effectively payload data index signal rx_dw, check errors index signal rx_perr.The clock signal dec_clk of decoder is connected with decoder.
Fig. 2 shows the circuit diagram of the transmitter of the present embodiment.
As shown in Figure 2, in the transmitter of the present embodiment, resistance R 16, R2 and triode VT1 form transmission enable circuits, when the first control signal ST is input as high level, send effectively.Resistance R 1, R3 and analog switch D1A and D1D have formed switching gate circuit, and the first two-phase two-phase unipolarity digital signal DO0 and DO1 are for conducting and the disconnection of control simulation switch D1A and D1D.Resistance R 5, capacitor C 9, diode VD1, resistance R 9, resistance R 12, resistance R 14 and triode VT2 have formed signal amplification shaping circuit, for by the first DO0 shaping of two-phase unipolarity digital signal and drive amplification of input, finally export by T1; Resistance R 6, capacitor C 10, diode VD2, resistance R 10, resistance R 13, resistance R 15 and triode VT3 have formed another road signal amplification shaping circuit, for by the first DO1 shaping of two-phase unipolarity digital signal and drive amplification of input, finally export by T0; Between output T0 and T1, form a bipolarity phase modulated signal.
Fig. 3 shows the circuit diagram of the receiver of the present embodiment.
As shown in Figure 3, in the receiver of the present embodiment, resistance R 19, resistance R 20 and diode VD3 and VD4 have formed signal limiter circuit, be mainly to prevent the second data overvoltage of R0 and R1 input and damage amplifier or cause output to cut width because input signal amplitude is excessive, thereby make a mistake.Resistance R 21, resistance R 22, resistance R 23, resistance R 24 and operational amplifier D2A form subtraction device; Resistance R 17, resistance R 18, capacitor C 11, capacitor C 15 and operational amplifier D2B have formed filter.The second data R0 of input and R1 (can be for example bipolarity phase modulated signal in the present embodiment), through signal limiter, then pass through subtraction device and filter, the bipolarity analog signal after output phase demodulation.Capacitor C 12, capacitor C 13, capacitor C 14, resistance R 4, resistance R 7, resistance R 8, resistance R 11, resistance R 25, resistance R 26 and comparator D3A and D3B have formed comparison circuit.Bipolarity analog signal after phase demodulating is given after comparison circuit, corresponding output the second two-phase unipolarity digital signal DI0 and DI1.UB is for the outside reference value of adjusting upper limit comparative voltage, and UH is for the outside reference value of adjusting lower limit comparative voltage.In the time using inner thresholding reference voltage, do not connect.
Fig. 4 tool is the structural representation of device under a kind of execution mode that has a general 1553B communication full-duplex transceiver.
As shown in Figure 4, device 200 bus configuration are connected to direct coupling system, and general 1553B communication full-duplex transceiver 100 is connected to the primary coil of isolating transformer Ti, and the secondary coil of isolating transformer Ti is by 56 Ohmic resistance R
i1and R
i2be connected to 1553B bus, the end point of 1553B bus will meet the terminating resistor R of 75 ohm
b1and R
b2.The Voltage Peak peak value of the bipolarity phase modulated signal that general 1553B communication full-duplex transceiver 100 is exported is 29V; The transformation ratio of isolating transformer Ti is 1.11:1, and the secondary coil output voltage peak-to-peak value of isolating transformer Ti is 6.8V, and the length of cable that isolating transformer Ti is connected to bus can not exceed 0.3m, otherwise can cause serious signal attenuation.
Fig. 5 is the structural representation of device under another kind of execution mode with general 1553B communication full-duplex transceiver.
As shown in Figure 5, install 300 bus configuration and be connected to transformer coupled mode, general 1553B communication full-duplex transceiver 100 is connected to the primary coil of isolating transformer Ti, the secondary coil of isolating transformer Ti is directly connected to the primary coil of terminal matching transformer Tt by cable, the secondary coil of terminal matching transformer Tt is by 56 Ohmic resistance R
t1and R
t2be connected to 1553 buses, the end point of 1553 buses will meet the terminating resistor R of 75 ohm
b1and R
b2.The Voltage Peak peak value of the bipolarity phase modulated signal that general 1553B communication full-duplex transceiver 100 is exported is 29V; The transformation ratio of isolating transformer is 1.56:1, and the secondary output voltage peak-to-peak value of isolating transformer Ti is 19V; The transformation ratio of terminal matching transformer Tt is 1:1.41, and the secondary output voltage peak-to-peak value of terminal matching transformer Tt is 6.8V.Adopt transformer coupledly, isolating transformer Ti can not exceed 6m to the length of cable between terminal matching transformer Tt, otherwise can cause serious signal attenuation.
Fig. 6 is the partial detailed circuit diagram of Fig. 4.
As shown in Figure 6, general 1553B communication full-duplex transceiver 100, uses epoxy resin as Embedding Material, because epoxy resin temperature resistant range is wider, can avoid the internal stress under high/low temperature condition to damage circuit and solder joint, and ensureing self can craze and transfiguration.General 1553B communication full-duplex transceiver 100 has 60 external pins, uses talmi gold pin to use as drawing pin.Please refer to Fig. 2 and Fig. 3, the K1 of general 1553B communication full-duplex transceiver 100 is connected 4.7～47pF capacitor C with K2 pin
k1and C
k2, be impedance matching for the balance input of isolating transformer Ti; The output T1 of general 1553B communication full-duplex transceiver 100 is connected isolating diode D with T0 pin
t1and D
t0be connected with the primary coil of isolating transformer Ti afterwards, isolating transformer Ti centre tap ground connection.In the time that general 1553B communication full-duplex transceiver 100 has data output transmission, data are through isolating diode D
t1and D
t0, output to the primary coil of isolating transformer Ti, output to the secondary coil of isolating transformer Ti through overcoupling, then pass through resistance R
i1and R
i2data export in 1553B bus.Use isolating diode D
t1and D
t0object be to prevent that data in 1553B bus from returning string to output interface, play output isolation object.The input R1 of general 1553B communication full-duplex transceiver 100 and R0 pin are directly connected to the primary coil of isolating transformer Ti, isolating transformer Ti centre tap ground connection.In the time having data input in 1553B bus, data are through resistance R
i1and R
i2, be input to the secondary coil of isolating transformer, be input to the primary coil of isolating transformer Ti through overcoupling, be then input to input R1 and the R0 pin of general 1553B communication full-duplex transceiver 100.Pin+12V ,-12V ,+5V and GND are used for being connected power supply.
Fig. 7 is transmitter and oscillogram corresponding to receiver of general 1553B communication full-duplex transceiver described in the utility model under a kind of execution mode.
As shown in Figure 7, DO0 and DO1 are the first two-phase unipolarity digital signal, and DI0 and DI1 are the second two-phase unipolarity digital signal, and input signal R0 and R1 and output signal T0 and T1 are the bipolarity phase modulated signal that holding wire differential pressure forms.T1 and t2 are idle period.
It should be noted that above enumerate only for specific embodiment of the utility model, obviously the utility model is not limited to above embodiment, has many similar variations thereupon.If all distortion that those skilled in the art directly derives or associates from the disclosed content of the utility model, all should belong to protection range of the present utility model.
Claims (10)
1. a general 1553B communication full-duplex transceiver, is characterized in that, comprising:
Transtation mission circuit, described transtation mission circuit comprises encoder and the transmitter being connected with encoder; Wherein said encoder has data receiver and output, and encoder receives to transmit into the first data of its data receiver and from its output exports the first two-phase unipolarity digital signal and the first control signal; Described transmitter has input and data output end, and the first two-phase unipolarity digital signal of the input received code device transmission of transmitter and the first control signal are also exported bipolarity phase modulated signal from data output end;
Receiving circuit, described receiving circuit comprises receiver and the decoder being connected with receiver; Wherein receiver has data receiver and output, and receiver receives to transmit into the second data of its data receiver and from output exports the second two-phase unipolarity digital signal; Described decoder has input and data output end, and the input of decoder receives the second two-phase unipolarity digital signal of receiver transmission, and from its data output end output parallel data and control signal.
2. general 1553B communication full-duplex transceiver as claimed in claim 1, it is characterized in that: described encoder comprises the synchronous code multiplex circuit, manchester encoder and the serializer that connect successively along the transmission direction of data, described serializer is exported described the first two-phase unipolarity digital signal and the first control signal.
3. general 1553B communication full-duplex transceiver as claimed in claim 2, is characterized in that: described encoder also comprises the first digit counter and verification maker, and described the first digit counter is connected with synchronous code multiplex circuit respectively with verification maker.
4. general 1553B communication full-duplex transceiver as claimed in claim 1, it is characterized in that: described transmitter comprises the switching gate circuit and the signal amplification shaping circuit that connect successively along the transmission direction of data, described signal amplification shaping circuit is exported described bipolarity phase modulated signal.
5. general 1553B communication full-duplex transceiver as claimed in claim 1, it is characterized in that: described receiver comprises the signal limiter, subtraction device, filter and the comparison circuit that connect successively along the transmission direction of data, described comparison circuit is exported described the second two-phase unipolarity digital signal.
6. general 1553B communication full-duplex transceiver as claimed in claim 1, it is characterized in that: described decoder comprises the change-over circuit, synchronous code testing circuit and the deserializer circuit that connect successively along the transmission direction of data, and second counter, described second counter is connected with synchronous code testing circuit and deserializer circuit respectively, and described second counter triggers to control deserializer circuit by synchronous code testing circuit.
7. general 1553B communication full-duplex transceiver as claimed in claim 6, it is characterized in that: described decoder also comprises verification testing circuit, described verification check circuit is connected with synchronous code testing circuit, so that the data of synchronous code testing circuit output are carried out to verification.
8. a device with the general 1553B communication full-duplex transceiver as described in any one in claim 1-7, is characterized in that, comprising:
Described general 1553B communication full-duplex transceiver;
Isolating transformer, the primary coil of described isolating transformer is connected respectively with the data output end of the data receiver of receiver and transmitter.
9. device as claimed in claim 8, is characterized in that, described device also comprises: terminal matching transformer, the primary coil of described terminal matching transformer is connected with the secondary coil of isolating transformer.
10. device as claimed in claim 9, is characterized in that, the length of cable being connected between described isolating transformer and terminal matching transformer is no more than 6m.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104346315A (en) * | 2014-11-15 | 2015-02-11 | 中国航天科工集团第三研究院第八三五七研究所 | Device for relaying and switching branch of 1553 bus |
| CN109542818A (en) * | 2018-11-16 | 2019-03-29 | 陕西千山航空电子有限责任公司 | A kind of general 1553B interface arrangement |
| CN109639663A (en) * | 2018-12-07 | 2019-04-16 | 天津津航计算技术研究所 | A kind of method for converting protocol of 1553 bus and CANFD bus |
| CN109698827A (en) * | 2018-12-07 | 2019-04-30 | 天津津航计算技术研究所 | A kind of protocol conversion apparatus of 1553 bus and CANFD bus |
-
2014
- 2014-05-23 CN CN201420265691.3U patent/CN203840365U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104346315A (en) * | 2014-11-15 | 2015-02-11 | 中国航天科工集团第三研究院第八三五七研究所 | Device for relaying and switching branch of 1553 bus |
| CN109542818A (en) * | 2018-11-16 | 2019-03-29 | 陕西千山航空电子有限责任公司 | A kind of general 1553B interface arrangement |
| CN109639663A (en) * | 2018-12-07 | 2019-04-16 | 天津津航计算技术研究所 | A kind of method for converting protocol of 1553 bus and CANFD bus |
| CN109698827A (en) * | 2018-12-07 | 2019-04-30 | 天津津航计算技术研究所 | A kind of protocol conversion apparatus of 1553 bus and CANFD bus |
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