CN204948179U - The circuit of a kind of use three line differential video link transmission BIT information - Google Patents

Abstract

The utility model discloses a kind of circuit using differential amplifier common-mode signal transmission information, particularly does one use three-wire system differential video link transmission BIT(Built? In? Test) circuit of information, belongs to electronic equipment built in test BIT field.This circuit comprises transtation mission circuit and receiving circuit, BIT information after level adjustment, input coding circuit, produce numerical value be zero clean interchange common-mode voltage, this common-mode voltage enters differential amplifier common mode input with video signal transmission; Receiving circuit is made up of terminal resistance network and hysteresis comparator circuit, and common-mode voltage recovers BIT information through hysteresis comparator decoding.The utility model uses unique common mode electrical level encoding scheme, well decreases the common mode electromagnetic radiation from cable; Rely on balanced transmission techniques, BIT information can with video long-distance transmissions; Circuit realiration is simple, flexibly, interconnected cost between reduction system/device, plays a role in promoting to system/device high integration, ting model.

Description

The circuit of a kind of use three line differential video link transmission BIT information

Technical field

The utility model relates to electronic equipment built in test BIT(BuiltInTest) field, the particularly circuit of a kind of use three line differential video link transmission BIT information.

Background technology

Modern electronic equipment becomes increasingly complex, large scale electronic equipment integrated level particularly numerous is more and more higher, once equipment breaks down, failure detection time is elongated, maintenance load will increase sharply, and therefore their safe and reliable operation and rapid-maintenance just seem very important.Along with the application and development of computer technology, a kind of technology BIT(BuiltInTest relying on the circuit of electronics self and program to complete failure diagnosis, Fault Isolation) be widely applied.It automatically can detect, diagnose and isolate the fault of equipment/internal system, greatly improves the failure diagnosis efficiency in electronics and accuracy, thus reduces maintenance cost, improve the availability of electronics.

BIT information transmission is various on realization means, can rely on existing multiple interfaces technology.The application of three line differential video links comes from and uses UTP(UnshieldedTwistedPaired: unshielded twisted pair) needs of transportation simulator vision signal, to simplify transmission of video approach (replacement coaxial cable), extend transmission distance, strengthen antijamming capability.Three-wire system differential video widely uses in fields such as Industry Control, vehicle-mounted, Aeronautics and Astronautics.Special circuit/interface transmission BIT information is used relative to tradition, designer proposes the circuit of the common mode technical transmission BIT information in use three line differential video, this circuit realiration is simple, flexible, interconnect between reduction system/device cost, plays a role in promoting to system/device high integration, miniaturization.

Summary of the invention

Problem to be solved in the utility model is: for existing BIT information transmission technology present situation, proposes a kind of circuit using the common-mode signal transmission BIT information of three-wire system differential video link.

For realizing above-mentioned technical problem, the solution that the utility model proposes is: the circuit of a kind of use three line differential video link transmission BIT information, is characterized in that: it comprises information transtation mission circuit and receiving circuit two parts.

Transtation mission circuit comprises three on all four differential amplifier U ₁, U ₂and U ₃, R _iN±, G (SOG) _iN±, B _iN± be respectively red, green, blue three-primary colors difference vision signal, wherein SOG represents that synchronizing signal is compound in green.At three positive differential input signal R _iN+, G (SOG) _iN+, B _iN+ with three differential amplifiers be connected in series gain setting resistor R respectively between input in the same way _g, at three negative differential input signal R _iN-, G (SOG) _iN-, B _iN-and the reverse input end of three differential amplifiers between be connected in series gain setting resistor R respectively _g, be connected in series feedback resistance R between input with negative output terminal in the same way at three differential amplifiers _f, three differential amplifiers reverse input end be connected in series feedback resistance R between positive output end _f.

BIT _data, BIT _clkbe BIT data and clock signal respectively, BIT _databe connected to controllable gain amplifier U ₄input, BIT _clkbe connected to controllable gain amplifier U ₅input, level terminal provides Voltage Reference by outside, is connected to controllable gain amplifier U ₄, U ₅gain control end, controllable gain amplifier U ₄, U ₅output be respectively data and clk; Clk is through inverter U ₆access adder U ₇input, data accesses adder U ₇another input, adder U ₇output access differential amplifier U ₁common mode input; Data is through fixed gain amplifier (2 times) U ₈output to inverter U ₉input, reverser U ₉differential amplifier U is received in output ₂common mode input; Data and clk accesses adder U respectively ₁₀two inputs, adder U ₁₀differential amplifier U is received in output ₃common mode input.

Receiving circuit comprises two hysteresis comparator U ₁₁and U ₁₂, the three pairs of differential signals at receiving terminal respectively and meet terminal resistance R _d, at the R of each terminal resistance _dsignal is drawn at/2 places, and these signals are the common-mode signal R of three differential lane transmission _cm, G _cm, B _cm, R _cmaccess hysteresis comparator U ₁₁reverse input end, B _cmaccess hysteresis comparator U ₁₁input in the same way, U ₁₁output is through Series Termination resistance R _safter can obtain BIT _clk; R _cmseries resistor R ₁rear access hysteresis comparator U ₁₂input in the same way, B _cmseries resistor R ₂rear access hysteresis comparator U ₁₂(the resistance R of input in the same way ₁with R ₂resistance identical), G _cmseries resistor R ₃rear access hysteresis comparator U ₁₂reverse input end, U ₁₂two inputs respectively with ground by electric capacity C ₁, C ₂connect, hysteresis comparator U ₁₂output is through Series Termination resistance R _safter can obtain BIT _data.

A kind of circuit using three-wire system differential video link transmission BIT information that the utility model proposes, its advantage is:

1, unique common mode electrical level encoding scheme, produces the clean interchange common-mode voltage that numerical value is zero, reduces the common mode electromagnetic radiation from cable;

2, rely on balanced transmission techniques, 300 meters or farther transmission range can be realized;

3, circuit realiration is simple, flexibly, interconnected cost between reduction system/device, plays a role in promoting to system/device high integration, ting model.

Accompanying drawing explanation

Fig. 1 is the utility model transtation mission circuit structural representation;

Fig. 2 is the utility model receiving circuit structural representation;

Fig. 3 is the electrical block diagram of an exemplary embodiment of the circuit of a kind of practical three line differential video link transmission BIT information of the present utility model;

Fig. 4 is the logical relation schematic diagram of the common mode electrical level that coding circuit exports;

Fig. 5 is serial data transmission form schematic diagram.

Embodiment

Below with reference to the drawings and specific embodiments, the utility model is described in further details.

Fig. 3 graphic extension embodiment of the present utility model, be one and use unshielded twisted pair (UTP, as Category-5e, be initially designed to transmission local network LAN flow, now become the economical solution of other a lot of Signal transmissions application) system of transmission broadband vision signal and BIT information, uses 3 couple transmission red, green, blue RGB simulation primary video signal in 4 pairs of twisted-pair feeders or brightness, aberration (YP _bp _r), high definition component video signal, the horizontal and vertical lock-out pulse of RGB simulation needed for primary video signal can embed in blanking interval, also can be compound in green, namely the SOG signal that the utility model is mentioned is horizontal and vertical be synchronously compound in green.BIT signal completes coding at transmitting terminal, and realizing decoding at receiving terminal, is also transmitted as common-mode signal by these three pairs of twisted-pair feeders.

BIT _data, BIT _clkbe data-signal and the clock signal of BIT information transmission respectively, design adopts synchronous serial-data transmission mode, and under the shift pulse of main device, data step-by-step is transmitted, and be simplex, data transmission bauds is very fast.Level when clock polarity represents that clock is idle, clock phase determination data is in the sampling of clk rising edge or trailing edge sampling, according to the various combination of clock polarity and clock phase, can obtain different mode of operations.The utility model uses common synchronous serial interface data framing form, as shown in Figure 5, data frame packet is containing opening flag, data fields, check bit sum position of rest, the equipment provided according to system and fault mode, data fields characterizes the fault message of monitored subsystem, as device number, fault type, fault number etc.

The utility model comprises information transtation mission circuit and Information Receiving Circuits two parts; Transtation mission circuit comprises three on all four differential amplifier U ₁, U ₂and U ₃with corresponding gain adjusting circuit, vision signal completes single-ended/differential conversion, gain-adjusted here, BIT _data, BIT _clkthrough controllable gain amplifier U ₄, U ₅level adjustment after, give coding circuit and complete coding, the result of coding is input to differential amplifier U respectively ₁, U ₂and U ₃common mode input complete information send.

BIT Information Receiving Circuits is by three terminal resistance R _dwith two hysteresis comparator U ₁₁and U ₁₂composition, each terminal resistance R _dthe signal that/2 places draw is the common-mode signal R of three differential lane transmission _cm, G _cm, B _cm, by hysteresis comparator to the common-mode signal R received _cm, G _cm, B _cmcompare, computing, complete BIT information decoding, recover BIT _data, BIT _clk.Terminal resistance R _dsimultaneously also as the terminal resistance of video signal receiver, vision signal recovers the high-frequency content of video through receiver/equalizer, provides smooth gain simultaneously, then provides correct sequential by analogue delay.

Although use RGB to simulate an embodiment of primary video signal in this illustration shows, can be readily appreciated that, the difference video signal transmission link of other kind, the circuit that the utility model also can be used to describe is to transmit BIT signal.

Operation principle:

As BIT signal BIT _data, BIT _clkbe input to controllable gain amplifier U ₄, U ₅after carrying out level adjustment, give coding circuit and complete coding, as shown in Figure 1 circuit, coding circuit is by inverter U ₆and U ₉, adder U ₇and U ₁₀, fixed gain amplifier (2 times) U ₈composition, entered coding circuit computing, we are easy to obtain following relational expression:

R _cm=K×（BIT _data–BIT _clk）/2+V _midsupply①

G _cm=K×（-2BIT _data）/2+V _midsupply②

B _cm=K×（BIT _data+BIT _clk）/2+V _midsupply③

Wherein:

K represents intermediate power supplies voltage (V _midsupply) peak deviation of common mode pulse voltage, its value is by controllable gain amplifier U ₄, U ₅determine;

BIT _dataand BIT _clkbe unit weighted term, be+1 for logical one, for logical zero be.

This encoding scheme produces the clean interchange common-mode voltage that numerical value is zero, as shown in Figure 4, can reduce the common mode electromagnetic radiation from cable like this.The result of coding is input to differential amplifier U respectively ₁, U ₂and U ₃common mode input complete information send.

As the difference video signal incoming terminal resistance R containing common-mode signal on twisted-pair feeder _dafter, difference video signal and common-mode signal receive respectively, respectively by terminal resistance R _d1/2 tap place extract signal be three common-mode signal R that link transmits _cm, G _cm, B _cm, 1., 2., 3. can be drawn by relational expression:

BIT _data=（B _cm+R _cm）-G _cm④

BIT _clk=B _cm-R _cm⑤

The logical relation design hysteresis comparator circuit decoding BIT data 4., 5. by relational expression.

Notice and be electrical block diagram shown in Fig. 1, Fig. 2, Fig. 3, the factors such as the power supply in circuit and decoupling are not considered in the present note.Equally, the devices such as the adder mentioned in example, reverser, controllable gain amplifier, fixed gain amplifier, hysteresis comparator, differential amplifier are the general-purpose device title of electronic applications, be not refering in particular to of certain circuit, all uses are led to kind of functional circuit and are realized this novel method, all should belong to covering scope of the present utility model.

Claims (6)

1. use a circuit for three line differential video link transmission BIT information, it is characterized in that comprising information transtation mission circuit and receiving circuit two parts, transtation mission circuit comprises gain adjusting circuit, coding circuit and three on all four differential amplifier U ₁, U ₂and U ₃composition, receiving circuit is by three terminal resistance R _dwith two hysteresis comparator circuit compositions, BIT information regulates level through gain adjusting circuit, send into coding circuit, differential amplifier common mode input is sent into after coding, send with vision signal, the vision signal comprising BIT information takes out common-mode signal through terminal resistance, sends into hysteresis comparator circuit computing, recovers BIT information.

2. the circuit of a kind of use as claimed in claim 1 three line differential video link transmission BIT information, is characterized in that described gain adjusting circuit is by controllable gain amplifier U ₄, U ₅composition, BIT data input signal BIT _databe connected to controllable gain amplifier U ₄input, BIT _clkbe connected to controllable gain amplifier U ₅input, level terminal provides Voltage Reference by outside, is connected to controllable gain amplifier U ₄, U ₅gain control end.

3. the circuit of a kind of use as claimed in claim 1 three line differential video link transmission BIT information, is characterized in that described coding circuit is by inverter U ₆and U ₉, adder U ₇and U ₁₀, fixed gain amplifier U ₈composition, controllable gain amplifier U ₅output clk through inverter U ₆access adder U ₇input, controllable gain amplifier U ₄output data access adder U ₇another input, adder U ₇output access differential amplifier U ₁common mode input, data is through fixed gain amplifier U ₈output to inverter U ₉input, reverser U ₉differential amplifier U is received in output ₂common mode input, data and clk accesses adder U respectively ₁₀two inputs, adder U ₁₀differential amplifier U is received in output ₃common mode input.

4. the circuit of a kind of use as claimed in claim 1 three line differential video link transmission BIT information, is characterized in that each terminal resistance R in described receiving circuit _dthe signal that/2 places draw is the common-mode signal R of three differential lane transmission _cm, G _cm, B _cm, by hysteresis comparator to the common-mode signal R received _cm, G _cm, B _cmcompare, computing, complete BIT information decoding, recover BIT _data, BIT _clk.

5. the circuit of a kind of use as claimed in claim 1 three line differential video link transmission BIT information, is characterized in that R in described hysteresis comparator circuit _cmaccess hysteresis comparator U ₁₁reverse input end, B _cmaccess hysteresis comparator U ₁₁input in the same way, U ₁₁output is through Series Termination resistance R _safter can obtain BIT _clk, R _cmseries resistor R ₁rear access hysteresis comparator U ₁₂input in the same way, B _cmseries resistor R ₂rear access hysteresis comparator U ₁₂input in the same way, G _cmseries resistor R ₃rear access hysteresis comparator U ₁₂reverse input end, U ₁₂two inputs respectively with ground by electric capacity C ₁, C ₂connect, hysteresis comparator U ₁₂output is through Series Termination resistance R _safter can obtain BIT _data.

6. the circuit of a kind of use as claimed in claim 1 three line differential video link transmission BIT information, is characterized in that described coding circuit produces the clean interchange common-mode voltage that numerical value is zero, can reduce the common mode electromagnetic radiation from cable.