CN219697667U - FlexRay bus communication module based on FPGA - Google Patents
FlexRay bus communication module based on FPGA Download PDFInfo
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- CN219697667U CN219697667U CN202320248975.0U CN202320248975U CN219697667U CN 219697667 U CN219697667 U CN 219697667U CN 202320248975 U CN202320248975 U CN 202320248975U CN 219697667 U CN219697667 U CN 219697667U
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Abstract
The utility model discloses a FlexRay bus communication module based on an FPGA (field programmable gate array), which comprises an ESD (electro-static discharge) protection circuit arranged at an output end, wherein the ESD protection circuit comprises a common mode choke coil L9, an impedance matching network and an ESD protection diode V5 which are connected in parallel, one side of the common mode choke coil L9 is connected with a front-stage input signal of the FlexRay bus communication module, the other side of the common mode choke coil L9 is connected with the ESD protection diode V5 through the impedance matching network, and a connecting node of the impedance matching network and the ESD protection diode V5 is used as the output end of the FlexRay bus communication module; the utility model has the advantages that: the output signal is stable, and the communication effect is good.
Description
Technical Field
The utility model relates to the technical field of communication, in particular to a FlexRay bus communication module based on an FPGA.
Background
The FlexRay bus communication implementation is mainly designed by taking a bus protocol controller as a core, and the implementation modes mainly include two types, namely, the first type of implementation is realized by adopting a microprocessor MCU and a bus driver BD of the integrated FlexRay bus protocol controller, as shown in (B) in FIG. 1; the second is implemented by using a separate FlexRay bus protocol control chip, namely a communication controller CC, a bus driver BD and a microprocessor MCU, as shown in fig. 1 (a).
However, the problems of interference caused by electromagnetic radiation and reflected waves in the circuit are not considered in the two cases, and the problems of unstable output signals and influence on communication effects caused by external spike pulse influence and common-mode interference signals exist.
Disclosure of Invention
The utility model aims to solve the technical problem that the output signal of a FlexRay bus communication module in the prior art is unstable, and the communication effect is affected.
The utility model solves the technical problems by the following technical means: the utility model provides a FlexRay bus communication module based on FPGA, includes the ESD protection circuit who sets up in the output, ESD protection circuit includes parallel connection's common mode choke L9, impedance matching network and ESD protection diode V5, the preceding stage input signal of FlexRay bus communication module is connected to one side of common mode choke L9, and the opposite side of common mode choke L9 passes through impedance matching network and is connected with ESD protection diode V5, and impedance matching network and ESD protection diode V5's connected node is as FlexRay bus communication module's output.
The beneficial effects are that: the FlexRay bus communication module is provided with the ESD protection circuit, wherein the common mode choke coil L9 can inhibit common mode signals, improve bus electromagnetic compatibility and electromagnetic radiation, connect an impedance matching network in parallel, ensure impedance continuity of a receiving end and a transmission line, avoid generation of reflected waves, eliminate interference problems caused by the reflected waves, and the ESD protection diode V5 can reduce external spike pulse influence and improve anti-interference capability, so that the output signal of the whole circuit is stable, and the communication effect is good.
Further, the impedance matching network includes a resistor R36, a resistor R40, a capacitor C119, a capacitor C116, and a capacitor C120, where a first pin and a fourth pin of the common mode choke L9 receive a front-stage input signal of the FlexRay bus communication module, one end of the resistor R36, one end of the capacitor C116, and a second pin of the ESD protection diode V5 are all connected to a third pin of the common mode choke L9, the other end of the resistor R36, one end of the capacitor C119, and one end of the resistor R40 are connected, the other end of the capacitor C116, the other end of the capacitor C119, and one end of the capacitor C120 are connected, the other end of the resistor R40, the other end of the capacitor C120, and the first pin of the ESD protection diode V5 are all connected to a second pin of the common mode choke L9, and the third pin of the ESD protection diode V5 is grounded, and the second pin and the first pin of the ESD protection diode V5 are used as output ends of the FlexRay bus communication module.
Further, the ESD protection diode V5 is of the type PESD1FLEX.
Furthermore, the FlexRay bus communication module based on the FPGA further comprises an FPGA, a communication controller, an isolation circuit and a bus driver, wherein the FPGA, the communication controller, the isolation circuit, the bus driver and the ESD protection circuit are sequentially connected.
Further, the model of the communication controller is MFR4310, and an IO input port of the communication controller is connected with an IO output port of the FPGA.
Further, the isolation circuit includes a chip N11, a chip N13, and a chip N14, where a fifth pin of the chip N11 is connected to an eighth pin of the chip N13 and a first pin of the chip N14, a fifth pin of the chip N13 is connected to a fourth pin of the chip N14, a fourth pin of the chip N13 is connected to a fifth pin of the chip N14, and a first pin of the chip N13 is connected to an eighth pin of the chip N14; the thirty-third pin, the forty-first pin, the thirty-sixth pin, the forty-third pin, the forty-fifth pin and the forty-fourth pin of the communication controller are respectively connected with the sixth pin of the chip N14, the second pin of the chip N11, the third pin of the chip N11, the seventh pin of the chip N14, the second pin of the chip N13 and the third pin of the chip N13 in a one-to-one correspondence manner.
Still further, the models of the chip N11, the chip N13 and the chip N14 are ADUM3210TRZ.
Further, the bus driver has two main chips, namely a chip U6 and a chip U7, wherein the second pin of the chip U6 is connected with the seventh pin of the chip N11, the third pin of the chip U6 is connected with the sixth pin of the chip N11, the fourth pin of the chip U6 is connected with the third pin of the chip N14, the second pin of the chip U7 is connected with the seventh pin of the chip N13, the third pin of the chip U7 is connected with the sixth pin of the chip N13, the fourth pin of the chip U7 is connected with the second pin of the chip N14, the twelfth pin and the thirteenth pin of the chip U6 are respectively connected with the fourth pin and the first pin of the common mode choke L9, and the twelfth pin and the thirteenth pin of the chip U7 are respectively connected with the fourth pin and the first pin of the common mode choke L10 of the other group of ESD protection circuits.
Further, the models of the chip U6 and the chip U7 are U-TJA1083.
Further, the common mode choke L9 and the common mode choke L10 are both of the type DLW31SN222SQ2.
The utility model has the advantages that:
(1) The FlexRay bus communication module is provided with the ESD protection circuit, wherein the common mode choke coil L9 can inhibit common mode signals, improve bus electromagnetic compatibility and electromagnetic radiation, connect an impedance matching network in parallel, ensure impedance continuity of a receiving end and a transmission line, avoid generation of reflected waves, eliminate interference problems caused by the reflected waves, and the ESD protection diode V5 can reduce external spike pulse influence and improve anti-interference capability, so that the output signal of the whole circuit is stable, and the communication effect is good.
(2) The FlexRay bus communication module is designed based on the FPGA, has more IO output ports, and can be connected with a plurality of groups of communication controllers and subsequent circuits, so that the expansion design of a FlexRay bus communication interface is realized, and the application requirements of different occasions are met.
(3) The utility model is provided with the isolation circuit, realizes the isolation function with an external interface, reduces external electromagnetic interference and improves the working stability of the system.
Drawings
FIG. 1 is a schematic diagram of a prior art FlexRay bus communication implementation;
fig. 2 is a block diagram of the overall structure of a FlexRay bus communication module based on FPGA according to an embodiment of the present utility model;
fig. 3 is a schematic diagram of a communication controller in a FlexRay bus communication module based on FPGA according to an embodiment of the present utility model;
fig. 4 is a schematic diagram of an isolation circuit in a FlexRay bus communication module based on an FPGA according to an embodiment of the present utility model;
fig. 5 is a schematic diagram of a bus driver and an ESD protection circuit in a FlexRay bus communication module based on an FPGA according to an embodiment of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions in the embodiments of the present utility model will be clearly and completely described in the following in conjunction with the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
As shown in fig. 2, an FPGA-based FlexRay bus communication module includes an FPGA, a communication controller, an isolation circuit, a bus driver, and an ESD protection circuit, where the FPGA, the communication controller, the isolation circuit, the bus driver, and the ESD protection circuit are sequentially connected. In fig. 2, MFR4310 is a FlexRay bus communication controller, and implements a FlexRay communication specification protocol; ISO is an isolation circuit, realizing bus isolation design; TJA1083 is a FlexRay bus driver, which completes the conversion of the bus electrical specification; the ESD is an ESD protection circuit of the FlexRay bus interface; the programmable logic device FPGA is a ZYNQ 7 series device of Xilinx company; and PCIe and Ethernet interfaces based on FPGA are designed to realize user application interfaces.
As shown in fig. 3, the model of the communication controller is MFR4310, and the IO input port of the communication controller is connected with the IO output port of the FPGA. The communication controller is in interconnection communication with the FPGA through a LocalBus bus mode, the FPGA completes the functions of configuration parameter configuration, driving execution, data receiving and transmitting and the like through the LocalBus bus and the communication controller MFR4310, and a specific circuit is shown in FIG. 3. The LocalBus interface mainly comprises: 12-bit address bus fpga_fr1_a [1:12], 16-bit data bus fpga_fr1_d [0:15], control signal fpga_fr1_reset_ N, FPGA _fr1_we_ N, FPGA _fr1_oe_ N, FPGA _ce_ N, FPGA _fr1_int_n; according to the technical manual of MFR4310, this LocalBus interface is its AMI (Asynchronous Memory Interface) interface.
As shown in fig. 4, the part utilizes a digital isolation device to realize the isolation function with an external interface, so that the external electromagnetic interference is reduced, and the working stability of the system is improved; the FlexRay bus carries out data transmission through two channels AB, the highest speed can reach 10Mbps, so that an isolation device meeting the communication speed requirement is selected, and an ADUM3210 digital isolation device of TI company is selected for isolation, wherein the isolation circuit comprises a chip N11, a chip N13 and a chip N14, a fifth pin of the chip N11 is connected with an eighth pin of the chip N13 and a first pin of the chip N14, a fifth pin of the chip N13 is connected with a fourth pin of the chip N14, a fourth pin of the chip N13 is connected with a fifth pin of the chip N14, and the first pin of the chip N13 is connected with an eighth pin of the chip N14; the thirty-third pin, the forty-first pin, the thirty-sixth pin, the forty-third pin, the forty-fifth pin and the forty-fourth pin of the communication controller are respectively connected with the sixth pin of the chip N14, the second pin of the chip N11, the third pin of the chip N11, the seventh pin of the chip N14, the second pin of the chip N13 and the third pin of the chip N13 in a one-to-one correspondence manner. The models of the chip N11, the chip N13 and the chip N14 are ADUM3210TRZ. And (3) carrying out isolation design on the data interfaces TXD and RXD of the AB two channels of the FlexRay controller MFR4310, and butting the TXD and RXD isolated by the isolation device with a bus driver of a later stage.
As shown in fig. 5, the bus driver provides a function of transmitting and receiving data by differential signals for the bus, is responsible for bidirectional time division multiplexing binary data stream transmission, adopts a TJA1083 device of NXP company, supports a maximum transmission rate of 10Mbps, has functions of bus monitoring and real-time diagnosis, and is uploaded to the FPGA through the SPI interface. Specifically, the bus driver has two main chips, namely a chip U6 and a chip U7 (corresponding to the part (1) in fig. 5), the second pin of the chip U6 is connected with the seventh pin of the chip N11, the third pin of the chip U6 is connected with the sixth pin of the chip N11, the fourth pin of the chip U6 is connected with the third pin of the chip N14, the second pin of the chip U7 is connected with the seventh pin of the chip N13, the third pin of the chip U7 is connected with the sixth pin of the chip N13, the fourth pin of the chip U7 is connected with the second pin of the chip N14, the twelfth pin and the thirteenth pin of the chip U6 are respectively connected with the fourth pin and the first pin of the common mode choke L9, and the twelfth pin and the thirteenth pin of the chip U7 are respectively connected with the fourth pin and the first pin of the common mode choke L10 of the other group of ESD protection circuits. The models of the chip U6 and the chip U7 are U-TJA1083. The common mode choke coil L9 and the common mode choke coil L10 are respectively of a model DLW31SN222SQ2.
The chip U6 and the chip U7 are used for receiving and sending binary data to the FlexRay bus communication controller MFR4310 through TXD and RXD physical interfaces; when data is transmitted, the FlexRay bus communication controller MFR4310 enables the TXEN pin of the TJA1083, and the TJA1083 receives a binary data stream at the moment and converts the binary data stream into a differential signal to be transmitted to the BM and BP buses; upon receiving the data, the TJA1083 acquires differential data from the BM, BP bus and converts it into a binary data stream, which is transmitted to the FlexRay bus communication controller MFR4310 through the RXD physical pin.
With continued reference to fig. 5, the ESD protection circuit includes a common mode choke L9, an impedance matching network, and an ESD protection diode V5 connected in parallel, where one side of the common mode choke L9 is connected to a front-stage input signal of the FlexRay bus communication module, and the other side of the common mode choke L9 is connected to the ESD protection diode V5 through the impedance matching network, and a connection node between the impedance matching network and the ESD protection diode V5 is used as an output end of the FlexRay bus communication module.
The impedance matching network comprises a resistor R36, a resistor R40, a capacitor C119, a capacitor C116 and a capacitor C120, wherein a first pin and a fourth pin of the common mode choke coil L9 are used for receiving a front-stage input signal of the FlexRay bus communication module, one end of the resistor R36, one end of the capacitor C116 and a second pin of the ESD protection diode V5 are all connected with a third pin of the common mode choke coil L9, the other end of the resistor R36, one end of the capacitor C119 and one end of the resistor R40 are connected, the other end of the capacitor C116, the other end of the capacitor C119 and one end of the capacitor C120 are connected, the other end of the resistor R40, the other end of the capacitor C120 and the first pin of the ESD protection diode V5 are all connected with the second pin of the common mode choke coil L9, the third pin of the ESD protection diode V5 is grounded, and the second pin and the first pin of the ESD protection diode V5 serve as output ends of the FlexRay bus communication module. The ESD protection diode V5 is of the type PESD1FLEX.
The common mode choke L9 and the common mode choke L10 are bus common mode chokes (corresponding to (2) in fig. 5), and function to improve bus electromagnetic compatibility and electromagnetic radiation, and suppress common mode signals, so that current driving capability of differential signals on the bus is the same and phases are opposite. The impedance matching network (corresponding to part (3) in fig. 5) is used for solving the problems of signal reflection, interference and the like in the process of transmitting signals by the bus; the parallel impedance matching network can ensure the impedance continuity of the receiving end and the transmission line, avoid the generation of reflected waves and eliminate the interference problem caused by the reflected waves. The terminal resistances of the resistors R36, R40, R45 and R55 are selected and designed according to the following formula: r is R DCLoad ＝[∑ m (R Tm ) -1 ] -1 . Wherein R is DCLoad For the direct current load on the bus, according to the requirements of the FlexRay bus standard protocol, the load is between 40 and 55 omega and mainly depends on the terminal resistance, if R is taken DCLoad For an intermediate value of 47 omega, a 94 omega termination resistor should be used for matching, for EMC performance a separate termination resistor is used, thus two 47 omega resistors are used for termination, while the common point of the two resistors is connected in series with a 4.7nF capacitor to provide a path for the common mode signal.
The ESD protection diode V5 (corresponding to part (4) in fig. 5) adopts a design of a special ESD protection diode device for a FlexRay bus of NXP, which can support a transmission rate of 10Mbps at maximum, and the design of ESD protection device can reduce the influence of external spike pulses and improve the anti-interference capability.
Through the technical scheme, the FlexRay bus communication module is provided with the ESD protection circuit, the common mode choke coil L9 can inhibit common mode signals, improve bus electromagnetic compatibility and electromagnetic radiation, connect an impedance matching network in parallel, ensure impedance continuity of a receiving end and a transmission line, avoid generation of reflected waves, eliminate interference problems caused by the reflected waves, and the ESD protection diode V5 can reduce external spike pulse influence and improve anti-interference capability, so that the whole circuit has stable output signals and good communication effect.
The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.
Claims (10)
1. The utility model provides a FlexRay bus communication module based on FPGA, its characterized in that includes the ESD protection circuit who sets up in the output, ESD protection circuit includes parallel connection's common mode choke L9, impedance matching network and ESD protection diode V5, the preceding stage input signal of FlexRay bus communication module is connected to one side of common mode choke L9, and the opposite side of common mode choke L9 passes through impedance matching network and is connected with ESD protection diode V5, and impedance matching network and ESD protection diode V5's connected node is as FlexRay bus communication module's output.
2. The FlexRay bus communication module according to claim 1, wherein the impedance matching network comprises a resistor R36, a resistor R40, a capacitor C119, a capacitor C116 and a capacitor C120, the first pin and the fourth pin of the common mode choke L9 receive the front-stage input signal of the FlexRay bus communication module, one end of the resistor R36, one end of the capacitor C116, the second pin of the ESD protection diode V5 are all connected to the third pin of the common mode choke L9, the other end of the resistor R36, one end of the capacitor C119 and one end of the resistor R40 are connected, the other end of the capacitor C116, the other end of the capacitor C119 and one end of the capacitor C120 are connected, the other end of the resistor R40, the other end of the capacitor C120 and the first pin of the ESD protection diode V5 are all connected to the second pin of the common mode choke L9, the third pin of the ESD protection diode V5 is grounded, and the second pin and the first pin of the ESD protection diode V5 are used as the output end of the FlexRay bus communication module.
3. An FPGA based FlexRay bus communication module according to claim 2, wherein the ESD protection diode V5 is of the type PESD1FLEX.
4. The FPGA-based FlexRay bus communication module of claim 2 further comprising an FPGA, a communication controller, an isolation circuit, and a bus driver, wherein the FPGA, the communication controller, the isolation circuit, the bus driver, and the ESD protection circuit are sequentially connected.
5. The FPGA-based FlexRay bus communication module according to claim 4, wherein the communication controller is MFR4310, and the IO input port of the communication controller is connected to the IO output port of the FPGA.
6. The FPGA-based FlexRay bus communication module of claim 5 wherein the isolation circuit comprises a chip N11, a chip N13 and a chip N14, wherein the fifth pin of the chip N11 is connected to the eighth pin of the chip N13 and the first pin of the chip N14, the fifth pin of the chip N13 is connected to the fourth pin of the chip N14, the fourth pin of the chip N13 is connected to the fifth pin of the chip N14, and the first pin of the chip N13 is connected to the eighth pin of the chip N14; the thirty-third pin, the forty-first pin, the thirty-sixth pin, the forty-third pin, the forty-fifth pin and the forty-fourth pin of the communication controller are respectively connected with the sixth pin of the chip N14, the second pin of the chip N11, the third pin of the chip N11, the seventh pin of the chip N14, the second pin of the chip N13 and the third pin of the chip N13 in a one-to-one correspondence manner.
7. The FPGA-based FlexRay bus communication module of claim 6 wherein the chips N11, N13 and N14 are all ADUM3210TRZ.
8. The FPGA-based FlexRay bus communication module of claim 7 wherein the bus driver has two main chips, namely a chip U6 and a chip U7, respectively, the second pin of the chip U6 is connected to the seventh pin of the chip N11, the third pin of the chip U6 is connected to the sixth pin of the chip N11, the fourth pin of the chip U6 is connected to the third pin of the chip N14, the second pin of the chip U7 is connected to the seventh pin of the chip N13, the third pin of the chip U7 is connected to the sixth pin of the chip N13, the fourth pin of the chip U7 is connected to the second pin of the chip N14, the twelfth pin and the thirteenth pin of the chip U6 are respectively connected to the fourth pin and the first pin of the common mode choke L9, and the twelfth pin and the thirteenth pin of the chip U7 are respectively connected to the fourth pin and the first pin of the common mode choke L10 of the other set of ESD protection circuits.
9. The FPGA-based FlexRay bus communication module of claim 8 wherein the die U6 and die U7 are each of the type U-TJA1083.
10. The FPGA-based FlexRay bus communication module of claim 8 wherein the common mode choke L9 and the common mode choke L10 are both model DLW31SN222SQ2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320248975.0U CN219697667U (en) | 2023-02-08 | 2023-02-08 | FlexRay bus communication module based on FPGA |
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| CN202320248975.0U CN219697667U (en) | 2023-02-08 | 2023-02-08 | FlexRay bus communication module based on FPGA |
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