CN203786260U

CN203786260U - Mainboard testing element and mainboard testing system

Info

Publication number: CN203786260U
Application number: CN201320879277.7U
Authority: CN
Inventors: 黄美红; 李鹏
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2013-12-27
Filing date: 2013-12-27
Publication date: 2014-08-20
Anticipated expiration: 2023-12-27

Abstract

The utility model provides a mainboard testing element and a mainboard testing system. The mainboard testing element comprises a first substrate, a first electric connector and a test chip. The first electric connector and the test chip are arranged on the first substrate. The first electric connector is electrically connected with the test chip. The test chip is used for storing application program codes of a test mainboard. The first electric connector is used for being electrically connected with a second electric connector of the mainboard, so that a CPU of the mainboard is enabled to utilize the test chip of the mainboard test element through the second electric connector to test the mainboard. Thus, operational processes of removing and burning application program codes on the mainboard are omitted, and the test efficiency of the mainboard is improved.

Description

Mainboard test element and mainboard test system

Technical Field

The utility model relates to an integrated circuit technical field especially relates to a mainboard test element and mainboard test system.

Background

In the development of a computer motherboard, for example, in the development process of a processor platform computer motherboard, stability and reliability tests need to be performed on the motherboard. However, if the stability and reliability of the motherboard need to be tested by other application programs, the codes of the application programs stored in the memory chip of the motherboard are erased, the codes of the new application programs are burned into the memory chip of the motherboard, and then the motherboard tests the stability and reliability of the motherboard by running the new application program codes stored in the memory chip, which results in low efficiency of testing the motherboard.

SUMMERY OF THE UTILITY MODEL

The utility model provides a mainboard test element and mainboard test system for improve the efficiency of software testing of mainboard.

In one aspect, the utility model provides a mainboard test element, include:

the test device comprises a first substrate, a first electric connector and a test chip, wherein the first electric connector and the test chip are arranged on the first substrate, and the first electric connector is electrically connected with the test chip; wherein,

the test chip is used for storing an application program code of the test mainboard;

the first electric connector is used for being electrically connected with a second electric connector of a mainboard, so that a Central Processing Unit (CPU) of the mainboard can call the test chip in the mainboard test element to test the mainboard through the second electric connector.

The motherboard test element as described above, the first electrical connector comprising two rows of pins, each row of pins comprising N pins, the N being an integer greater than or equal to 4;

the test chip is provided with a Serial Peripheral Interface (SPI) interface; 4 pins in the first electric connector are respectively connected with an enabling signal line, a data output line, a data input line and a clock signal line of an SPI interface of the test chip.

As above, in the motherboard testing component, one pin of the first electrical connector is connected to the power supply line of the testing chip, so that the motherboard supplies power to the testing chip, and the pin of the power supply line of the testing chip is different from the pins of the 4 SPI interfaces of the testing chip.

In a second aspect, the utility model provides a mainboard test system, include: the mainboard test element is provided with a first substrate, a first electric connector and a test chip, wherein the first electric connector and the test chip are arranged on the first substrate, the first electric connector is electrically connected with the test chip, and the test chip is used for storing an application program code of the test mainboard;

the mainboard is provided with a second electric connector, the second electric connector is arranged on the mainboard, and the second electric connector is electrically connected with the CPU of the mainboard;

the first electrical connector and the second electrical connector are electrically connected with each other, so that a CPU of the mainboard can call the test chip in the mainboard test element to test the mainboard.

As with the motherboard testing system described above, the first electrical connector directly engages the second electrical connector.

The mainboard test system further comprises a connecting piece, and two sides of the connecting piece are respectively and electrically connected with the first electric connector and the second electric connector.

According to the mainboard test system, the first electrical connector comprises two rows of pins, the second electrical connector comprises two rows of pins, each row of pins comprises N pins, two sides of the connecting piece respectively comprise two rows of pin holes, each row of pin holes comprises N pin holes, and N is an integer greater than or equal to 4;

the test chip is provided with a Serial Peripheral Interface (SPI) interface; 4 pins in the first electric connector are respectively connected with an enabling signal line, a data output line, a data input line and a clock signal line of an SPI interface of the test chip;

the CPU is provided with an SPI interface; and 4 pins in the second electric connector are respectively connected with an enabling signal line, a data output line, a data input line and a clock signal line of the SPI interface of the CPU.

In the above motherboard testing system, the positions of the 4 pins connected to the SPI interface of the test chip in the first electrical connector are the same as the positions of the 4 pins connected to the SPI interface of the CPU in the second electrical connector.

As above mainboard test system, a stitch of first electric connector with the power supply line of test chip is connected, a stitch in the second electric connector with the power electric connection of mainboard, so that the mainboard is right the test chip supplies power, connect the stitch of the power supply line of test chip is different from connect 4 stitches of the SPI interface of test chip, electric connection the stitch of the power of mainboard is different from connect 4 stitches of the SPI interface of CPU.

In the motherboard testing system, the memory chip of the motherboard has an SPI interface; a pin hole in the second electric connector is connected with an enabling signal line of an SPI interface of a storage chip of the mainboard, and pins of the enabling signal line of the SPI interface electrically connected with the storage chip are different from 4 pins connected with the SPI interface of the CPU;

a data output line, a data input line and a clock signal line of an SPI (serial peripheral interface) interface of the storage chip of the mainboard are respectively connected with a data output line, a data input line and a clock signal line of the SPI interface of the CPU;

the pin of the enabling signal line of the SPI interface of the storage chip is connected with the pin of the enabling signal line of the SPI interface of the CPU through the tripping device to realize short circuit of the second electric connector.

The utility model provides a mainboard test element and mainboard test system, the second electric connector's of first electric connector and mainboard through mainboard test element looks electric connection, thereby make the CPU of mainboard can call the test chip among the mainboard test element and test the mainboard, therefore the mainboard can realize carrying out the purpose of testing to the mainboard according to different application program codes through changing different mainboard test elements, also can realize a test chip through changing different mainboards and carry out the purpose of testing to a plurality of mainboards, thereby the operation process that the mainboard removed and burns the application program code has been saved, the efficiency of software testing of mainboard is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a first embodiment of a motherboard testing device according to the present invention;

fig. 2 is a schematic structural diagram of a first embodiment of the motherboard testing system of the present invention;

FIG. 3 is a circuit diagram of the motherboard testing device of FIG. 2;

FIG. 4 is a circuit diagram of the motherboard shown in FIG. 2;

fig. 5 is a schematic diagram of a tripping device provided by the present invention.

Description of reference numerals:

10: a motherboard test element;

11: a first substrate;

12; a first electrical connector;

13: testing the chip;

20: a main board;

21: a second electrical connector;

22：CPU；

23: a power source;

24: a memory chip;

30: a connecting member;

40: a jump and cold device.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a first embodiment of a novel motherboard testing device in this embodiment, and as shown in fig. 1, a motherboard testing device 10 is provided in this embodiment. The motherboard testing device 10 in this embodiment has a first substrate 11, a first electrical connector 12 and a testing chip 13, and the first electrical connector 12 and the testing chip 13 are disposed on the first substrate 11. The first substrate 11 is used to carry other objects (such as the first electrical connector 12 and the test chip 13) and provide a current transmission medium between the objects, so that the first substrate 11 can be a Printed Circuit Board (PCB) or a metal Circuit Board (PCB) or other devices with similar functions.

The first electrical connector 12 in this embodiment is disposed on the first substrate 11 and electrically connected to the test chip 13, and is used for electrically connecting with a second electrical connector of the motherboard, for example, plugging with the second electrical connector of the motherboard to realize electrical connection, so that the motherboard testing component 10 is electrically connected with the motherboard, and the motherboard testing component 10 can perform information transmission. Alternatively, the first electrical connector 12 may be located at an edge of the first substrate 11 to facilitate plugging with a second electrical connector of a motherboard.

The test chip 13 in this embodiment is used to store an application program code for testing the motherboard, and can provide the motherboard with the application program code for testing the motherboard. For example, the test chip 13 may be a Serial Peripheral Interface (SPI) type chip, and the test chip 13 may be a memory chip in the prior art, and the description of the test chip 13 in this embodiment is not repeated herein.

In this embodiment, the first electrical connector 12 of the motherboard testing component 10 is electrically connected to the second electrical connector of the motherboard, so that the CPU of the motherboard can call the testing chip 13 in the motherboard testing component 10 to test the motherboard through the second electrical connector, and therefore the motherboard can test the motherboard according to different application codes by replacing different motherboard testing components 10, and also can test a plurality of motherboards by replacing one testing chip 13 through replacing different motherboards, thereby saving the operating process of erasing and burning the application codes of the motherboard, and improving the testing efficiency of the motherboard.

Other specific implementations of how the motherboard testing component 10 can test the motherboard can be seen in the following description of the present invention.

Fig. 2 is the schematic structural diagram of the first embodiment of the motherboard testing system of the present invention, as shown in fig. 2, in this embodiment, a motherboard testing system is provided, and the motherboard testing system of this embodiment may include: a motherboard test element 10 and a motherboard 20.

The motherboard testing device 10 in this embodiment has a first substrate 11, a first electrical connector 12 and a testing chip 13, and the first electrical connector 12 and the testing chip 13 are disposed on the first substrate 11. The first substrate 11 is used to carry other objects (such as the first electrical connector 12 and the test chip 13) and provide a current transmission medium between the objects, so that the first substrate 11 can be a Printed Circuit Board (PCB) or a metal Circuit Board (PCB) or other devices with similar functions.

The first electrical connector 12 in this embodiment is disposed on the first substrate 11 and electrically connected to the test chip 13, and is used for electrically connecting with a second electrical connector 21, for example, plugging the second electrical connector 21 to electrically connect the motherboard test element 10 with the motherboard 20, so that the motherboard 20 and the motherboard test element 10 can perform information transmission. Alternatively, the first electrical connector 12 may be located at an edge of the first substrate 11 to facilitate mating with the second electrical connector 21.

The test chip 13 in this embodiment is used to store an application program code for testing the motherboard 20, and may provide the motherboard 20 with the application program code for testing the motherboard 20. For example, the test chip 13 may be a Serial Peripheral Interface (SPI) type chip, and the test chip 13 may be a memory chip in the prior art, and the description of the test chip 13 in this embodiment is not repeated herein.

The motherboard 20 in this embodiment has a second electrical connector 21, and the second electrical connector 21 is disposed on the motherboard 20 and is used for electrically connecting with the first electrical connector 12, for example, plugging with the first electrical connector 12 to realize electrical connection. Alternatively, the second electrical connector may be located at an edge of the motherboard 20 to facilitate mating with the first electrical connector 12. Optionally, the first electrical connector 12 and the second electrical connector 21 are opposite.

The motherboard 20 of the present embodiment further includes all components included in the motherboard in the prior art, and in the present embodiment, only a Central Processing Unit (CPU) 22 of the motherboard 20 is shown, and the second electrical connector 21 is electrically connected to the CPU 22, after the first electrical connector 12 and the second electrical connector 21 are electrically connected, the CPU 22 of the motherboard 20 can call the test chip 13 in the motherboard test element 10 to test the motherboard 20, that is, the CPU 22 of the motherboard 20 is electrically connected to the test chip 13 of the motherboard test element 10, so that the CPU 22 can load an application program code stored in the test chip 13, and run the application program code to test the motherboard 20.

Alternatively, the first electrical connector 12 in this embodiment may be directly joined with the second electrical connector 21.

Optionally, the motherboard testing system of the present embodiment may further include a connecting element 30, and two sides of the connecting element 30 are electrically connected to the first electrical connector 12 and the second electrical connector 21, respectively. That is, the first electrical connector 12 is separated from the second electrical connector 21, and then the first electrical connector 12 and the second electrical connector 21 are electrically connected to each other by the connecting member 30. Alternatively, the connecting member 30 may be a printed circuit board, a flexible circuit board, a wire, or other components capable of transmitting signals, and both sides of the connecting member 30 may have electrical connectors (not shown), so that both sides of the connecting member 30 can be electrically connected to the first electrical connector 12 and the second electrical connector 21, respectively. The connecting member 30 can increase a distance between the motherboard testing component 10 and the motherboard 20, so that the motherboard testing component 10 and the motherboard 20 can be located in two separated spaces.

When the motherboard 20 needs to be tested according to different application program codes, a plurality of motherboard test elements 10 can be adopted, one application program code is stored in each motherboard test element 10, different motherboard test elements 10 are connected with the motherboard 20, and plug and play are performed, so that the purpose of testing the motherboard 20 by adopting different application program codes is achieved, and the operation process of repeatedly erasing and burning the memory chip in the motherboard is avoided. Meanwhile, one motherboard testing component 10 can be connected to a plurality of different motherboards 20, so that the purpose of testing a plurality of motherboards 20 can be achieved only by burning application program codes once. Therefore, the mainboard test system can improve the test efficiency of the mainboard.

In this embodiment, the motherboard testing system adopts the testing chip 13 in the motherboard testing component 10 to test the motherboard 20, so that the purpose of testing the motherboard 20 according to different application program codes can be realized by replacing different motherboard testing components 10, and the purpose of testing a plurality of motherboards 20 by using one testing chip can also be realized by replacing different motherboards 20, thereby saving the operation processes of erasing and burning the application program codes of the motherboard, and improving the testing efficiency of the motherboard.

Fig. 3 is a schematic circuit diagram of the motherboard testing element in fig. 2, fig. 4 is a schematic circuit diagram of the motherboard in fig. 2, as shown in fig. 3 and fig. 4, the first electrical connector 12 of the motherboard testing element 10 provided in this embodiment may include pins, for example, the first electrical connector 12 may be a pin array connector or a non-pin array connector, and optionally, the first electrical connector 12 may include two rows of pins, the second electrical connector 21 of the motherboard 20 provided in this embodiment may also include pins, for example, the second electrical connector 21 may be a pin array connector or a non-pin array connector, and optionally, the second electrical connector 21 may also include two rows of pins, and each row of pins includes N pins, N is an integer greater than or equal to 4, in order to electrically connect the first electrical connector 12 and the second electrical connector 21, both sides of the connecting part 30 respectively include two rows of pin holes, that is, each side of the connecting component 30 includes two rows of pin holes, each row of pin holes includes N pin holes, and the number of pins included in each row of pin holes is the same as the number of pin holes included in each row of pin holes, so that the two rows of pins of the first electrical connector 12 can be pressed into the two rows of pin holes on one side of the connecting component 30, and the two rows of pins of the second electrical connector 21 can also be pressed into the two rows of pin holes on the other side of the connecting component 30, thereby realizing the phase electrical connection between the first electrical connector 12 and the second electrical connector 21.

Each row of pins in the first electrical connector 12 and the second electrical connector 21 shown in the present embodiment comprises 5 pins. As shown in fig. 3, the first electrical connector 12 includes pins No. 1, No. 2, No. 3, No. 4, No. 5, No. 6, No. 7, No. 8, No. 9, and No. 10, but pins are not shown at the pin No. 4 of the first electrical connector 12 in this embodiment. As shown in fig. 4, the second electrical connector 21 includes pins No. 1, No. 2, No. 3, No. 4, No. 5, No. 6, No. 7, No. 8, No. 9, and No. 10, but pins are not shown at the pin No. 4 of the first electrical connector 12 in this embodiment.

In this embodiment, the test chip 13 has an SPI interface, and the test chip 13 shown in fig. 3 has an SPI interface. The 4 pin holes of the first electrical connector 12 are connected to an enable signal line (CPU0_ GPIO0), a data input line (CPU0_ SPI _ SDI), a data output line (CPU0_ SPI _ SDO), and a clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the test chip 13, respectively. The CPU 22 of the main board 20 also has an SPI interface, and the 4 pins of the second electrical connector 21 are connected to an enable signal line (CPU0_ GPIO0), a data input line (CPU0_ SPI _ SDI), a data output line (CPU0_ SPI _ SDO), and a clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the CPU 22, respectively. Therefore, the phase electrical connection between the SPI interface of the CPU 22 and the SPI interface of the test chip 13 can be realized through the phase electrical connection between the first electrical connector 12 and the second electrical connector 21, so that the enable signal of the CPU 22 can be transmitted to the second electrical connector 21 through the enable signal line (CPU0_ GPIO0) of the SPI interface of the CPU 22, transmitted to the first electrical connector 12 through the phase electrical connection between the second electrical connector 21 and the first electrical connector 12, and transmitted to the test chip 3513 through the enable signal line (CPU0_ GPIO0) of the SPI interface of the test chip 13, so that the CPU 22 can enable the test chip 13, and the CPU 22 can call the test chip 13 to test the motherboard 20.

Optionally, the positions of the 4 pins of the SPI interface of the test chip 13 in the first electrical connector 12 are the same as the positions of the 4 pins of the SPI interface of the CPU 22 in the second electrical connector 21. In one possible implementation, as shown in fig. 3, pin No. 1 of the first electrical connector 12 is connected to an enable signal line (CPU0_ GPIO0) of the SPI interface of the test chip 13, pin No. 3 of the first electrical connector 12 is connected to a data input line (CPU0_ SPI _ SDI) of the SPI interface of the test chip 13, pin No. 5 of the first electrical connector 12 is connected to a data output line (CPU0_ SPI _ SDO) of the SPI interface of the test chip 13, and pin No. 7 of the first electrical connector 12 is connected to a clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the test chip 13; similarly, as shown in fig. 4, pin No. 1 of the second electrical connector 21 is connected to an enable signal line (CPU0_ GPIO0) of the SPI interface of the CPU 22, pin No. 3 of the second electrical connector 21 is connected to a data input line (CPU0_ SPI _ SDI) of the SPI interface of the CPU 22, pin No. 5 of the second electrical connector 21 is connected to a data output line (CPU0_ SPI _ SDO) of the SPI interface of the CPU 22, and pin No. 7 of the second electrical connector 21 is connected to a clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the CPU 22.

In order to ensure the normal start of the test chip 13, the test chip 13 needs to be powered, and optionally, a power supply may be specially provided externally to supply power to the test chip 13.

Alternatively, when the first electrical connector 12 is electrically connected to the second electrical connector 21, the test chip 13 is powered by the power supply of the motherboard 20. As shown in fig. 4, the present embodiment further shows a power supply 23 of the motherboard 20, one pin of the second electrical connector 21 is electrically connected to the power supply 23 of the motherboard 20, and the pin of the power supply 23 electrically connected to the motherboard 20 is different from the 4 pins connected to the SPI interface of the CPU 22. As shown in fig. 3, one pin of the first electrical connector 12 is connected to the power supply line (VDD _ SPI _ CARD) of the test chip 13, and the pin connected to the power supply line of the test chip 13 is different from the 4 pins connected to the SPI interface of the test chip 13, so that the power supply 23 of the motherboard 20 directly supplies power to the test chip 13 through the electrical connection between the first electrical connector 12 and the second electrical connector 21, and optionally, the position of the pin connected to the power supply 23 of the motherboard 20 in the second electrical connector 21 is the same as the position of the pin connected to the test chip 13 and used for transmitting power to the test chip 13 in the first electrical connector 12. In one possible implementation, pin No. 6 of the first electrical connector 12 is connected to the test chip 13, and pin No. 6 of the second electrical connector 21 is connected to the power supply 23.

Optionally, the voltage of the power supply 23 of the motherboard 20 is 1.8V or 3.3V.

As shown in fig. 4, this embodiment also shows the memory chip 24 of the motherboard 20, the memory chip 24 may have an SPI interface, and optionally, one pin of the second electrical connector 21 is connected to the enable signal line (CPU0_ GPIO0_ R) of the SPI interface of the memory chip 24 of the motherboard 20, that is, the enable signal line (CPU0_ GPIO0_ R) of the SPI interface of the memory chip 24 is not directly connected to the enable signal line (CPU0_ GPIO0) of the SPI interface of the CPU 22, and it should be noted that the pin connected to the enable signal line (CPU0_ GPIO0_ R) of the SPI interface of the memory chip 24 may be different from the 4 pins connected to the SPI interface of the CPU 22, and the pin connected to the enable signal line (CPU0_ GPIO0_ R) of the SPI interface of the memory chip 24 may be different from the pin connected to the power supply 23.

A data input line (CPU0_ SPI _ SDI), a data output line (CPU0_ SPI _ SDO), and a clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the memory chip 24 of the main board 20 are connected to the data input line (CPU0_ SPI _ SDI), the data output line (CPU0_ SPI _ SDO), and the clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the CPU 22, respectively; that is, the data input line (CPU0_ SPI _ SDI) of the SPI interface of the memory chip 24 is directly connected to the data input line (CPU0_ SPI _ SDI) of the SPI interface of the CPU 22, the data output line (CPU0_ SPI _ SDO) of the SPI interface of the memory chip 24 is directly connected to the data output line (CPU0_ SPI _ SDO) of the SPI interface of the CPU 22, and the clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the memory chip 24 is directly connected to the clock signal line (CPU0_ SPI _ SCK) of the SPI interface of the CPU 22.

Wherein, the pin of the enable signal line of the SPI interface of the connection memory chip 24 and the pin of the enable signal line of the SPI interface of the connection CPU 22 are connected through the jump device to realize the short circuit of the second electrical connector. Fig. 5 is a schematic diagram of the jump and cap device provided by the present invention, as shown in fig. 5, the jump and cap device 40 may have two pin holes, as shown in fig. 4, in this embodiment, the pin 1 of the second electrical connector 21 on the motherboard 20 is connected to the enable signal line (CPU0_ GPIO0) of the SPI interface of the CPU 22, and the pin 2 is connected to the enable signal line (CPU0_ GPIO0_ R) of the SPI interface of the memory chip 24, when the first electrical connector 12 is disconnected from the second electrical connector 21, the jump and cap device 40 shown in fig. 5 may be connected to the second electrical connector 21, that is, the two pin holes of the jump and cap device 40 are pressed to the pin 1 and the pin 2 of the second electrical connector 21, so that the pin 1 of the array is electrically connected to the pin 2, and thus the second electrical connector 21, the SPI interface of the CPU 22 is electrically connected to the SPI interface of the memory chip 24, then the enable signal of the CPU 22 can be transmitted to the second electrical connector 21 through the enable signal line (CPU0_ GPIO0) of the SPI interface of the CPU 22, and then transmitted to the memory chip 24 through the enable signal line (CPU0_ GPIO0_ R) of the SPI interface of the memory chip 24 due to the short circuit of the second electrical connector 21, so that the CPU 22 can enable the memory chip 24, and then the CPU 22 can call the memory chip 24 to test the motherboard 20. If one pin of the second electrical connector 21 is connected to the enable signal line (CPU0_ GPIO0_ R) of the SPI interface of the memory chip 24, then one pin at the same position in the first electrical connector 12 is not connected to other components, such as pin No. 2 in the first electrical connector shown in fig. 3. As shown in fig. 3 and 4, the connection method of the other pins of the first electrical connector 12 and the connection method of the other pins of the second electrical connector 21 can be the same except that the connection method of the No. 2 pin of the first electrical connector 12 and the No. 2 pin of the second electrical connector 21 are different.

Alternatively, the first electrical connector 12 may comprise pins and the second electrical connector 21 may comprise pin holes; alternatively, the first electrical connector 12 may include pin holes and the second electrical connector 21 may include pins, so that the first electrical connector 12 and the second electrical connector 21 may be directly coupled.

Alternatively, the first electrical connector 12 may include a pin hole, the second electrical connector 21 may include a pin hole, and both sides of the connecting element 30 include pins, respectively, and it is also possible to electrically connect both sides of the connecting element 30 to the first electrical connector 12 and the second electrical connector 21, respectively.

Alternatively, when the second electrical connector 21 includes a pin hole, the snap-off device 40 may include two pins.

It should be noted that the pin holes of the first electrical connector 12 are connected in a similar manner to the pins of the first electrical connector 12, and the pin holes of the second electrical connector 21 are connected in a similar manner to the pins of the second electrical connector 21, which is not described herein again.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A motherboard test element, comprising:

2. The motherboard test element of claim 1, wherein the first electrical connector comprises two rows of pins, each row of pins comprising N pins, wherein N is an integer greater than or equal to 4;

3. The motherboard test element as recited in claim 2, wherein a pin of the first electrical connector is connected to a power supply line of the test chip to enable the motherboard to supply power to the test chip, the pin connected to the power supply line of the test chip being different from the 4 pins connected to the SPI interface of the test chip.

4. A motherboard testing system, comprising:

the mainboard test element is provided with a first substrate, a first electric connector and a test chip, wherein the first electric connector and the test chip are arranged on the first substrate, the first electric connector is electrically connected with the test chip, and the test chip is used for storing an application program code of the test mainboard;

the mainboard is provided with a second electric connector, the second electric connector is arranged on the mainboard, and the second electric connector is electrically connected with a Central Processing Unit (CPU) of the mainboard;

5. The motherboard testing system of claim 4, wherein the first electrical connector directly engages the second electrical connector.

6. The motherboard testing system of claim 4, further comprising a connector, wherein two sides of the connector are electrically connected to the first electrical connector and the second electrical connector respectively.

7. The motherboard testing system of claim 6, wherein the first electrical connector comprises two rows of pins, the second electrical connector comprises two rows of pins, each row of pins comprises N pins, two sides of the connector respectively comprise two rows of pin holes, each row of pin holes comprises N pin holes, and N is an integer greater than or equal to 4;

8. The motherboard testing system of claim 7, wherein the locations of the 4 pins of the SPI interface of the test chip in the first electrical connector are the same as the locations of the 4 pins of the SPI interface of the CPU in the second electrical connector.

9. The motherboard testing system of claim 7 or 8, wherein a pin of the first electrical connector is connected to the power supply line of the testing chip, a pin of the second electrical connector is electrically connected to the power supply of the motherboard, so that the motherboard supplies power to the testing chip, the pin connected to the power supply line of the testing chip is different from the 4 pins connected to the SPI interface of the testing chip, and the pin electrically connected to the power supply of the motherboard is different from the 4 pins connected to the SPI interface of the CPU.

10. The motherboard test system of claim 7 or 8, wherein the memory chip of the motherboard has an SPI interface; one pin in the second electric connector is connected with an enabling signal line of an SPI (serial peripheral interface) interface of a storage chip of the mainboard, and the pin of the enabling signal line of the SPI interface electrically connected with the storage chip is different from the 4 pins connected with the SPI interface of the CPU;