CN210270878U

CN210270878U - Display mainboard and display

Info

Publication number: CN210270878U
Application number: CN201921866713.0U
Authority: CN
Inventors: 王国桦; 蔡东宜
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd; Gaochuang Suzhou Electronics Co Ltd
Priority date: 2019-10-31
Filing date: 2019-10-31
Publication date: 2020-04-07
Anticipated expiration: 2029-10-31

Abstract

The utility model provides a display mainboard and display is applied to and shows technical field to match the use with the debugging device, realize not needing the shell of tearing open just can carry out software updating to the display. Wherein the display mainboard includes: the plate body, and set up control circuit, control chip and electric energy management circuit on the plate body. The control circuit is coupled with the control chip and the electric energy management circuit. The control circuit can be coupled with a debugging device for transmitting debugging signals and is conducted under the control of the working level of the control signals output by the control chip so as to transmit the debugging signals to the control chip; alternatively, the control circuit can be coupled to an external power source for providing power and shut down under control of a non-operating level of the control signal to deliver power to the power management circuit. The display main board is used for driving the display to realize display and other functions.

Description

Display mainboard and display

Technical Field

The utility model relates to a show technical field, especially relate to a display mainboard and display.

Background

In some cases, the program of the software in the display needs to be debugged to enable the software update. Before debugging, the display needs to be coupled with a debugging board for debugging, so that the debugging board outputs a debugging signal to the display. In the related art, the interface of the debugging plate does not correspond to the interface of the display, and therefore the display cannot be coupled through the interface, in this case, the display needs to be disassembled, the wiring terminal is exposed, the wiring terminal of the display is connected with the wiring terminal of the debugging plate through the resistance wire, the coupling of the debugging plate and the display is realized, and the display is debugged. This is cumbersome, time consuming and labor intensive.

SUMMERY OF THE UTILITY MODEL

To the current situation among the above-mentioned correlation technique, the embodiment of the utility model provides a display mainboard and display to the realization need not tear the shell and just can carry out software updating to the display.

In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions:

on the one hand, the embodiment of the utility model provides a display mainboard is provided, display mainboard includes: the electric energy meter comprises a plate body, and a control circuit, a control chip and an electric energy management circuit which are arranged on the plate body. The control circuit is coupled with the control chip and the electric energy management circuit. The control circuit can be coupled with a debugging device for transmitting debugging signals and is conducted under the control of the working level of the control signals output by the control chip so as to transmit the debugging signals to the control chip; alternatively, the control circuit can be coupled to an external power source for providing power and shut down under control of a non-operating level of the control signal to deliver the power to the power management circuit. The control chip is configured to generate the control signal; and receiving the debugging signal transmitted by the control circuit, and debugging the program loaded in the display mainboard.

Compared with the prior art, the utility model provides a display mainboard has following beneficial effect:

the utility model provides an among the display mainboard, control circuit can be coupled with the debugging device, can also be coupled with external power source, like this when needs carry out software updating to the display mainboard, control circuit is coupled with the debugging device to switch on when being coupled with the debugging device, with debugging signal transmission to control chip, thereby control chip receives the debugging signal of control circuit transmission, debugs the procedure that loads in the display mainboard. The control circuit is closed when being coupled with an external power supply, the transmission of signals to the control chip is blocked, and the electric energy is transmitted to the electric energy management circuit to supply power for the display mainboard to perform work such as image display. Therefore, the interference of the incidental noise to the control chip when the external power supply inputs the electric energy can be avoided, the misoperation of the control system chip is avoided, and the normal operation of the display mainboard is ensured.

Based on this, the utility model provides a when the display mainboard is applied to in the display, the interface of display not only can be coupled with external power source, can also be coupled with the debugging device, whether transmit to control chip through the signal of control circuit control input to this interface, when debugging the procedure of software in the display, only need with the interface of display and the interface coupling of debugging device can to under the prerequisite that need not tear open the machine, realize the software update to the display.

In some embodiments, the debug signal comprises a serial data signal and a serial clock signal; the control signal output by the control chip comprises a first control signal and a second control signal. The control circuit includes: a first control circuit and a second control circuit.

The first control circuit is coupled with the control chip; the first control circuit is configured to be conducted under the action of the working level of the first control signal so as to transmit the serial data signal to the control chip; or the first control signal is turned off under the action of a non-working level of the first control signal so as to transmit the electric energy to the electric energy management circuit.

The second control circuit is coupled with the control chip; the second control circuit is configured to be conducted under the action of the working level of the second control signal so as to transmit the serial clock signal to the control chip; or the power management circuit is switched off under the action of the non-working level of the second control signal so as to transmit the electric energy to the electric energy management circuit.

In some embodiments, the first control circuit includes a first transistor, a first pole of the first transistor is configured to receive the serial data signal, a second pole of the first transistor is coupled to the control chip to transmit the serial data signal, and a control pole of the first transistor is coupled to the control chip to receive the first control signal. The second control circuit comprises a second transistor, a first pole of the second transistor is configured to receive the serial clock signal, a second pole of the second transistor is coupled with the control chip to transmit the serial clock signal, and a control pole of the second transistor is coupled with the control chip to receive the second control signal.

In some embodiments, the control chip comprises: a first receive pin coupled to a second pole of the first transistor, the first receive pin configured to receive the serial data signal. A second receive pin coupled to a second pole of the second transistor, the second receive pin configured to receive the serial clock signal.

In some embodiments, the display main board further comprises: the mainboard interface is arranged on the plate body and is coupled with the control circuit and the electric energy management circuit. The motherboard interface can be coupled with an interface of the debugging device to receive the debugging signal. The motherboard interface is also capable of being coupled to the external power source to receive power provided by the external power source.

In some embodiments, the motherboard interface comprises: a negative voltage data line pin coupled to the control circuit configured to receive the serial data signal with the motherboard interface coupled to the debug device. A positive voltage data line pin coupled to the control circuit configured to receive the serial clock signal with the motherboard interface coupled to the debug device. A power line pin coupled to the power management circuit configured to receive power provided by the external power source when the motherboard interface is coupled to the external power source. A ground pin that is grounded.

In some embodiments, a negative voltage data line pin is coupled to the first control circuit and a positive voltage data line pin is coupled to the second control circuit.

In some embodiments, a negative voltage data line pin is coupled to the first pole of the first transistor and a positive voltage data line pin is coupled to the first pole of the second transistor.

In some embodiments, the motherboard interface is any one of a mini universal serial bus interface, and a type C universal serial bus.

On the other hand, the embodiment of the utility model provides a display still provides, including the display screen, and with the display screen is coupled as in any one of the above one aspect display mainboard.

The beneficial effects of the display and the display main board are the same, and are not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram illustrating a system architecture for updating software in a display according to the related art;

fig. 2 is a schematic diagram of a system architecture for updating software in a display according to the present invention;

fig. 3A is a schematic structural view of an adapter plate according to the present invention;

fig. 3B is a schematic diagram of the type of interface provided by the present invention;

fig. 4 is a schematic structural diagram of a debugging apparatus provided by the present invention;

fig. 5A is a schematic view of a first structure of a display main board according to the present invention;

fig. 5B is a schematic diagram of a second structure of the display main board according to the present invention;

fig. 5C is a schematic view of a third structure of the display main board according to the present invention;

fig. 6 is a schematic diagram of a data line provided by the present invention;

fig. 7 is a schematic diagram of the display main board and the external power source provided by the present invention;

fig. 8 is a schematic diagram of a display provided by the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail with reference to the accompanying drawings. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.

In the following, the terms "first", "second", "third", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first," "second," "third," etc. may explicitly or implicitly include one or more of the features. In the description herein, the meaning of "a plurality" is two or more unless otherwise specified.

In some embodiments, for a device, such as a display, reference to "terminals" in describing some embodiments refers to terminals disposed on a circuit board of the device for connecting wires. The connecting terminal is packaged in the outer shell of the device, and only when the outer shell of the device is removed, the connecting terminal can be exposed on the circuit board, and the connecting terminal of one device can be coupled with the connecting terminal of the other device through a wire, so that the two devices are coupled. The connection terminal may be, for example, a PCB (Printed Circuit Board) terminal, a hardware terminal, a nut terminal, a spring terminal, or the like.

The term "interface" as used in describing some embodiments refers to an interface that can be seen from the outside of the device (see the motherboard interface 35 of the display 300 in fig. 8) without disassembling the external housing of the device, and the interface of one device can be coupled with the interface of another device through a data line, so as to realize coupling between the two devices, and further realize transmission of data signals between the two devices. As shown in fig. 3B, the interface may be, for example, a universal serial bus Type a (USB Type a, shown in (a) of fig. 3B), a universal serial bus Type B (USB Type B, shown in (B) of fig. 3B), a universal serial bus Type C (USB Type C, shown in (C) of fig. 3B), a Micro universal serial bus (Micro USB, shown in (d) of fig. 3B) interface, a mini USB (shown in (e) of fig. 3B) interface, or the like.

The expressions "connected" and "coupled" and derivatives thereof are used in describing some embodiments. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components do not directly contact each other, but yet still cooperate or interact with each other, for example, the two or more components interact with each other through Wireless connection such as Wifi (Wireless Fidelity), Bluetooth (Bluetooth), GPRS (General Packet Radio Service), etc., and the like. Embodiments of the inventions herein are not necessarily limited to that which is described herein.

In some cases, the program of the software in the display needs to be debugged to enable the software update. For example, before the display leaves a factory, software function testing needs to be performed on the display, and a program of software with a detected problem needs to be debugged to realize software updating; as another example, in the process of using the display by the user, in the case of a failure of the display, or in the case of the user having a need to change the software specification of the display, the program of the software in the display needs to be debugged to realize the software update. It should be noted that the "software" of the display referred to herein may include system software, for example, system applications including an embedded application installed in the display (i.e., the display). Where the embedded application is an application provided as part of a display implementation.

As shown in fig. 1, in the related art, software update is performed on a display 100 by coupling a controller 1 (e.g., a computer) with a Debug Board 2(Debug Board), for example, coupling the controller 1 and the Debug Board through an interface (i.e., coupling an interface 11 of the controller 1 and a third interface 23 of the Debug Board), coupling the Debug Board 2 with the display 100, controlling the Debug Board 2 through the controller 1, so that the Debug Board 2 outputs a Debug signal to the display 100, and the display 100 debugs software (e.g., a program) loaded on the display 100 under the action of the Debug signal to complete the software update.

With continued reference to fig. 1, in some examples, the debug board 2 includes an Interface 24 and a connection terminal (e.g., the second connection terminal 22), wherein the Interface 24 of the debug board 2 is one of a VGA (Video Graphics Array) Interface, a DVI (Digital Video Interface) Interface, and an HDMI (High Definition multimedia Interface), and the debug board 2 is coupled to the display 100 by coupling these interfaces to corresponding interfaces of the display 100, so that the debug board 2 transmits the debug signal to the display 100 under the control of the controller 1 to update software of the display 100.

However, in a case that the display 100 does not have an interface corresponding to the VGA interface, the DVI interface and the HDMI interface of the debug board 2, for example, the interface 102 included in the display 100 is a Micro USB (Micro universal serial bus) interface, and none of the Micro USB interface and the debug board 2 has the above-mentioned interface, which can be correspondingly coupled, so that the debug board 2 and the display 100 cannot be coupled through the coupling of the interfaces, and the debug signal cannot be transmitted to the display through the debug board 2. In this case, to implement the software update of the display 100, the display 100 needs to be disassembled, the main board of the display 100 is exposed, and the connection terminal (e.g., the second connection terminal 22 in fig. 1) of the debugging board 2 is coupled to the connection terminal 101 on the main board of the display 100 through a conductive wire (e.g., a resistance wire), so as to implement the coupling of the debugging board 2 and the display 100, so as to implement the software update operation on the display 100. This method is tedious, time-consuming and labor-consuming, and during the process of removing the housing of the display 100, the components of the display 100 may be damaged due to misoperation, which may affect the normal display.

Introduce a debugging device below, and the utility model provides a can with this debugging device assorted display mainboard and display, when utilizing this debugging device to carry out software updating to the display, need not tear the machine open to the display, convenient operation saves consuming time. In order to introduce the display main board and the display more clearly, the debugging device is introduced first.

As shown in fig. 2 and 4, the debugging apparatus 200 includes: the debugging board 2 and the adapter board 4, wherein the debugging board 2 is configured to generate a debugging signal according to the instruction output by the controller 1, and the adapter board 4 is configured to receive the debugging signal and to adapter the debugging signal, so as to input the debugging signal to a device to be debugged (for example, the display 300).

The debugging board 2 includes: a second board body 21, a second connection terminal 22 and a third interface 23. The second connection terminal 22 is disposed on the second board body 21. A third interface 23 is disposed on the second board body 21, the third interface 23 can be coupled with the controller 1 (for example, a computer), and the third interface 23 is configured to receive an instruction output by the controller 1, so that the debug board 2 outputs the debug signal according to the instruction.

As shown in fig. 3A, the interposer 4 includes: a first board body 41, a first connection terminal 42, and a first interface 43. The first connection terminal 42 is disposed on the first board body 41, and the first connection terminal 42 can be coupled to the second connection terminal 22 of the debugging board 2 to receive the debugging signal output by the debugging board 2, and transfer the debugging signal to output the transferred debugging signal. The first interface 43 is disposed on the first board 41, the first interface 43 is coupled to the first connection terminal 42, and the first interface 43 can be coupled to a device to be debugged. The first interface 43 is configured to transmit the transferred debug signal to the device to be debugged.

The debugging device 200 comprises a patch panel 4 and a debugging panel 2, wherein the debugging panel 2 is configured to generate a debugging signal according to an instruction output by the controller 1, and the patch panel 4 is configured to receive the debugging signal, transfer the debugging signal, and input the debugging signal to the device to be debugged. Debugging board 2 includes second binding post 22 and third interface 23, second binding post 22 is coupled with the first binding post 42 of keysets 4, third interface 23 is coupled with controller 1, controller 1 has been realized, sequential coupling of debugging board 2 and keysets 4, thereby under the prerequisite that need not treat that the debugging device tears the machine open, directly couple the first interface 43 of debugging board 2 with treating the debugging device, and then debugging device 200 is under the control of controller 1, just can realize treating the debugging device and carry out software updating, and is convenient for operation, and the operating efficiency is improved, and the operating time is saved.

In some embodiments, the debug signals received by the patch panel 4 include TX (transmit) signals and RX (receive) signals. As shown in fig. 3A, the first connection terminal 42 includes a first pin 421, a second pin 422, and a third pin 423.

The first pin 421 is configured to receive a TX signal and convert the TX signal into a serial data Signal (SDA); the second pin 422 is configured to receive an RX signal and to convert the RX signal to a Serial clock Signal (SCL); the third pin 423 is grounded.

The debug signal is switched through the first pin 421 and the second pin 422, so that the switched debug signal can be received by the pins of the first interface 43. The third pin 423 is grounded, so that a stable low level can be provided, and the risk of electric shock is reduced.

In some embodiments, with continued reference to fig. 3A, the first interface 43 includes: a first negative voltage data line pin 431, a first positive voltage data line pin 432, and a first ground pin 433.

The first negative voltage data line pin 431 is coupled to the first pin 421, and the first negative voltage data line pin 431 is configured to receive a serial data signal. The first positive voltage data line pin 432 is coupled to the second pin 422, and the first positive voltage data line pin 432 is configured to receive a serial clock signal. The first ground pin 433 is grounded.

The first negative voltage data line pin 431 and the first positive voltage data line pin 432 respectively receive a serial data signal and a serial clock signal, so that the switched debugging signal is received, and the switched debugging signal is transmitted to a device to be debugged. The first ground pin 433 is grounded, which can provide a stable low level for the first interface 43, thereby reducing the risk of electric shock.

In some embodiments, as shown in fig. 3A, the interposer 4 further includes a first resistor 44 and a second resistor 45, wherein a first end of the first resistor 44 is coupled to the first negative voltage data line pin 431 of the first interface 43, and a second end of the first resistor 44 is coupled to the first pin 421 of the first connection terminal 42; a first terminal of the second resistor 45 is coupled to the first positive voltage data line pin 432 of the first interface 43, and a second terminal of the second resistor 45 is coupled to the second pin 422 of the first connection terminal 42.

By providing the first resistor 44 and the second resistor 45, the interference on the serial data signal transmitted from the first pin 421 to the first negative voltage data line pin 431 and the interference on the serial clock signal transmitted from the second pin 422 to the first positive voltage data line pin can be reduced, so that the transmitted signals are more accurate.

With continuing reference to fig. 3A and fig. 4, in some embodiments, the interposer 4 further includes: a second interface 46 disposed on the first board body 41, wherein the second interface 46 is coupled to the first interface 43, and the second interface 46 is capable of being coupled to a first power source. The second interface 46 is configured to receive power provided by the first power source and transmit the received power to the first interface 43.

In the process of updating the software of the device to be debugged, an external power supply is required to be accessed to provide electric energy for the device to be debugged so as to support the software updating. For example, the external power source may be accessed by coupling an interface of the device to be debugged with the first power source. In the case that the device to be debugged includes only one interface, for example, as shown in fig. 2, taking the device to be debugged as the display 300 as an example, the display 300 includes only the motherboard interface 35, and when the software update is performed, since the motherboard interface 35 of the display 300 is coupled with the first interface 43 of the patch panel 4, the display 300 cannot be coupled with the first power supply. In this case, the second interface 46 included in the adapter board 4 is coupled to the first power supply, receives the power provided by the first power supply, transmits the received power to the first interface 43, and transmits the power to the device to be debugged through the first interface 43, so as to provide power for the software update operation of the device to be debugged.

Continuing to refer to fig. 3A, the first interface 43 further includes a first power line pin 434, for example. The second interface 46 includes: a second power line pin 461 and a second ground pin 462.

The second power line pin 461 is coupled to the first power line pin 434, the second power line pin 461 can be coupled to the first power source, and the second power line pin 461 is configured to receive the power provided by the first power source and transmit the received power to the first power line pin 434. The second ground pin 462 is grounded.

The second power line pin 461 is coupled to the first power line pin 434, so that the electric energy received by the second interface 46 is transmitted to the first interface 43, and further the electric energy is transmitted to the device to be debugged through the first interface 43.

In other embodiments, in the case that the device to be debugged includes at least two interfaces, during the process of performing the software update, one of the interfaces is coupled to the first interface 43 of the interposer 4, and the other interface is coupled to the first power supply, so that the device to be debugged can be directly powered by the first power supply to ensure the performance of the software update. In this case, it may not be necessary to provide the second interface 46 for coupling with an external power supply in the interposer 4.

In some embodiments, as shown in fig. 3A, the interposer 4 further comprises: a capacitor 47 disposed on the first board 41, wherein one end of the capacitor 47 is coupled to a node, which is equivalent to a node where the second power line pin 461 of the second interface 46 and the first power line pin 434 of the first interface 43 are coupled, and the other end of the capacitor 47 is grounded.

By arranging the capacitor 47, the electric energy provided by the first power supply to the second interface 46 can be more stably transmitted to the first interface 43, so that stable electric energy is provided for the device to be debugged during software updating, and smooth software updating process is ensured.

The embodiment of the utility model provides an in not injecing the type of first interface 43 and second interface 46 of keysets 4, the type of first interface 43 and second interface 46 can be selected according to actual need, as long as can realize the two function that will realize respectively. Illustratively, as shown in fig. 3B, the type of the first interface 43 or the second interface 46 may select one of a type a universal serial bus (USB type a) interface, a type B universal serial bus (USB type B) interface, a type C universal serial bus (USB type C) interface, a Micro universal serial bus (Micro USB) interface, a Mini universal serial bus (Mini USB) interface, and the like. For example, the first interface 43 is a type a universal serial bus (USB type a) interface. For example, the second interface 46 is a Micro universal serial bus (Micro USB) interface.

In some embodiments, as shown in fig. 4, in the case where the first connection terminal 42 of the interposer 4 includes a first pin 421, a second pin 422, and a third pin 423, the second connection terminal 22 of the debug board 2 needs to be matched with the first connection terminal 42 of the interposer 4, and the second connection terminal 22 of the debug board 2 includes: a fourth pin 221, a fifth pin 222, and a sixth pin 223.

The fourth pin 221 is coupled to the first pin 421, and the fourth pin 221 is configured to output a TX signal. The fifth pin 222 is coupled to the second pin 422, and the fifth pin 222 is configured to output an RX signal. The sixth pin 223 is coupled to the third pin 423, and the sixth pin 223 is grounded.

The fourth pin 221 and the fifth pin 222 are respectively coupled to the first pin 421 and the second pin 422, and the TX signal and the RX signal are respectively input to the first connection terminal 42, so as to input the debug signal generated by the debug board 2 to the patch board 4. The sixth pin 223 is grounded, so that a stable low level can be provided for the second connection terminal 22, and the risk of electric shock is reduced.

In some embodiments, please continue to refer to fig. 4, the debugging apparatus 200 further includes: and three resistance lines, through which the respective pins of the first connection terminal 42 are coupled to the respective pins of the second connection terminal 22, respectively.

In some embodiments, the third interface 23 of the debug board 2 is a type B universal serial bus (USB type B) interface, through which a computer is coupled to the debug board 2 to transmit instructions.

The above is a description of the debugging apparatus 200 used for updating software of a display, and the display main board provided by the present invention is described below.

Referring to fig. 2, fig. 5A to 5C, and fig. 7, some embodiments of the present invention provide a display main board 3, including: the board 31, and a control circuit 32, a control chip 33 and an electric energy management circuit 34 which are arranged on the board 31.

The control circuit 32 is coupled to the control chip 33 and the power management circuit 34.

The control circuit 32 can be coupled to a debugging device for transmitting the debugging signal, and is turned on under the control of the operating level of the control signal output by the control chip 33 to transmit the debugging signal to the control chip 33. Alternatively, the control circuit 32 can be coupled to an external power source for providing power and shut down under control of a non-operational level of the control signal to deliver power to the power management circuit.

The control chip 33 is configured to generate a control signal; and, receiving the debugging signal transmitted by the control circuit 32, debugging the program loaded in the display main board.

The embodiment of the present invention provides a display main board 3, for example, a driving main board of a display, in some embodiments, the display main board 3 is integrated with various electronic components, circuits, chips, etc. to support the display to realize various functions such as image display, touch control, etc.

In some embodiments, in the case that the debugging apparatus is the above-mentioned debugging apparatus 200, the debugging apparatus 200 outputs the transit debugging signal, and the control circuit 32 is turned on by the control signal to transmit the transit debugging signal to the control chip 33. The following description will be given taking the debugging apparatus 200 as an example.

The utility model provides an in display mainboard 3, control circuit 32 can be coupled with debugging device 200, can also be coupled with external power source, when needs carry out software updating to display mainboard 3 like this, control circuit 32 is coupled with debugging device 200 to switch on when coupling with debugging device 200, with debugging signal transmission to control chip 33, thereby control chip 33 receives the debugging signal of control circuit 32 transmission, debugs the program that loads in the display mainboard.

After the software update of the display main board 3 is completed, or under the condition that the software update operation is not performed, the display main board 3 drives the display to perform the work such as image display, and at this time, the control circuit 32 is coupled with the external power source and is turned off when being coupled with the external power source, so as to block the transmission of noise possibly attached when the external power source supplies power to the control chip 33, and transmit the power to the power management circuit 34, so as to supply power for the work such as image display, and the like, of the display main board 3. Therefore, the interference of the noise possibly attached to the external power supply to the control chip 33 can be avoided when the external power supply inputs electric energy, the misoperation of the control chip 33 is avoided, and the normal operation of the display main board 3 is ensured.

That is to say, the utility model provides an among the display mainboard 3, through setting up control circuit 32, and control circuit 32 can switch on or close under the control of the control signal of control chip 33 output, realized the transmission of control input to display mainboard 3's signal to control chip 33 (and electric energy management circuit 34) to make display mainboard 3 can normally work.

Based on this, the utility model provides a when display mainboard 3 is applied to in the display, the interface of display can be coupled with debugging device 200, also can be coupled with external power source, switch on and close the realization through control circuit 32 and transmit the control to control chip 33 to the signal of this interface of input, when debugging the procedure of software in the display, only need with the interface of display and debugging device 200 the interface coupling can, thereby under the prerequisite that does not need the tear open the machine, realize the software update to the display.

In some examples, when the control circuit is coupled to the debugging apparatus 200, the adapter board 4 in the debugging apparatus 200 further includes a second interface, and when receiving the power provided by the first power supply, the debugging apparatus 200 not only outputs the adapted debugging signal, but also can provide the power for the display motherboard, and the power provided by the debugging apparatus 200 is transmitted to the power management circuit 34 to supply power to the display motherboard 3, so as to ensure that the control chip 33 debugs the program loaded in the display motherboard.

In some embodiments, the debug signal includes a serial data signal and a serial clock signal; the control signals output by the control chip 33 include a first control signal and a second control signal.

As shown in fig. 5B, the control circuit 32 includes: a first control circuit 321 and a second control circuit 322.

The first control circuit 321 is coupled to the control chip 33; the first control circuit 321 is configured to be turned on by an operating level of the first control signal to transmit the serial data signal to the control chip 33; or alternatively, shut down under the non-operating level of the first control signal to deliver power to the power management circuit 34.

The second control circuit 322 is coupled to the control chip 33; the second control circuit 322 is configured to be turned on by the operating level of the second control signal to transmit the serial clock signal to the control chip 33; or alternatively, shut down under the non-operating level of the second control signal to deliver power to the power management circuit 34.

In some embodiments, the "operating level" of the first control signal refers to a level that enables the first control circuit 321 to be turned on, and correspondingly, the "non-operating level" refers to a level that does not enable the first control circuit 321 to be turned on (i.e., the first control circuit 321 is turned off). In other embodiments, the "active level" of the second control signal refers to a level that enables the second control circuit 322 to be turned on, and correspondingly, the "inactive level" refers to a level that does not enable the second control circuit 322 to be turned on (i.e., the second control circuit 322 is turned off).

Because the first control circuit 321 and the second control circuit 322 are disposed in the display main board 3, and the first control circuit 321 and the second control circuit 322 can be turned on or off under the action of the control signal, when the control circuit of the display main board 3 is coupled to the debugging apparatus 200, under the action of the working level of the first control signal, the first control circuit 321 is turned on, and under the action of the working level of the second control signal, the second control circuit 322 is turned on, so that the serial data Signal (SDA) and the serial clock Signal (SCL) can be transmitted to the control chip 33, and the control chip 33 debugs the program loaded in the display main board according to the transferred debugging signal.

In some embodiments, when the control circuit of the display main board 3 is coupled to the debugging apparatus 200, the debugging signal output by the debugging apparatus 200 is transmitted to the control chip 33 through the first control circuit 321 and the second control circuit 322; the electric energy provided by the debugging device 200 is transmitted to the electric energy management circuit 34 to supply power to the display main board 3, so as to ensure that the control chip 33 can debug the program loaded in the display main board 3 normally.

When the control circuit 32 of the display main board 3 is coupled with the external power supply, under the effect of the non-working level of the first control signal, the first control circuit 321 is turned off, under the effect of the non-working level of the second control signal, the second control circuit 322 is turned off, thereby other signals except for the electric energy attached to the external power supply are prevented from being transmitted to the control chip 33, the electric energy provided by the external power supply is transmitted to the electric energy management circuit, thereby supplying power to the display main board 3, enabling the display main board to normally work, avoiding the control chip 33 from being interfered by noise to cause misoperation, and ensuring the normal operation of the display main board 3.

In some embodiments, as shown in fig. 5C, the first control circuit 321 includes a first transistor T1, a first pole of the first transistor T1 is configured to receive the serial data signal, a second pole of the first transistor T1 is coupled to the control chip 33 to transmit the serial data signal, and a control pole of the first transistor T1 is coupled to the control chip 33 to receive the first control signal. In this way, in the case where the level of the first control signal received by the gate of the first transistor T1 is the operation level, the first transistor T1 is turned on, so that the serial data signal is transmitted to the control chip 33 through the first transistor T1. When the level of the first control signal received by the control electrode of the first transistor T1 is at the off level, the first transistor T1 is turned off to prevent noise from being transmitted to the control chip 33, so that the power supplied by the external power source is transmitted to the power management circuit 34.

The second control circuit 322 includes a second transistor T2, a first pole of the second transistor T2 is configured to receive the serial clock signal, a second pole of the second transistor T2 is coupled to the control chip 33 to transmit the serial clock signal, and a control pole of the second transistor T2 is coupled to the control chip 33 to receive the second control signal. In this way, in the case that the second control signal received by the control electrode of the second transistor T2 is at the operation level, the second transistor T2 is turned on, so that the serial data signal is transmitted to the control chip 33 through the second transistor T2. When the level of the second control signal received by the control electrode of the second transistor T2 is at the non-operating level, the second transistor T2 is turned off to prevent noise from being transmitted to the control chip 33, so that the power supplied by the external power source is transmitted to the power management circuit 34.

The operating level may be higher or lower than the non-operating level depending on the type (N-type or P-type) of transistors in the circuit configuration of the first and second control circuits 321 and 322, and the like. For example, the first transistor T1 and the second transistor T2 are N-type transistors, the operation level of the first control signal is high level, and the operation level of the second control signal is high level, so that the first transistor T1 and the second transistor T2 are turned on under the control of the high level. Alternatively, the first transistor T1 and the second transistor T2 are P-type transistors, the operation level of the first control signal is a low level, and the operation level of the second control signal is a low level, so that the first transistor T1 and the second transistor T2 are turned on under the control of the low level. The embodiment of the present invention is not limited to the types of the first transistor T1 and the second transistor T2.

For example, the types of the first transistor T1 and the second transistor T2 may be the same or different, so that the operating levels of the first control signal and the second control signal are both high or both low when the types of the first transistor T1 and the second transistor T2 are the same. In the case where the types of the first transistor T1 and the second transistor T2 are different, the operation level of one of the first control signal and the second control signal is high level and the operation level of the other is low level.

In some embodiments, the first transistor T1 and the second transistor T2 used in the circuit provided by the embodiments of the present invention may be thin film transistors, field effect transistors, or other switching devices.

In some embodiments, the control electrodes of the first transistor T1 included in the first control circuit 321 and the second transistor T2 included in the second control circuit 322 are gates of transistors, the first electrode is one of a source and a drain of the transistor, and the second electrode is the other of the source and the drain of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, the source and the drain may not be different in structure, that is, the first pole and the second pole of the transistor in the embodiment of the present invention may not be different in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In some embodiments, the first control circuit 321 further includes a plurality of transistors connected in parallel with the first transistor T1, i.e., a control electrode of each of the plurality of transistors and a control electrode of the first transistor T1 both receive the first control signal, a first electrode of each of the plurality of transistors and a first electrode of the first transistor T1 are coupled to the third negative voltage data line pin 351, and a second electrode of each of the plurality of transistors and a second electrode of the first transistor T1 are coupled to the first receiving pin 331. In this way, each of the plurality of transistors achieves the same function as the first transistor T1, and a detailed switching principle will not be described.

The second control circuit 322 further includes a plurality of transistors connected in parallel with the second transistor T2, and the connection manner of the plurality of transistors can be referred to the plurality of transistors included in the first control circuit 321, which is not described herein again.

In the embodiment of the present invention, the specific implementation manner of the first control circuit 321 and the second control circuit 322 is not limited to the above-described manner, and may be any implementation manner that can be used, for example, a conventional connection manner known to those skilled in the art, and only needs to ensure that the corresponding function is implemented. The above examples do not limit the scope of the present invention. In practical application, a technician can selectively use or not use one or more of the circuits according to the situation, and various combination variants based on the circuits do not depart from the principle of the present invention, which is not repeated herein.

In some embodiments, as shown in fig. 5A to 5C, the control chip 33 includes: a first receiving pin 331 and a second receiving pin 332.

The first receiving pin 331 is coupled to the second pole of the first transistor T1, and the first receiving pin 331 is configured to receive a serial data signal.

The second receive pin 332 is coupled to a second pole of the second transistor T2, the second receive pin 332 configured to receive a serial clock signal.

The reception of the serial data signal and the serial clock signal is realized through the first receiving pin 331 and the second receiving pin 332 provided on the control chip 33.

In some embodiments, as shown in fig. 5A, the display main board 3 further includes: a motherboard interface 35 disposed on the board 31, wherein the motherboard interface 35 is coupled to the control circuit 32 and the power management circuit 34.

The motherboard interface 35 can be coupled with an interface of a debugging apparatus to receive a debugging signal. That is, the control circuit 32 is coupled to the debugging apparatus 200 through the motherboard interface 35.

The motherboard interface 35 can also be coupled to an external power source to receive power from the external power source. That is, the control circuit 32 is coupled to an external power source through the motherboard interface 35.

In the above embodiment, the motherboard interface 35 included in the display motherboard 3 can be coupled to an interface of the debugging apparatus 200 (the first interface 43 of the adapter board 4 in the debugging apparatus 200), receive the adapted debugging signal output by the adapter board 4, and then transmit the adapted debugging signal to the control chip 33 through the control circuit 32, and the control chip 33 receives the adapted debugging signal to debug the program loaded in the display motherboard 3. Therefore, when software is updated, only the mainboard interface 35 of the display mainboard 3 needs to be coupled with the first interface 43 of the adapter plate 4, so that the operation is simple and convenient, and the time consumption is reduced.

The main board interface 35 is also capable of coupling with an external power source, receiving the electric power provided by the external power source, and transmitting the electric power to the electric power management circuit 34 to provide the electric power for the display main board 3, thereby ensuring the operation of the display main board to display images.

In some embodiments, the main board interface 35 of the display main board 3 is coupled to the first interface 43 of the interposer 4 via a data line, as shown in fig. 6, the data line 5 includes a transmission line 51 and a first connector 52 and a second connector 53 disposed at two ends of the transmission line, the first connector 52 is matched with the main board interface 35 of the display main board 3, and the second connector 53 is matched with the first interface 43 of the interposer 4. For example, when the first interface 43 of the adapter board 4 is an a-type usb interface and the motherboard interface 35 of the display motherboard 3 is a micro-usb interface, the first connector 52 and the second connector 53 included in the data line 5 are an a-type usb connector and a micro-usb connector, respectively, so that the connectors are inserted into the interfaces correspondingly, and the transmission of the debug signal after the adapter is performed can be realized.

With continued reference to fig. 5A to 5C, in some embodiments, in a case where the first interface 43 of the interposer 4 includes a first negative voltage data line pin 431, a first positive voltage data line pin 432, a first ground line pin 433, and a first power line pin 434, the motherboard interface 35 of the display motherboard 3 includes: a negative voltage data line pin 351, a positive voltage data line pin 352, a power line pin 354, and a ground line pin 353.

The negative voltage data line pin 351 is coupled to the control circuit 32, and is configured to be coupled to the first negative voltage data line pin 431 of the first interface 43 to receive the serial data signal when the motherboard interface 35 is coupled to the debugging apparatus 200.

The positive voltage data line pin 352 is coupled to the control circuit 32 and configured to receive the serial clock signal when the motherboard interface 35 is coupled to the debug apparatus 20 and coupled to the first positive voltage data line pin 432 of the first interface 43.

The power line pin 354 is coupled to the power management circuit 34 and configured to receive power from an external power source to power the display motherboard 3 when the motherboard interface 35 is coupled to the external power source. The third power line pin 354 can also be coupled to the first power line pin 434 of the first interface 43 to receive the power output by the first power line pin 434 to supply power for the software update operation.

The ground pin 353 is grounded, and can be coupled to the first ground pin 433 of the first interface 43 when the motherboard interface 35 is coupled to the debugging apparatus 200.

The first negative voltage data line pin 431, the first positive voltage data line pin 432, the first ground line pin 433, and the first power line pin 434 of the first interface 43 of the adapter board 4 are respectively coupled with the negative voltage data line pin 351, the positive voltage data line pin 352, the ground line pin 353, and the power line pin 354 of the motherboard interface 35, so as to transmit the switched debugging signals (i.e., the serial data signal and the serial clock signal) to the motherboard interface 35 of the display motherboard 3, and further to the control chip 33, and further transmit the power provided by the debugging apparatus 200 to the power management circuit 34 to supply power to the display motherboard 3.

In some embodiments, as shown in fig. 5B, the negative voltage data line pin 351 is coupled to the first control circuit 321, and the positive voltage data line pin 352 is coupled to the second control circuit 322.

Thus, when the motherboard interface 35 is coupled to the debug apparatus 100, the first control circuit 321 is turned on to transmit the serial data signal received by the negative voltage data line pin 351 to the control chip 33, and the second control circuit 322 is turned on to transmit the serial clock signal received by the positive voltage data line pin 352 to the control chip. When the motherboard interface 35 is coupled to an external power source, the first control circuit 321 is turned off to prevent the noise received by the negative voltage data line pin 351 from being transmitted to the control chip 33, and the second control circuit 322 is turned on to prevent the noise received by the positive voltage data line pin 352 from being transmitted to the control chip 33, so as to transmit the power provided by the external power source to the power management circuit 34.

In some embodiments, as shown in fig. 5C, the negative voltage data line pin 351 is coupled to a first pole of the first transistor T1, and the positive voltage data line pin 352 is coupled to a first pole of the second transistor T2.

In some embodiments, the main board interface 35 of the display main board 3 adopts any one of a Micro universal serial bus interface, a mini universal serial bus interface, and a C-type universal serial bus, and the main board interface 35 is illustratively a Micro universal serial bus (Micro USB) interface. As shown in fig. 6, in the case that the first interface 43 is an a-type usb interface and the motherboard interface 35 is a micro usb interface, the first interface 43 and the motherboard interface 35 may be coupled by using the data line 5. The data line 5 includes a transmission line 51, and a first connector 52 and a second connector 53 disposed at two ends of the transmission line, the first connector 52 is matched with the motherboard interface 35 of the display motherboard 3, and the second connector 53 is matched with the first interface 43 of the adapter board 4.

Illustratively, in a case where the first interface 43 of the interposer 4 is an a-type usb interface, and the motherboard interface 35 of the display motherboard 3 is a micro usb interface, the first connector 52 and the second connector 53 included in the data line are an a-type usb connector and a micro usb connector, respectively, so that the connectors are correspondingly inserted into the interfaces, and thus the pluggable coupling between the interposer 4 and the display motherboard 3 can be achieved without detaching the display, thereby achieving transmission of the transferred debug signal.

As shown in fig. 8, some embodiments of the present invention further provide a display 300, which includes a display screen, and the display main board 3 coupled to the display screen.

In some embodiments, the display 300 is a product with a display function, such as a mobile phone, a tablet computer, a notebook computer, a display, a digital photo frame, or a navigator, and the present invention is not limited thereto.

In some embodiments, will the utility model provides a display mainboard 3 assembles with the display screen to the assembly chassis obtains display 300, and under display mainboard 3's control, the display screen can carry out work such as image display.

The advantageous effects of the display 300 are the same as those of the display main board 3, and are not described herein.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can think of the changes or substitutions within the technical scope of the present invention, and all shall be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A display main board, comprising: the control circuit, the control chip and the electric energy management circuit are arranged on the board body; wherein the content of the first and second substances,

the control circuit is coupled with the control chip and the electric energy management circuit;

the control circuit can be coupled with a debugging device for transmitting debugging signals and is conducted under the control of the working level of the control signals output by the control chip so as to transmit the debugging signals to the control chip; alternatively, the first and second electrodes may be,

the control circuit is capable of being coupled to an external power source for providing electrical energy and being turned off under control of a non-operating level of the control signal to transfer the electrical energy to the power management circuit;

the control chip is configured to generate the control signal; and receiving the debugging signal transmitted by the control circuit, and debugging the program loaded in the display mainboard.

2. The display motherboard of claim 1, wherein the debug signal comprises a serial data signal and a serial clock signal; the control signals output by the control chip comprise a first control signal and a second control signal;

the control circuit includes:

a first control circuit coupled with the control chip; the first control circuit is configured to be conducted under the action of the working level of the first control signal so as to transmit the serial data signal to the control chip; or the first control signal is turned off under the action of a non-working level of the first control signal so as to transmit the electric energy to the electric energy management circuit;

a second control circuit coupled with the control chip; the second control circuit is configured to be conducted under the action of the working level of the second control signal so as to transmit the serial clock signal to the control chip; or the power management circuit is switched off under the action of the non-working level of the second control signal so as to transmit the electric energy to the electric energy management circuit.

3. The display motherboard of claim 2, wherein the first control circuit comprises a first transistor, a first pole of the first transistor configured to receive the serial data signal, a second pole of the first transistor coupled to the control chip to transmit the serial data signal, a control pole of the first transistor coupled to the control chip to receive the first control signal;

the second control circuit comprises a second transistor, a first pole of the second transistor is configured to receive the serial clock signal, a second pole of the second transistor is coupled with the control chip to transmit the serial clock signal, and a control pole of the second transistor is coupled with the control chip to receive the second control signal.

4. The display main board of claim 3, wherein the control chip comprises:

a first receive pin coupled to a second pole of the first transistor, the first receive pin configured to receive the serial data signal;

a second receive pin coupled to a second pole of the second transistor, the second receive pin configured to receive the serial clock signal.

5. The display main board of claim 3, further comprising:

a motherboard interface disposed on the board body, the motherboard interface being coupled to the control circuit and the power management circuit;

the mainboard interface can be coupled with an interface of the debugging device to receive the debugging signal;

the motherboard interface is also capable of being coupled to the external power source to receive power provided by the external power source.

6. The display motherboard of claim 5, wherein the motherboard interface comprises:

a negative voltage data line pin coupled to the control circuit and configured to receive the serial data signal when the motherboard interface is coupled to the debug device;

a positive voltage data line pin coupled to the control circuit and configured to receive the serial clock signal when the motherboard interface is coupled to the debug device;

a power line pin coupled to the power management circuit and configured to receive power provided by the external power source when the motherboard interface is coupled to the external power source;

a ground pin that is grounded.

7. The display motherboard of claim 6 wherein the negative voltage data line pin is coupled to the first control circuit and the positive voltage data line pin is coupled to the second control circuit.

8. The display motherboard of claim 7 wherein the negative voltage data line pin is coupled to the first pole of the first transistor and the positive voltage data line pin is coupled to the first pole of the second transistor.

9. The display main board according to claim 5, wherein the main board interface is any one of a micro universal serial bus interface, a mini universal serial bus interface, and a type C universal serial bus.

10. A display, characterized in that the display comprises a display screen, and the display main board of any one of claims 1 to 9 is coupled with the display screen.