CN107065364A - Array base palte, display panel, display device, big plate and method of testing - Google Patents
Array base palte, display panel, display device, big plate and method of testing Download PDFInfo
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- CN107065364A CN107065364A CN201710453586.0A CN201710453586A CN107065364A CN 107065364 A CN107065364 A CN 107065364A CN 201710453586 A CN201710453586 A CN 201710453586A CN 107065364 A CN107065364 A CN 107065364A
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- Prior art keywords
- array base
- base palte
- lead
- edge
- contact terminal
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
Abstract
The embodiments of the invention provide a kind of array base palte, display panel, display device, big plate and method of testing, it is related to display device technical field, the space-consuming for reducing test circuit, it is to avoid the short circuit problem caused due to the damage of test switch.Wherein, the array base palte includes many signal lines, and the one end of each signal wire at the first edge of the array base palte is connected at the first edge of the array base palte by first lead；The array base palte also includes at least one contact terminal and a plurality of second lead；One end of second lead is connected to the contact terminal, and the other end is connected at the second edge of the array base palte；The first edge is oppositely arranged with the second edge.Above-mentioned array base palte is suitable for display device.
Description
【Technical field】
The present invention relates to display device technical field, more particularly to it is a kind of array base palte, display panel, display device, big
Plate and method of testing.
【Background technology】
In the prior art, as shown in figure 1, display panel 1 includes many signal lines 30 being located in viewing area 2, to upper
Signal wire is stated to complete after wiring, it is necessary to carry out electrical testing to above-mentioned signal wire 30.
At present, the method for carrying out electrical testing to signal wire 30 is as follows：One end connection signal wire 30 of lead 50, the other end connects
Contact terminal 40 is connect, when applying electric signal to contact terminal 40, electrical testing is carried out to signal wire 30.
In above-mentioned Electrical Test Procedure, because the area occupied of contact terminal 40 is larger, therefore the quantity of contact terminal 40 is remote
Much smaller than the quantity of signal wire 30, now, many signal lines 30 must share a contact terminal 40.
But, when array base palte 1 and color membrane substrates and liquid crystal composition between array base palte and color membrane substrates are aobvious
Show after panel, must be disconnected between many signal lines 30 and a contact terminal 40 by switch 60, just can guarantee that each letter
The signal that number line 30 is received is different, and short circuit is not present between many signal lines 30.
However, the test circuit that above-mentioned contact terminal is constituted with lead, at least needs to take array base palte 500um length
Degree, also, display panel is in use, and above-mentioned switch is easy to damage and causes short circuit between many signal lines.
【The content of the invention】
The present invention provides a kind of array base palte, display panel, display device, big plate and method of testing, for reducing test
The space-consuming of circuit, it is to avoid the short circuit problem caused due to the damage of test switch.
In a first aspect, the invention provides a kind of array base palte, the array base palte includes many signal lines, each institute
State the one end of signal wire at the first edge of the array base palte and the array base palte is connected to by first lead
First edge at；
The array base palte also includes at least one contact terminal and a plurality of second lead；One end of second lead
The contact terminal is connected to, the other end is connected at the second edge of the array base palte；The first edge and described the
Two edges are oppositely arranged.
Optionally, the array base palte also includes being provided with multiple circuit boards on flexible PCB, the flexible PCB
Terminal；
Each first lead is connected to the first edge of the array base palte by the circuit board terminals
Place.
Optionally, many signal lines include a plurality of data lines and at least one clock cable；
One contact terminal includes clock signal line terminals and at least one data line terminal；Second lead
Including the 3rd lead and the 4th lead；
A plurality of first lead for connecting the data wire is connected with one article of the 3rd lead, and the 3rd lead does not draw with first
One end of line connection is connected to the data line terminal；
One article of first lead of connection clock cable is connected with one article of the 4th lead, and the 4th lead does not draw with first
One end of line connection is connected to the clock signal line terminals.
Optionally, the flexible PCB, the contact terminal, first lead and second lead are respectively positioned on
In the non-display area of the array base palte.
Optionally, connected between the contact terminal in array basal plate by resistance.
Optionally, the Standard resistance range of the resistance is more than or equal to 180K Ω, and less than or equal to 220K Ω.
Optionally, the resistance of the resistance is 200K Ω.
Optionally, the material of the resistance is polysilicon.
The second aspect of the present invention provides a kind of display panel, and the display panel is included involved by first aspect present invention
The array base palte arrived, and the color membrane substrates being oppositely arranged with array base palte；The display panel also includes being arranged on the battle array
Liquid crystal layer between row substrate and the color membrane substrates.
The third aspect of the present invention provides a kind of display device, and the display device is included involved by second aspect of the present invention
The display panel arrived.
The fourth aspect of the present invention provides a kind of big plate, and the big plate includes multiple array base paltes, the array base palte bag
Many signal lines are included, the one end of each signal wire at the first edge of the array base palte is drawn by one first
Line is connected at the first edge of the array base palte；
The array base palte also includes at least one contact terminal and a plurality of second lead；One end of second lead
The contact terminal is connected to, the other end is connected at the second edge of the array base palte；The first edge and described the
Two edges are oppositely arranged；
Wherein, at the second edge of the first lead at the first edge of i-th of array base palte and i+1 array base palte
The second lead be connected, contact terminal on the i+1 array base palte is that the signal wire on i-th of array base palte enters
Horizontal electrical signal is tested；
Wherein, i=1,2,3 ... ..., N-1, N；N is the number for the array base palte that the big plate includes.
Optionally, the array base palte also includes being provided with multiple circuit boards on flexible PCB, the flexible PCB
Terminal；
Each first lead is connected to the first edge of the array base palte by the circuit board terminals
Place.
Optionally, signal wire includes a plurality of data lines and at least one clock cable；
One contact terminal includes at least one data line terminal and clock signal line terminals；Second lead includes the 3rd
Lead and the 4th lead；
Wherein, a plurality of first lead of data wire is connected in i-th of array base palte with one positioned at i+1 array base palte
In the 3rd lead connection, one end that the 3rd lead is not connected with the first lead is connected to the i+1 array base palte
In data line terminal, the data line terminal be used on i-th of array base palte data wire carry out electrical testing；
On first lead and an i+1 array base palte that clock cable is connected in i-th of array base palte
4th lead is connected, and one end that the 4th lead is not connected with the first lead is connected to described on i+1 array base palte
Clock signal line terminals, the clock signal line terminals are used to carry out electrical testing to the clock cable on i-th of array base palte；
Wherein, i=1,2,3 ... ..., N, N are the number for the array base palte that the big plate includes.
Optionally, the flexible PCB, the contact terminal, first lead and second lead are respectively positioned on
In the non-display area of the array base palte.
Optionally, connected between the contact terminal in array basal plate by resistance.
Optionally, the Standard resistance range of the resistance is more than or equal to 180K Ω, and less than or equal to 220K Ω.
Optionally, the resistance of the resistance is 200K Ω.
Optionally, the material of the resistance is polysilicon.
Optionally, the array base palte array is arranged on the big plate.
The fifth aspect of the present invention provides a kind of method of testing, and the method for testing is applied to the invention described above fourth aspect
Involved big plate；Wherein, the of the first lead at the first edge of i-th of array base palte and i+1 array base palte
Second lead of two edges is connected；
The method of testing includes：
Electric signal is applied to the contact terminal on the i+1 array base palte, for the letter in i-th of array base palte
Number line carries out electrical testing；
Big plate is cut, multiple independent array base paltes are formed；
Wherein, i=1,2,3 ... ..., N, N are the number for the array base palte that the big plate includes.
Above-mentioned any embodiment has the beneficial effect that：
Pass through the first lead at the first edge of i-th of array base palte and i+1 array base palte in the present embodiment
The second lead at second edge is connected, and applies electric signal to the contact terminal on i+1 array base palte, so as to i-th
Signal wire in individual array base palte carries out electrical testing.I-th of array base palte is carried out by then passing through i+1 array base palte
Electrical testing, therefore after array substrate is cut, contact terminal is respectively present in from signal wire in different array base paltes,
Therefore during follow-up use will not because one end of signal wire is connected with each other and occurs short circuit, and then also without contact
Switch is set between terminal and signal wire, so as to effectively release the space in array base palte, increased between signal wire
Spacing, reduces the probability that short circuit occurs between signal wire.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be attached to what is used required in embodiment
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this area
For those of ordinary skill, without having to pay creative labor, it can also be obtained according to these accompanying drawings other attached
Figure.
Fig. 1 is the structural representation of array base palte in the prior art；
The first structure schematic diagram for the big plate that Fig. 2 is provided by the embodiment of the present invention；
Second structural representation of the big plate that Fig. 3 is provided by the embodiment of the present invention；
3rd structural representation of the big plate that Fig. 4 is provided by the embodiment of the present invention；
The first structure schematic diagram for the array base palte that Fig. 5 is provided by the embodiment of the present invention；
Second structural representation of the array base palte that Fig. 6 is provided by the embodiment of the present invention；
3rd structural representation of the array base palte that Fig. 7 is provided by the embodiment of the present invention；
4th structural representation of the array base palte that Fig. 8 is provided by the embodiment of the present invention；
5th structural representation of the array base palte that Fig. 9 is provided by the embodiment of the present invention；
The structural representation for the display panel that Figure 10 is provided by the embodiment of the present invention；
The structural representation for the display device that Figure 11 is provided by the embodiment of the present invention.
【Embodiment】
In order to be better understood from technical scheme, the embodiment of the present invention is retouched in detail below in conjunction with the accompanying drawings
State.
It will be appreciated that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
Its embodiment, belongs to the scope of protection of the invention.
The term used in embodiments of the present invention is the purpose only merely for description specific embodiment, and is not intended to be limiting
The present invention." one kind ", " described " and "the" of singulative used in the embodiment of the present invention and appended claims
It is also intended to including most forms, unless context clearly shows that other implications.
It will be appreciated that though may describe to draw using term first, second and are third in embodiments of the present invention
Line or edge, but these leads or edge should not necessarily be limited by these terms.These terms be only used for by lead or edge that
This is distinguished.For example, in the case where not departing from range of embodiment of the invention, the first lead can also be referred to as the second lead,
Similarly, the second lead can also be referred to as the first lead；Similarly, first edge is also referred to as second edge.
The present embodiment provides a kind of big plate, as shown in Fig. 2 the first structure of its big plate provided by the embodiment of the present invention
Schematic diagram.Big plate 100 includes multiple array base paltes 1, and array base palte 1 includes many signal lines 30, and each signal line 30 is close
One end at the first edge of array base palte 1 is electrically connected at the first edge of array base palte 1 by first lead 10.
Array base palte 1 also includes at least one contact terminal 40 and a plurality of second lead 20, one end of the second lead 20
Contact terminal 40 is electrically connected to, the other end is electrically connected at the second edge of array base palte 1, and first edge is relative with second edge
If.
Wherein, the second side of the first lead 10 and i+1 array base palte 1 at the first edge of i-th of array base palte 1
The second lead 20 at edge is connected, and the contact terminal on i+1 array base palte is the signal wire 30 on i-th of array base palte 1
Enter horizontal electrical signal test.Wherein, i=1,2,3 ... ..., N-1, N；N is the number for the array base palte that big plate includes.
Array base palte of the prior art test, is the contact terminal in array base palte to the array base with continued reference to Fig. 1
Signal wire in plate carries out electrical testing, therefore, it is necessary to set switch between signal wire and contact terminal, just can guarantee that normal
The input signal of each signal line is different during use, and short circuit does not occur between signal wire.Also, no matter this is contacted
Terminal and switch are arranged on non-display area or viewing area and take certain space, exacerbate the negative of array base palte
Carry, so that the probability of short circuit occur between increasing signal wire.Moreover, not being avoided that switch is damaged in use
And the short circuit problem caused.
However, not being that same array base palte is tested the signal wire of itself, but pass through i-th in the present embodiment
The first lead at the first edge of individual array base palte is connected with the second lead at the second edge of i+1 array base palte,
Electric signal is applied to the contact terminal on i+1 array base palte, so as to carry out electricity to the signal wire in i-th of array base palte
Test.By then passing through the electrical testing that i+1 array base palte is carried out to i-th of array base palte, therefore enter in array substrate
After row cutting, contact terminal is respectively present in from signal wire in different array base paltes, therefore will not during follow-up use
Because one end of signal wire is connected with each other and occurs short circuit, and then opened also without being set between contact terminal and signal wire
Close, so as to effectively release the space in array base palte, increase the spacing between signal wire, reduce hair between signal wire
The probability of raw short circuit.
It should be noted that on the basis of the orientation in Fig. 2, first edge is the top edge of array base palte, second edge
For the lower edge of array base palte, but in fact, the first edge of array base palte may be alternatively located at array base palte left hand edge or
Right hand edge, likewise, the second edge of array base palte may be alternatively located at the right hand edge or left hand edge of array base palte, the present invention is not right
The particular location of first edge and second edge, which is made, to be particularly limited to.Also, as an example, Fig. 2 illustrate only 9 array bases
Plate, in fact, the quantity for the array base palte that big plate is included is far longer than in 9, the present embodiment, the quantity of array substrate is not done
Go out to be particularly limited to.
In a kind of specific embodiment, as shown in figure 3, the second knot of its big plate provided by the embodiment of the present invention
Structure schematic diagram.Array base palte 1 includes the clock cable 302 of a plurality of data lines 301 and at least one.One contact terminal 40 includes
At least one data line terminal 401 and clock signal line terminals 402.Second lead 20 includes the 3rd lead 201 and the 4th
Lead 202.
Wherein, a plurality of first lead 10 of data wire 301 is connected in i-th of array base palte 1 with one positioned at i+1 battle array
The 3rd lead 201 in row substrate is electrically connected, and one end that the 3rd lead 201 is not connected with the first lead 10 is electrically connected to i+1
Data line terminal 401 in individual array base palte 1, data line terminal 401 is used to enter the data wire 301 on i-th of array base palte 1
Row electrical testing.
First lead 10 and an i+1 array base for clock cable 302 is connected in i-th of array base palte 1
The 4th lead 202 on plate 1 is electrically connected, and one end that the 4th lead 202 is not connected with the first lead 10 is electrically connected to i+1 battle array
Clock signal line terminals 402 on row substrate 1, clock signal line terminals 402 are used to believe the clock on i-th of array base palte 1
Number line 302 carries out electrical testing.
Wherein, i=1,2,3 ... ..., N-1, N；N is the number for the array base palte that the big plate includes.
It is understood that because the electric signal of a plurality of data lines can be identical, therefore a plurality of data lines can be connected to
Electrical testing is carried out on one data line terminal, so as to save the quantity of data line terminal, and the sky of array base palte is released
Between.Due to needing that different electric signal tests are carried out to clock cable, therefore each clock cable can be with clock signal
Line terminals are electrically connected correspondingly, to facilitate follow-up electrical testing.
It should be noted that as an example, Fig. 3 illustrate only 6 array base paltes, in fact, the array that big plate is included
The quantity of substrate, which is far longer than in 6, the present embodiment the not quantity of array substrate, to be made and being particularly limited to.
In another feasible embodiment, as shown in figure 4, the of its big plate provided by the embodiment of the present invention
Three structural representations.The present embodiment can be electrically connected signal wire by lead with contact terminal, can also be in lead with contacting
Circuit board terminals are set between terminal.Fig. 4 is on the basis of Fig. 3, by the specific connected mode and work of circuit board terminals
The explanation carried out as mode：Array base palte 1 also includes being provided with flexible PCB (being not shown), the flexible PCB
Multiple circuit board terminals 51.Each first lead 10 is electrically connected to the first of array base palte 1 by a circuit board terminals 51
Edge.The first lead and the company of the second lead, data line terminal and clock signal line terminals by circuit board terminals 51
Connect relation and working method refer to above-mentioned corresponding part, will not be repeated here.
It should be noted that as an example, Fig. 4 illustrate only 6 array base paltes, each array base palte includes 10 circuits
Plate terminal, in fact, the quantity of the circuit board terminals included on array base palte is far longer than in 10, the present embodiment not to circuit
The quantity of plate terminal is particularly limited.
Due to above-mentioned array base palte, color membrane substrates and liquid crystal are constituted after display panel (namely by the battle array on big plate
After row substrate is cut), the electric signal of each data line is required to be connected to drive end by the circuit board terminals of response.
With continued reference in Fig. 2, Fig. 3 and Fig. 4, dotted line represents the line of cut on short side direction, big plate is cut into many
After individual array base palte, so as to regard as, after the completion of cutting, contact terminal is stayed in an array base palte, connection signal wire
A plurality of first lead is in another array base palte, also, one end that the first lead is not connected with signal wire does not have mutually
Short circuit together, therefore does not interfere with the follow-up electric signals different to the application of each signal line.It is specific real at another
Apply in mode, with continued reference to Fig. 4, circuit board terminals 51, contact terminal 40, the first lead 10 and the second lead 20 are respectively positioned on battle array
In the non-display area 3 of row substrate 1.Due in viewing area, there is more signal wire, by contact terminal, first
Lead and the second lead are arranged at non-display area, can effectively discharge in the space of viewing area, increase viewing area
Spacing between signal wire, it is to avoid occur short circuit phenomenon between the signal wire in viewing area.
In another embodiment, as shown in figure 5, the first of its array base palte provided by the embodiment of the present invention
Structural representation.Connected between the contact terminal 40 in array basal plate 1 by resistance 50.
Due in the preparation process of array base palte, inevitably there is electrostatic, electrostatic now can cause thin oxygen
Change layer breakdown, cause Leakage Current, the scorification of device can be also caused when serious.Therefore, will by resistance 50 in the present embodiment
Two adjacent contact terminals 40 are connected, now, the formation electrostatic impedor of resistance 50, play a part of eliminating electrostatic.
Further, the Standard resistance range of resistance is more than or equal to 180K Ω, and less than or equal to 220K Ω.This reality
Apply example preferred, the resistance of resistance is 200K Ω.Larger resistance, not only forms electrostatic impedor, eliminates electrostatic, can also prevent
Short circuit occurs between contact terminal.
Certainly, the material for making resistance has many kinds, exemplary, and the present embodiment is preferred, and the material of resistance is polycrystalline
Silicon.
In a kind of feasible embodiment, arrangement mode of the array base 1 on big plate 100 can have a variety of, this implementation
Example is preferred, and with continued reference to Fig. 2, the array of array base palte 1 is arranged on big plate 100.Array base palte array is arranged in greatly
On plate, the utilization rate of big plate can be improved.
The present embodiment provides a kind of array base palte, as shown in fig. 6, its array base palte provided by the embodiment of the present invention
Second structural representation.The array base palte 1 includes many signal lines 30, and each signal line 30 is close to the first of array base palte 1
One end of edge is connected at the first edge of array base palte 1 by first lead 10.
Also, the array base palte 1 also includes at least one contact terminal 40 and a plurality of second lead 20；Second lead 20
One end be connected to contact terminal 40, the other end is connected at the second edge of array base palte 1.First edge and second edge phase
To setting.
It should be noted that the signal wire in array substrate enters horizontal electrical signal test, it is to be cut in array substrate
The array base palte test (Array Test) carried out before is cut, specific array base palte test process is referring to above-mentioned big plate, herein
Repeat no more.
Array base palte test of the prior art, with continued reference to Fig. 1, it is necessary to set and open between signal wire and contact terminal
Close, just can guarantee that the input signal of each signal line during normal use is different, and short circuit does not occur between signal wire.
Also, no matter this contact terminal and switch are arranged on non-display area or viewing area and take certain space, plus
The acute load in space, so that the probability of short circuit occur between increasing signal wire.Moreover, not being avoided that in use
Switch the short circuit problem for being damaged and causing.However, passing through at the first edge of i-th of array base palte in the present embodiment
One lead is connected with the second lead at the second edge of i+1 array base palte, to the contact jaw on i+1 array base palte
Son applies electric signal, so as to carry out electrical testing to the signal wire in i-th of array base palte.By then passing through i+1 array
The electrical testing that substrate is carried out to i-th of array base palte, therefore after array substrate is cut, contact terminal and signal wire point
It is not present in different array base paltes, therefore will not be connected with each other and send out because of one end of signal wire during follow-up use
Raw short circuit, and then switched also without being set between contact terminal and signal wire, so as to effectively release in array base palte
Space, increase the spacing between signal wire, reduce the probability that short circuit occurs between signal wire.
It should be noted that as an example, the array base palte shown in Fig. 6 only shows 3 signal lines, 3 the first leads, 3
Individual contact terminal and 3 the second leads, in fact, signal wire, the first lead, contact terminal and second are drawn on array base palte
The quantity of line is far longer than signal wire, the first lead, contact terminal and second in 3, array substrate of the embodiment of the present invention
The quantity of lead is not specially limited.Also, on the basis of the orientation in Fig. 2, first edge is the top edge of array base palte, the
Two edges are the lower edge of array base palte, but in fact, the first edge of array base palte may be alternatively located at the left side of array base palte
Edge or right hand edge, likewise, the second edge of array base palte may be alternatively located at the right hand edge or left hand edge of array base palte, this hair
Bright do not made to the particular location of first edge and second edge is particularly limited to.
In a kind of more specifically embodiment, as shown in fig. 7, its array base palte for being provided by the embodiment of the present invention
The 3rd structural representation.Many signal lines 30 include the clock cable 302 of a plurality of data lines 301 and at least one.One connects
Contravention 40 includes clock signal line terminals 402 and at least one data line terminal 401；Second lead 20 includes the 3rd lead
201 and the 4th lead 202.
A plurality of first lead 10 of connection data wire 301 is connected with one article of the 3rd lead 201, and the 3rd lead 201 is not with the
One end of one lead 10 connection is connected to data line terminal 401.
One article of first lead 10 of connection clock cable 302 is connected with one article of the 4th lead 202, and the 4th lead 202 is not
The one end being connected with the first lead 10 is connected to clock signal line terminals 402.
It is understood that according to above-mentioned annexation, when applying electric signal to data line terminal, so as to data
Line enters horizontal electrical signal test.When applying electric signal to clock signal terminal, surveyed so as to enter horizontal electrical signal to clock cable
Examination.
Because the electric signal of a plurality of data lines can be identical, therefore a plurality of data lines can be connected to same number according to line terminals
Upper carry out electrical testing, so as to save the quantity of data line terminal, and releases the space of array base palte.Due to when needing pair
Clock signal wire carries out different electric signal tests, therefore each clock cable can be one-to-one with clock signal line terminals
Electrical connection, to facilitate follow-up electrical testing.
It should be noted that as an example, the array base palte shown in Fig. 7 only shows 3 data lines, 5 the first leads, 2
Bar clock cable, 1 data line terminal, 2 clock signal line terminals, 3 article of the 3rd lead and 2 article of the 4th lead are actual
On, the quantity of data wire and the 3rd lead is much larger than 3 on array base palte, and the quantity of the first lead is much larger than 5, clock signal
The quantity of line, the 4th lead and clock signal line terminals is much larger than 2, and the quantity of data line terminal is much larger than 1, and the present invention is implemented
Data wire, the first lead, the 3rd lead, the 4th lead, clock cable, data wire, data line terminal in example array substrate
And the quantity of clock signal line terminals is not specially limited.
In another embodiment, in the present embodiment, signal wire can be connected on contact terminal by lead,
Circuit board terminals can also be set between lead and contact terminal, the specific connected modes of the circuit board terminals as shown in figure 8,
4th structural representation of its array base palte provided by the embodiment of the present invention.Array base palte also includes flexible PCB, soft
Multiple circuit board terminals 51 are provided with property circuit board, each first lead 10 is connected to battle array by a circuit board terminals 51
At the first edge of row substrate.
It should be noted that as an example, Fig. 8 illustrate only 5 circuit board terminals, in fact, being wrapped on array base palte
The quantity that the quantity of the circuit board terminals contained is far longer than in 5, the present embodiment not to circuit board terminals is particularly limited.
Due to above-mentioned array base palte, color membrane substrates and liquid crystal are constituted after display panel (namely by the battle array on big plate
After row substrate is cut), the electric signal of each data line is required to be connected to drive end by the circuit board terminals of response.
In another embodiment, as shown in figure 9, it is the 5th of the array base palte of the invention in real time that example is provided
Structural representation.Circuit board terminals 51, contact terminal 40, the first lead 10 and the second lead 20 are arranged at array base palte
In non-display area 3.
It is understood that in fig .9, the region filled is viewing area 2, it is non-aobvious around viewing area 2
Show region 3.It is due in viewing area, there is more signal wire, contact terminal, the first lead and the second lead is equal
Non-display area is arranged on, the spacing between the signal wire in the space of viewing area, increase viewing area can be effectively discharged,
Avoid occurring short circuit phenomenon between the signal wire in viewing area.
In another embodiment, with continued reference to shown in Fig. 5, between the contact terminal 40 in array basal plate 1
Connected by resistance 50.
Due in the preparation process of array base palte, inevitably producing electrostatic, cause thin oxide layer breakdown, enter
And Leakage Current, the scorification of device can be also caused when serious.Therefore, adjacent two are contacted by resistance 50 in the present embodiment
Terminal 40 is connected, now, the formation electrostatic impedor of resistance 50, plays a part of eliminating electrostatic.
Further, the Standard resistance range of resistance is more than or equal to 180K Ω, and less than or equal to 220K Ω.This reality
Apply example preferred, the resistance of resistance is 200K Ω.Larger resistance, not only forms electrostatic impedor, eliminates electrostatic, can also prevent
Short circuit occurs between contact terminal.
Certainly, the material for making resistance has many kinds, exemplary, and the material of the preferred resistance of the present embodiment is polycrystalline
Silicon.
As shown in Figure 10, the structural representation of its touch-control display panel provided by the embodiment of the present invention.The touch-control shows
Show that panel also includes liquid crystal display panel, liquid crystal display panel includes the array base palte 21 and color membrane substrates 22 being oppositely arranged, with
And the liquid crystal layer 23 between array base palte 21 and color membrane substrates 22.
In the display panel that the present embodiment is provided, array base palte test is completed not in same display panel, because
This simultaneously need not set switch between signal wire and contact terminal, so as to effectively release the space in display panel, increase
Spacing between big signal wire, reduces between signal wire and occurs the probability of short circuit.Also, will not during follow-up use
Short circuit between signal wire is caused because of the damage of switch.
As shown in figure 11, the exemplary plot of the display device provided by the embodiment of the present invention.The display device 500 includes upper
State touch-control display panel 100.
In the display device that the present embodiment is provided, array base palte test is completed not in same display device, because
This simultaneously need not set switch between signal wire and contact terminal, so as to effectively release the space in display panel, increase
Spacing between big signal wire, reduces between signal wire and occurs the probability of short circuit.Also, will not during follow-up use
Short circuit between signal wire is caused because of the damage of switch.
It should be noted that Figure 11 using mobile phone as display device exemplified by carry out example, but display device is not limited to
Mobile phone, specifically, the display device can include but is not limited to personal computer (Personal Computer, PC), individual number
Word assistant (Personal Digital Assistant, PDA), radio hand-held equipment, tablet personal computer (Tablet
Computer), any electronic equipment with display function such as MP4 players or television set.
The present embodiment provides a kind of method of testing, and method of testing is applied to the big plate involved by the present embodiment.Wherein,
The first lead at the first edge of i array base palte is connected with the second lead at the second edge of i+1 array base palte.
The method of testing includes：
Electric signal is applied to the contact terminal on i+1 array base palte, for the signal wire in i-th of array base palte
Carry out electrical testing.
Big plate is cut, multiple independent array base paltes are formed.
Wherein, i=1,2,3 ... ..., N-1, N；N is the number for the array base palte that the big plate includes.
By method of testing, signal wire that can be in array substrate carries out electrical testing, so as to find electric signal transmission in time
Bad signal wire.Also, the method for testing in the present embodiment, due to not being that array base palte enters horizontal electrical signal to the signal of itself
Test, but horizontal electrical signal is entered to the signal wire in adjacent array base palte by another array base palte and tested, therefore,
After the completion of cutting, it can't be switched being set between signal wire and contact terminal, so as to effectively save array base palte
Usable floor area, and in the array base palte during follow-up use, the damage that will not therefore switch and cause signal wire each other
Between short circuit.
It is apparent to those skilled in the art that, for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, may be referred to the corresponding process in preceding method embodiment, will not be repeated here.
In several embodiments provided by the present invention, it should be understood that disclosed system, apparatus and method can be with
Realize by another way.For example, device embodiment described above is only schematical, for example, the unit
Divide, only a kind of division of logic function there can be other dividing mode when actually realizing, for example, multiple units or group
Part can combine or be desirably integrated into another system, or some features can be ignored, or not perform.It is another, it is shown
Or the coupling each other discussed or direct-coupling or communication connection can be by some interfaces, device or unit it is indirect
Coupling is communicated to connect, and can be electrical, machinery or other forms.
The unit illustrated as separating component can be or may not be it is physically separate, it is aobvious as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple
On NE.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
In addition, each functional unit in each embodiment of the invention can be integrated in a processing unit, can also
That unit is individually physically present, can also two or more units it is integrated in a unit.Above-mentioned integrated list
Member can both be realized in the form of hardware, it would however also be possible to employ hardware adds the form of SFU software functional unit to realize.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (20)
1. a kind of array base palte, it is characterised in that the array base palte includes many signal lines, each signal wire is close
One end at the first edge of the array base palte is connected at the first edge of the array base palte by first lead；
The array base palte also includes at least one contact terminal and a plurality of second lead；One end connection of second lead
To the contact terminal, the other end is connected at the second edge of the array base palte；The first edge and second side
Edge is oppositely arranged.
2. array base palte according to claim 1, it is characterised in that the array base palte also includes flexible PCB, institute
State and multiple circuit board terminals are provided with flexible PCB；
Each first lead is connected at the first edge of the array base palte by the circuit board terminals.
3. array base palte according to claim 2, it is characterised in that the signal wire includes a plurality of data lines and at least one
Bar clock cable；
One contact terminal includes clock signal line terminals and at least one data line terminal；Second lead includes
3rd lead and the 4th lead；
A plurality of first lead for connecting the data wire is connected with one article of the 3rd lead, and the 3rd lead does not connect with the first lead
The one end connect is connected to the data line terminal；
One article of first lead of connection clock cable is connected with one article of the 4th lead, and the 4th lead does not connect with the first lead
The one end connect is connected to the clock signal line terminals.
4. array base palte according to claim 3, it is characterised in that the flexible PCB, the contact terminal, described
First lead and second lead are respectively positioned in the non-display area of the array base palte.
5. array base palte according to claim 1, it is characterised in that between the contact terminal in array basal plate
Connected by resistance.
6. array base palte according to claim 5, it is characterised in that the Standard resistance range of the resistance be more than or equal to
180K Ω, and less than or equal to 220K Ω.
7. array base palte according to claim 6, it is characterised in that the resistance of the resistance is 200K Ω.
8. the array base palte according to any one of claim 5~7, it is characterised in that the material of the resistance is polysilicon.
9. a kind of display panel, it is characterised in that the display panel includes the array as described in any one of claim 1~8
Substrate, and the color membrane substrates being oppositely arranged with array base palte；The display panel also include be arranged on the array base palte and
Liquid crystal layer between the color membrane substrates.
10. a kind of display device, it is characterised in that the display device includes display panel as claimed in claim 9.
11. a kind of big plate, it is characterised in that the big plate includes multiple array base paltes, the array base palte includes many bars
Line, the one end of each signal wire at the first edge of the array base palte is connected to institute by first lead
State at the first edge of array base palte；
The array base palte also includes at least one contact terminal and a plurality of second lead；One end connection of second lead
To the contact terminal, the other end is connected at the second edge of the array base palte；The first edge and second side
Edge is oppositely arranged；
Wherein, the at the second edge of the first lead at the first edge of i-th of array base palte and i+1 array base palte
Two leads are connected, and the contact terminal on the i+1 array base palte carries out electricity for the signal wire on i-th of array base palte
Signal testing；
Wherein, i=1,2,3 ... ..., N-1, N；N is the number for the array base palte that the big plate includes.
12. big plate according to claim 11, it is characterised in that the array base palte also includes flexible PCB, described
Multiple circuit board terminals are provided with flexible PCB；
Each first lead is connected at the first edge of the array base palte by the circuit board terminals.
13. big plate according to claim 12, it is characterised in that signal wire includes a plurality of data lines and at least one clock
Signal wire；
One contact terminal includes at least one data line terminal and clock signal line terminals；Second lead includes the 3rd lead
And the 4th lead；
Wherein, a plurality of first lead of data wire is connected in i-th of array base palte with one in the i+1 array base palte
3rd lead is connected, and one end that the 3rd lead is not connected with the first lead is connected in the i+1 array base palte
Data line terminal, the data line terminal is used to carry out electrical testing to the data wire on i-th of array base palte；
The 4th on one article of first lead and one article of i+1 array base palte of clock cable is connected in i-th of array base palte
Lead is connected, and one end that the 4th lead is not connected with the first lead is connected to the clock on i+1 array base palte
Signal line terminals, the clock signal line terminals are used to carry out electrical testing to the clock cable on i-th of array base palte；
Wherein, i=1,2,3 ... ..., N-1, N；N is the number for the array base palte that the big plate includes.
14. big plate according to claim 12, it is characterised in that the flexible PCB, the contact terminal, described
One lead and second lead are respectively positioned in the non-display area of the array base palte.
15. big plate according to claim 11, it is characterised in that lead to between the contact terminal in array basal plate
Cross resistance connection.
16. big plate according to claim 15, it is characterised in that the Standard resistance range of the resistance be more than or equal to
180K Ω, and less than or equal to 220K Ω.
17. big plate according to claim 16, it is characterised in that the resistance of the resistance is 200K Ω.
18. the array base palte according to any one of claim 15~17, it is characterised in that the material of the resistance is polycrystalline
Silicon.
19. the big plate according to any one of claim 11~14, it is characterised in that the array base palte array is arranged in
On the big plate.
20. a kind of method of testing, it is characterised in that the method for testing is applied to described in any one of the claims 10~17
Big plate；Wherein, at the second edge of the first lead at the first edge of i-th of array base palte and i+1 array base palte
The second lead be connected；
The method of testing includes：
Electric signal is applied to the contact terminal on the i+1 array base palte, for the signal wire in i-th of array base palte
Carry out electrical testing；
Big plate is cut, multiple independent array base paltes are formed；
Wherein, i=1,2,3 ... ..., N-1, N；N is the number for the array base palte that the big plate includes.
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| CN201710453586.0A CN107065364A (en) | 2017-06-15 | 2017-06-15 | Array base palte, display panel, display device, big plate and method of testing |
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| CN201710453586.0A CN107065364A (en) | 2017-06-15 | 2017-06-15 | Array base palte, display panel, display device, big plate and method of testing |
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Application publication date: 20170818 |