CN108877616A - A kind of test method and display panel of array substrate driving circuit - Google Patents
A kind of test method and display panel of array substrate driving circuit Download PDFInfo
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- CN108877616A CN108877616A CN201810933627.0A CN201810933627A CN108877616A CN 108877616 A CN108877616 A CN 108877616A CN 201810933627 A CN201810933627 A CN 201810933627A CN 108877616 A CN108877616 A CN 108877616A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
This application discloses the test methods and display panel of a kind of array substrate driving circuit, this method includes by from one drive signal line of a connection in a plurality of test signal wire drawn in the calibrating terminal of array substrate, to calibrating terminal input signal to test；Disconnect the connection of the test signal wire and drive signal line tested recently；Another test signal wire is connected into another drive signal line, to calibrating terminal input signal to test；The step of connection for disconnecting the test signal wire and drive signal line tested recently is returned to, until test is completed.By the above-mentioned means, the application can complete the test of driving circuit with less than the calibrating terminal of drive signal line quantity, calibrating terminal and production cost are saved.
Description
Technical field
This application involves field of display technology, and in particular to a kind of test method and display surface of array substrate driving circuit
Plate.
Background technique
Array gate driving (Gate-driver On Array, GOA) technology has been widely used for display panel at present
In, GOA technology can save the cost of grid integrated circuits, can also reduce the width of display floater frame, to current trend
Narrow frame design it is highly beneficial, GOA is an important technology of following display panel design.
Present inventor has found that existing GOA product realizes that the output of scanning signal needs multiple groups in long-term R & D
Signal and circuit are completed jointly；Since the output of scanning signal needs multiple groups GOA signal, so that in array substrate processing procedure
Inspection process needs to increase multiple calibrating terminals to be detected to display panel offer input signal；But with to production
The requirement of product is higher and higher, and GOA signal gradually increases, so that array substrate test needs to design multiple groups calibrating terminal, board is surveyed
The pin for trying jig increases, to greatly increase the cost of array substrate test fixture.
Summary of the invention
The application mainly solves the problems, such as the test method and display panel that are to provide a kind of array substrate driving circuit, energy
Enough calibrating terminals with less than drive signal line quantity complete the test of driving circuit, save calibrating terminal and are produced into
This.
In order to solve the above technical problems, the application is the technical solution adopted is that provide a kind of survey of array substrate driving circuit
Method for testing, this method include：One will be connected from one in a plurality of test signal wire drawn in the calibrating terminal of array substrate
Drive signal line, to calibrating terminal input signal to test；It disconnects the test signal wire tested recently and driving is believed
The connection of number line；Another test signal wire is connected into another drive signal line, to calibrating terminal input signal to survey
Examination；The step of connection for disconnecting the test signal wire and drive signal line tested recently is returned to, until test is completed.
In order to solve the above technical problems, another technical solution that the application uses is to provide a kind of display panel, the display
Panel includes：Substrate, pixel circuit, several drive signal lines and several test signal wires；It is aobvious that pixel circuit is located at substrate side
Show region；Drive signal line is located on the substrate ipsilateral with pixel circuit, and the non-display area of self-reference substrate periphery extend to it is aobvious
Show region, drive signal line is connect with pixel circuit；Test signal wire is located on the substrate ipsilateral with pixel circuit, every test
Signal wire is designed to connect with a drive signal line to test pixel circuit；Wherein, at least one test letter
Connection structure number between line and drive signal line is welding structure, and/or at least one test signal wire and driving signal
Exist between line and blows or cut off structure.
Through the above scheme, the beneficial effect of the application is：The calibrating terminal of array substrate and a plurality of test in the application
Signal wire connection, first by one drive signal line of a connection in a plurality of test signal wire being connect with calibrating terminal, benefit
With external testing probe to calibrating terminal input signal to test；Then it repeats：The test tested recently is believed
Connection number between line and drive signal line disconnects, and another test signal wire is connected another drive signal line, to survey
Operation of the terminal input signal to be tested is tried, until test is completed；Pass through the test with less than drive signal line quantity
Terminal completes the test of driving circuit, saves calibrating terminal and production cost.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein：
Fig. 1 is the connection schematic diagram of signal wire and calibrating terminal in the prior art；
Fig. 2 is the flow diagram of the test method first embodiment of array substrate driving circuit provided by the present application；
Fig. 3 is the connection schematic diagram of step 21 corresponding drive signal line and calibrating terminal in Fig. 2；
Fig. 4 is the connection schematic diagram of step 22 and step 23 corresponding drive signal line and calibrating terminal in Fig. 2；
Fig. 5 is the flow diagram of the test method second embodiment of array substrate driving circuit provided by the present application；
Fig. 6 be array substrate driving circuit provided by the present application test method second embodiment in carry out high vertical arrangement
The connection schematic diagram of drive signal line and calibrating terminal when curing process；
Fig. 7 is high vertical arrangement solidification in the test method second embodiment of array substrate driving circuit provided by the present application
The connection schematic diagram of drive signal line and calibrating terminal after the completion of processing procedure；
Fig. 8 is the flow diagram of the test method 3rd embodiment of array substrate driving circuit provided by the present application；
Fig. 9 is the connection schematic diagram of step 81 corresponding drive signal line and calibrating terminal in Fig. 8；
Figure 10 is driving signal timing in the test method 3rd embodiment of array substrate driving circuit provided by the present application
Figure；
Figure 11 is the connection schematic diagram of step 82 and step 83 corresponding drive signal line and calibrating terminal in Fig. 8；
Figure 12 is the flow diagram of the test method fourth embodiment of array substrate driving circuit provided by the present application；
Figure 13 is the connection schematic diagram of step 121 corresponding drive signal line and calibrating terminal in Figure 12；
Figure 14 is the connection schematic diagram of step 122 and step 123 corresponding drive signal line and calibrating terminal in Figure 12；
Figure 15 is the structural schematic diagram of an embodiment of display panel provided by the present application；
Figure 16 is another structural schematic diagram of display panel in an embodiment of display panel provided by the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall in the protection scope of this application.
As shown in Figure 1, existing product array substrate test signal mainly include data-signal (Blue, Green and
Red), GOA signal and common signal (ACOM and CFCOM)；GOA signal mainly includes the clock signal of multiple groups high frequency；VSS is low
The direct current signal of current potential, LC1 and LC2 are one group of low-frequency ac signals, they are input source signal, under the action of GOA circuit
Realize the output of scanning signal；In order to improve the charging ability of grid, increase the ability that resumes of grid, clock signal gradually increases
Add, 4CK (Clock, clock), 6CK, 8CK or 12CK etc. are become by 2CK, the number of array substrate calibrating terminal is caused gradually to increase
Add；By taking 6CK as an example, calibrating terminal is at least 16, and this requires the test fixture numbers of array substrate to increase, and considerably increases
Cost.
It is the test method first embodiment of array substrate driving circuit provided by the present application refering to Fig. 2 and Fig. 3, Fig. 2
Flow diagram, this method include：
Step 21：One will be connected from one in a plurality of test signal wire 32 drawn in the calibrating terminal 31 of array substrate
Drive signal line 33, to 31 input signal of calibrating terminal to test.
Drive signal line 33 can be clock cable, and driving circuit can be GOA circuit 34；As shown in figure 3, clock is believed
Number line has four (CK1, CK2, CK3 and CK4), in order to save calibrating terminal 31, a plurality of test signal wire 32 is connected to same
On calibrating terminal 31, when testing, by test signal wire 32 in wherein one connect with drive signal line 33 (CK1).
Drive signal line 33 connects GOA circuit 34, and external tester probe 35 is connect with to GOA circuit 34 with calibrating terminal 31
Desired signal is inputted, so that the output scanning signal in GOA circuit 34, display panel is lighted, and by analysis shows that face
The picture of plate detects bad position.
Step 22：Disconnect the connection of the test signal wire 32 and drive signal line 33 tested recently.
Since a plurality of test signal wire 32 is connected on same calibrating terminal 31, connect in another drive signal line 33 of test
When whether the GOA circuit 34 connect works normally, need the test signal wire 32 tested recently and drive signal line 33 first
Connection disconnects, to avoid retest.
Step 23：Another test signal wire 32 is connected into another drive signal line 33, calibrating terminal 31 is inputted and is believed
Number to be tested.
After disconnecting the connection between the test signal wire 32 tested recently and drive signal line 33, such as Fig. 4 institute
Show, another test signal wire 32 is connected into another drive signal line 33 (CK2), then utilizes external 35 pairs of tester probe surveys
31 input signal of terminal is tried to be tested.
Step 24：The step of connection for disconnecting the test signal wire 32 and drive signal line 33 tested recently is returned to, directly
It is completed to test.
In order to complete to repeat step 22 and step 23 to the test of all GOA circuits 34, until test is completed.
It is different from the prior art, present embodiments provides a kind of test method of array substrate driving circuit, array substrate
Calibrating terminal 31 connect with a plurality of test signal wire 32, first will be in a plurality of test signal wire 32 that connect with calibrating terminal 31
One drive signal line 33 of a connection, using external testing probe 35 to 31 input signal of calibrating terminal to test；
Then it repeats：Connection between the test signal wire 32 tested recently and drive signal line 33 is disconnected, and will be another
Item test signal wire 32 connects another drive signal line 33, the operation to 31 input signal of calibrating terminal to be tested, directly
It is completed to test；By completing the test of driving circuit with less than the calibrating terminal 31 of 33 quantity of drive signal line, save
Calibrating terminal 31 and production cost.
It is the test method second embodiment of array substrate driving circuit provided by the present application refering to Fig. 5 to Fig. 7, Fig. 5
Flow diagram, this method include：
Step 51：One will be connected from one in a plurality of test signal wire 62 drawn in the calibrating terminal 61 of array substrate
Drive signal line 63, to 61 input signal of calibrating terminal to test.
Step 52：Disconnect the connection of the test signal wire 62 and drive signal line 63 tested recently.
Step 53：Another test signal wire 62 is connected into another drive signal line 63, calibrating terminal 61 is inputted and is believed
Number to be tested.
Step 54：The step of connection for disconnecting the test signal wire 62 and drive signal line 63 tested recently is returned to, directly
It is completed to test.
Wherein, step 51-54 is similar with step 11-14 in first embodiment, and details are not described herein.
The quantity of calibrating terminal 61 is to be at least 2, and the quantity of test signal wire 62 is equal to the quantity of drive signal line 63；It surveys
It is provided with circuit breakpoint on trial signal line 62, welding point 64 is preset on circuit breakpoint, as shown in fig. 6, passing through welding circuit
Welding point 64 on breakpoint will test signal wire 62 and drive signal line 63 connects；It can use on laser welding circuit breakpoint
Welding point 64 so that drive signal line 63 and test signal wire 62 connect, formed access.
Step 55：After the completion of test, a plurality of test signal wire 62 that will be drawn from the calibrating terminal 61 of array substrate
In the whole drive signal line 63 of a connection, to carry out high vertical arrangement curing process.
After completing to the test of GOA circuit 65, a plurality of test drawn from the calibrating terminal 61 of array substrate is believed
The whole drive signal line 63 of a connection in number line 62, to carry out high vertical arrangement solidification (High Vertical
Alignment Curing, HVA) processing procedure；In shown in Fig. 6 by Article 4 test signal wire 62 and all drive signal lines 63 into
Connection is gone, remaining test signal wire 62 is disconnected with drive signal line 63.
Step 56：After high vertical arrangement curing process is completed, test signal wire 62 and drive signal line 63 are disconnected
Connection.
As shown in fig. 7, test signal wire 62 after completing HVA processing procedure and the connection of drive signal line 63 is disconnected, with
Display panel to sell rear drive signal line to work normally.
It is different from the prior art, a kind of test method of array substrate driving circuit is present embodiments provided, by battle array
A plurality of test signal wire 62, and the setting welding point 64 on test signal wire 62 is arranged in the calibrating terminal 61 of column substrate, right
When the GOA circuit 65 that different drive signal lines 63 connects is tested, to test by the welding point 64 for welding different
Signal wire 62 is connect with drive signal line 63, improves the utilization rate of calibrating terminal 61, is saved calibrating terminal 61 and is produced into
This.
It is the test method 3rd embodiment of array substrate driving circuit provided by the present application refering to Fig. 8 to Figure 11, Fig. 8
Flow diagram, this method include：
Step 81：Draw in first calibrating terminal 91 first test signal wire is connected into the first drive signal line, and will
The 4th test signal wire connection fourth drive signal line drawn in second calibrating terminal 92, respectively to 91 He of the first calibrating terminal
Second calibrating terminal, 92 input signal is to be tested.
The signal S2 current potential of the second calibrating terminal 92 of signal S1 and input of the first calibrating terminal 91 is inputted on the contrary, such as Figure 10
It is shown；The the first test signal wire drawn in first calibrating terminal 91 is connect with the first drive signal line, the second calibrating terminal 92
4th test signal wire of middle extraction is connect with fourth drive signal line, is utilized respectively external tester probe 93 to the first test lead
Son 91 and 92 input signal of the second calibrating terminal are to be tested, as shown in Figure 9.
Step 82：The connection for the first the test signal wire and the first drive signal line tested is disconnected, and disconnects and testing
The 4th test signal wire and fourth drive signal line connection.
Step 83：Draw in first calibrating terminal 91 second test signal wire is connected into the second drive signal line, and will
The 5th test signal wire drawn in second calibrating terminal 92 connects the 5th drive signal line, respectively to 91 He of the first calibrating terminal
Second calibrating terminal, 92 input signal is to be tested.
After the GOA circuit test for completing to connect the first drive signal line with fourth drive signal line, by the first test
The connection of signal wire and the first drive signal line disconnects, and the connection of the 4th test signal wire and fourth drive signal line is broken
It opens, as shown in figure 11；The second test signal wire is connect with the second drive signal line again, and tests signal wire and the 5th for the 5th
Drive signal line connection, then respectively input signal into the first calibrating terminal 91 and the second calibrating terminal 92.
Step 84：The connection for the second the test signal wire and the second drive signal line tested is disconnected, and disconnects and testing
The 5th test signal wire and the 5th drive signal line connection.
Step 85：It repeats the above steps, until testing all drive signal lines.
After the GOA circuit test for completing to connect the second drive signal line and the 5th drive signal line, by the second test
The connection of signal wire and the second drive signal line disconnects, and the connection of the 5th test signal wire and the 5th drive signal line is broken
It opens；Then step 81-84 is repeated, until testing all drive signal lines.
It is different from the prior art, a kind of test method of array substrate driving circuit is present embodiments provided, by every
A plurality of test signal wire is connected on a calibrating terminal, when testing, the test signal that will first be connected in each calibrating terminal
One in line connect with a drive signal line, and after the completion of test, between cutting test signal wire and drive signal line
Connection, realize recycling calibrating terminal, improve the utilization rate of calibrating terminal, completed pair using less calibrating terminal
The test of GOA circuit, saves calibrating terminal and production cost.
2 and Figure 14 refering to fig. 1, Figure 12 are the test method fourth embodiments of array substrate driving circuit provided by the present application
Flow diagram, this method includes：
Step 121：Draw in calibrating terminal 131 first test signal wire is connected into the first drive signal line, and will be surveyed
The the first test signal wire drawn in examination terminal 131 connects fourth drive signal line by phase inverter 132, to calibrating terminal 131
Input signal is to be tested.
The the first test signal wire drawn in calibrating terminal 131 is connect with the first drive signal line, and the first test is believed
Number line is connected to fourth drive signal line by phase inverter 132, then defeated to calibrating terminal 131 using external tester probe 133
Enter signal to be tested, as shown in figure 13.
Step 122：The connection for the first the test signal wire and the first drive signal line tested is disconnected, and disconnects and testing
First test signal wire and fourth drive signal line connection.
Step 123：Draw in calibrating terminal 131 second test signal wire is connected into the second drive signal line, and will be surveyed
The the second test signal wire drawn in examination terminal 131 connects the 5th drive signal line by phase inverter 132, to calibrating terminal 131
Input signal is to be tested.
After the GOA circuit test for completing to connect the first drive signal line with fourth drive signal line, respectively by first
The connection for testing signal wire and the first drive signal line and fourth drive signal line disconnects, as shown in figure 14；Again by the second test
Signal wire is connect with the second drive signal line, and the second test signal wire is connected by phase inverter 132 and the 5th drive signal line
It connects, then using external 133 input signal of tester probe into calibrating terminal 131.
Step 124：The connection for the second the test signal wire and the second drive signal line tested is disconnected, and disconnects and testing
Second test signal wire and the 5th drive signal line connection.
Step 125：It repeats the above steps, until testing all drive signal lines.
After the GOA circuit test for completing to connect the second drive signal line and the 5th drive signal line, respectively by second
The connection for testing signal wire and the second drive signal line and the 5th drive signal line disconnects；Then step 121-124 is repeated,
Until testing all drive signal lines.
It is different from the prior art, present embodiments provides a kind of test method of array substrate driving circuit, driven
When the test of dynamic circuit, first one in the test signal wire connected in calibrating terminal 131 is connect with a drive signal line,
Another drive signal line is connected by phase inverter simultaneously, and after the completion of test, cutting test signal wire and drive signal line
Between connection, realize recycling calibrating terminal 131, improve the utilization rate of calibrating terminal 131, save calibrating terminal
131 and production cost.
5 and Figure 16 refering to fig. 1, Figure 15 are the structural schematic diagram of one embodiment of display panel provided by the present application, the display
Panel includes：Substrate 151, pixel circuit 152, several drive signal lines 153 and several test signal wires 154.
Substrate 151 is array substrate, and pixel circuit 152 is located at the display area 1511 of 151 side of substrate；Drive signal line
153 are located on the substrate 151 ipsilateral with pixel circuit 151, and the non-display area 1512 of 151 periphery of self-reference substrate extends to display
Region 1511, drive signal line 153 are connect with pixel circuit 152.
Test signal wire 154 is located on the substrate 151 ipsilateral with pixel circuit 152, and every test signal wire 154 is designed
To connect with a drive signal line 153 to test pixel circuit 152.
Wherein, the connection structure between at least one test signal wire 154 and drive signal line 153 is welding structure,
And/or exists between at least one test signal wire 154 and drive signal line 153 and blow or cut off structure.
Further, display panel further includes two calibrating terminals 155, and each calibrating terminal 155 connects a plurality of test letter
Number line 154, every test signal wire 154 connect a drive signal line 153, and each calibrating terminal 155 is with external jig (in figure
It is not shown) it connects with input signal into test signal wire 154, as shown in figure 15.
In addition, display panel can also only include a calibrating terminal 155, calibrating terminal 155 connects a plurality of test signal wire
154, and every test signal wire 154 connects two drive signal lines 153, calibrating terminal 155 is connect with external jig to input
Signal is into test signal wire 154, as shown in figure 16.
Wherein, exist between at least one test signal wire 154 and all drive signal lines 153 and blow or cut off knot
Structure, to prevent test signal wire 154 to be connected to all drive signal lines 153, so that 153 short circuit of drive signal line.
It is different from the prior art, display panel provided in this embodiment, by utilizing less 155 terminal of test can be real
Now to the test of pixel circuit 152, the space that calibrating terminal 155 occupies display panel is reduced, reduces non-display area 1512
Area, be conducive to raising display panel accounts for screen ratio, can also save the cost of production calibrating terminal 155.
The above is only embodiments herein, are not intended to limit the scope of the patents of the application, all to be said using the application
Equivalent structure or equivalent flow shift made by bright book and accompanying drawing content is applied directly or indirectly in other relevant technology necks
Domain similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of test method of array substrate driving circuit, which is characterized in that including：
It is right by from one drive signal line of a connection in a plurality of test signal wire drawn in the calibrating terminal of array substrate
The calibrating terminal input signal is to be tested；
Disconnect the connection of the test signal wire and the drive signal line tested recently；
Another test signal wire is connected into another drive signal line, to the calibrating terminal input signal to survey
Examination；
The step of returning to the connection of the test signal wire and the drive signal line for disconnecting and testing recently, until surveying
Examination is completed.
2. the test method of array substrate driving circuit according to claim 1, which is characterized in that the calibrating terminal
Quantity is to be at least 2, and the quantity of the test signal wire is equal to the quantity of the drive signal line.
3. the test method of array substrate driving circuit according to claim 2, which is characterized in that the method includes：
Draw in first calibrating terminal first test signal wire is connected into the first drive signal line, and described second is surveyed
The 4th test signal wire connection fourth drive signal line drawn in examination terminal, respectively to first calibrating terminal and described the
Two calibrating terminal input signals are to be tested；
The connection of the first test signal wire and first drive signal line tested is disconnected, and disconnects the institute tested
State the connection of the 4th test signal wire and the fourth drive signal line；
Draw in first calibrating terminal second test signal wire is connected into the second drive signal line, and described second is surveyed
The 5th test signal wire drawn in examination terminal connects the 5th drive signal line, respectively to first calibrating terminal and described the
Two calibrating terminal input signals are to be tested；
The connection of the second test signal wire and second drive signal line tested is disconnected, and disconnects the institute tested
State the connection of the 5th test signal wire and the 5th drive signal line；
It repeats the above steps, until testing all drive signal lines.
4. the test method of array substrate driving circuit according to claim 3, which is characterized in that
The signal for inputting first calibrating terminal is opposite with the signal potential for inputting second calibrating terminal.
5. the test method of array substrate driving circuit according to claim 1, which is characterized in that
It is provided with circuit breakpoint on the test signal wire, welding point is preset on the circuit breakpoint, by described in welding
The welding point on circuit breakpoint connects the test signal wire with the drive signal line.
6. the test method of array substrate driving circuit according to claim 5, which is characterized in that
Using point is welded described in laser welding, so that the drive signal line is connected with the test signal wire.
7. the test method of array substrate driving circuit according to claim 1, which is characterized in that the method is also wrapped
It includes：
It, will be from one in a plurality of test signal wire drawn in the calibrating terminal of the array substrate after the completion of test
Whole drive signal lines is connected, to carry out high vertical arrangement curing process；
After high vertical arrangement curing process is completed, the connection of the test signal wire and the drive signal line is disconnected.
8. the test method of array substrate driving circuit according to claim 1, which is characterized in that the method includes：
Draw in the calibrating terminal first test signal wire is connected into the first drive signal line, and will be in the calibrating terminal
Draw it is described first test signal wire by phase inverter connection fourth drive signal line, to the calibrating terminal input signal with
It is tested；
The connection of the first test signal wire and first drive signal line tested is disconnected, and disconnects the institute tested
State the connection of the first test signal wire Yu the fourth drive signal line；
Draw in the calibrating terminal second test signal wire is connected into the second drive signal line, and will be in the calibrating terminal
The second test signal wire drawn connects the 5th drive signal line by the phase inverter, inputs and believes to the calibrating terminal
Number to be tested；
The connection of the second test signal wire and second drive signal line tested is disconnected, and disconnects the institute tested
State the connection of the second test signal wire Yu the 5th drive signal line；
It repeats the above steps, until testing all drive signal lines.
9. a kind of display panel, which is characterized in that including：
Substrate；
Pixel circuit is located at substrate side display area；
Several drive signal lines are shown on the substrate ipsilateral with the pixel circuit, and from the non-of the substrate peripheral
Show that region extends to the display area, is connect with the pixel circuit；
Several test signal wires, on the substrate ipsilateral with the pixel circuit, every test signal wire is set
It is calculated as connecting with a drive signal line to test the pixel circuit；
Wherein, the connection structure between at least one test signal wire and the drive signal line is welding structure, and/
Or exists at least between a test signal wire and the drive signal line and blow or cut off structure.
10. display panel according to claim 9, which is characterized in that
The display panel further includes two calibrating terminals, and the calibrating terminal connects a plurality of test signal wire, every institute
It states test signal wire and connects a drive signal line, the calibrating terminal is connect with outside jig with input signal to described
It tests in signal wire；
Alternatively, the display panel further includes a calibrating terminal, the calibrating terminal connects a plurality of test signal wire, and
Every test signal wire connects two drive signal lines, and the calibrating terminal is connect with the external jig to input
Signal is into the test signal wire；
Wherein, exist between at least one test signal wire and all drive signal lines and blow or cut off structure.
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| CN201810933627.0A CN108877616B (en) | 2018-08-16 | 2018-08-16 | A kind of test method and display panel of array substrate driving circuit |
| PCT/CN2018/122615 WO2020034525A1 (en) | 2018-08-16 | 2018-12-21 | Test method for array substrate driving circuit, and display panel |
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| CN201810933627.0A CN108877616B (en) | 2018-08-16 | 2018-08-16 | A kind of test method and display panel of array substrate driving circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109637405A (en) * | 2018-12-05 | 2019-04-16 | 惠科股份有限公司 | Method and device for testing array substrate and storage medium |
| WO2020034525A1 (en) * | 2018-08-16 | 2020-02-20 | 深圳市华星光电半导体显示技术有限公司 | Test method for array substrate driving circuit, and display panel |
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| CN108877616B (en) * | 2018-08-16 | 2019-09-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of test method and display panel of array substrate driving circuit |
-
2018
- 2018-08-16 CN CN201810933627.0A patent/CN108877616B/en active Active
- 2018-12-21 WO PCT/CN2018/122615 patent/WO2020034525A1/en active Application Filing
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| US20150160276A1 (en) * | 2013-12-11 | 2015-06-11 | Samsung Display Co., Ltd. | System for inspecting display panel |
| CN103995407A (en) * | 2014-05-08 | 2014-08-20 | 京东方科技集团股份有限公司 | Array substrate and display panel |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020034525A1 (en) * | 2018-08-16 | 2020-02-20 | 深圳市华星光电半导体显示技术有限公司 | Test method for array substrate driving circuit, and display panel |
| CN109637405A (en) * | 2018-12-05 | 2019-04-16 | 惠科股份有限公司 | Method and device for testing array substrate and storage medium |
| CN109637405B (en) * | 2018-12-05 | 2021-04-06 | 惠科股份有限公司 | Method and device for testing array substrate and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020034525A1 (en) | 2020-02-20 |
| CN108877616B (en) | 2019-09-20 |
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