CN203760475U - Anti-radiation reinforced aluminium-grid CMOS phase inverter and CMOS semiconductor device - Google Patents

Anti-radiation reinforced aluminium-grid CMOS phase inverter and CMOS semiconductor device Download PDF

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Publication number
CN203760475U
CN203760475U CN201320882202.4U CN201320882202U CN203760475U CN 203760475 U CN203760475 U CN 203760475U CN 201320882202 U CN201320882202 U CN 201320882202U CN 203760475 U CN203760475 U CN 203760475U
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China
Prior art keywords
nmos pass
pass transistor
gate
oxide
shading ring
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Chinese (zh)
Inventor
张禄
孟欣
张伟
和斌
张燏
郭艳玲
邢岳
吕崇森
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BEIJING YU XIANG ELECTRONIC Co Ltd
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BEIJING YU XIANG ELECTRONIC Co Ltd
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Abstract

The utility model provides an anti-radiation reinforced aluminium-grid CMOS phase inverter and a CMOS semiconductor device. The phase inverter comprises a PMOS transistor and an NMOS transistor, which respectively comprise a source electrode, a drain electrode, and a grid electrode. The phase inverter also comprises an N+ isolating ring and a P+ isolating ring, which respectively surround the PMOS transistor and the NMOS transistor. The grid electrode of the PMOS transistor and the grid electrode of the NMOS transistor are communicated with each other to form the input end of the phase inverter. The drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor are communicated with each other to form the output end of the phase inverter. The source electrode of the PMOS transistor forms a high-level end of the phase inverter, and the source electrode of the NMOS transistor forms a low-level end of the phase inverter. In the phase inverter, the thickness of a field oxide layer formed under the aluminium grid electrode layer of the NMOS transistor is equal to the thickness of a grid oxide layer of the NMOS transistor. Through employing the characteristic of strong capability, of a thin grid oxide layer, of resisting accumulated dose radiation, the thin grid oxide layer of the NMOS transistor extends to the P+ isolating ring, thereby cutting off a conducting circuit between drain and source electrode of the NMOS transistor under the condition of large-dose radiation, and improving the capability, of the phase inverter, of resisting accumulated dose radiation.

Description

Through alum gate CMOS inverter and the cmos semiconductor device of radiation hardening
Technical field
The utility model belongs to microelectronics technology.Be specifically related to a kind of place through the alum gate cmos semiconductor device of radiation hardening with through the alum gate CMOS of radiation hardening inverter.
Background technology
Along with scientific and technical development, particularly along with the development of nuclear technology and space technology, increasing electronic equipment need to use under various radiation environment conditions.Radiation interaction in components and parts and environment in electronic equipment causes components and parts electrical quantity to change, and when serious, causes circuit malfunction, makes electronic equipment cisco unity malfunction.Once affect in history nuclear technology development because the capability of resistance to radiation of components and parts is poor and affect the situation generation of the lifetime of satellite.Cmos circuit is widely used in satellite and nuclear test environment, and cmos circuit is especially responsive to radiation, without the cmos circuit anti-integral dose radiation ability of reinforcing, common process is produced lower than 1 × 10 2gY (Si), as exceed this dosage and can cause device damage, its cisco unity malfunction caused.Long-life satellite is during along its orbital motion, and the integral dose radiation being subject to can reach 5 × 10 3more than GY (Si), obviously, can not meet long-life satellite and the instructions for use of nuclear radiation environment to device without the cmos circuit of radiation hardening, therefore must carry out radiation hardening to cmos circuit.
For cmos device, the effect that integral dose radiation causes is mainly in oxide, to produce electron-hole pair electric charge and at Si-SiO 2generation of interfaces interfacial state.Even at room temperature, SiO 2in electronics be also movably, it can move rapidly and leave SiO 2layer, towards the gate electrode motion of positive bias; On the other hand, at SiO 2hole in layer can produce oxidation charge Q 0x, at this moment positive Oxide trapped charge can cause cut-in voltage drift, the drift of cut-in voltage is proportional to SiO 2thickness square, i.e. t 2ox.
In prior art, alum gate cmos circuit is to be made up of traditional body silicon device.In conventional alum gate cmos circuit manufacture craft, along with the progressively attenuate of gate oxide, the electric charge that radiation source produces in gate oxide is very little on the impact of device.But because the requirement of device architecture and performance parameter, the thickness of field oxide can not be too thin, and General Requirements is more than 500nm.The electric charge that radiation source produces in the field oxide of this thickness can cause place transoid, forms conducting channel, affects device and normally works.
In cmos circuit, place is mainly used in rising buffer action between device, and place dielectric layer is mainly by for example SiO 2medium form, place dielectric layer is provided with the aluminum strip that is used to form gate electrode simultaneously, metal-oxide-semiconductor structure conventional in this structure and integrated circuit is closely similar, generally can be thought the metal-oxide-semiconductor structure of place dielectric layer as gate oxide, this metal-oxide-semiconductor structure is commonly called MOS field pipe.
Between the each device of body sial grid cmos circuit, have the doped region isolation of high concentration, therefore the cut-in voltage of parasitic metal-oxide-semiconductor is higher, generally can not cause substrate transoid and forms conducting channel.
In P trap cmos circuit, the substrate of nmos pass transistor is lightly doped P type place, and surface concentration is about 1 × 10 16/ cm 3.General N MOS transistor source region, drain region are to P +region between shading ring is place, and wherein the thickness of field oxide is 600nm-1 μ m, is 10-20 times of gate oxide thickness.Due to square being directly proportional of integral dose radiation damage and oxidated layer thickness, so the conventional thick place oxide layer of 1.0 μ m, under the radiation effects of accumulated dose 500GY (Si), its cut-in voltage drifts about will be greater than 50V; It is a lot of that the voltage producing due to integral dose radiation again can cause lightly doped P type place cut-in voltage to decline, and causes P type substrate transoid, between drain region, source region, forms conducting channel, and CMOS integrated circuit static leakage current is increased.This phenomenon the lighter causes electrical quantity to exceed standard, and makes circuit loss of function when serious.
For above problem, need a kind of technology of P trap alum gate cmos circuit place being carried out to radiation hardening, need cmos circuit and a kind of inverter that have through the cmos circuit of radiation hardening of a kind of place through radiation hardening.
Utility model content
The purpose of this utility model is to overcome problems of the prior art, a kind of anti-integral dose radiation place reinforcement technique is provided, MOS transistor cut-in voltage drift value under high dose radiation is reduced, solve the source drain edge parasitic leakage problem being caused by integral dose radiation, keep the validity of isolation characteristic, and be convenient to implement.
According to an aspect of the present utility model, provide a kind of through the alum gate CMOS of radiation hardening inverter, comprise
Comprise respectively PMOS transistor and the nmos pass transistor of source electrode, drain and gate,
Surround respectively the N of described PMOS transistor and described nmos pass transistor +shading ring and P +shading ring,
The grid of the transistorized grid of described PMOS and described nmos pass transistor is communicated with the input that forms inverter,
The drain electrode of the transistorized drain electrode of described PMOS and described nmos pass transistor is communicated with the output that forms inverter,
The transistorized source electrode of described PMOS forms the hot end of inverter,
The source electrode of described nmos pass transistor forms the cold end of inverter,
It is characterized in that, the thickness of field oxide of aluminum gate electrode layer below that is formed on nmos pass transistor is identical with the thickness of the gate oxide of described nmos pass transistor.
Preferably, extend to described P with the field oxide of the gate oxide same thickness of nmos pass transistor along the bearing of trend of aluminum gate electrode layer +shading ring.
Preferably, the field oxide of the gate oxide same thickness of described and nmos pass transistor extends to described P along the bearing of trend of aluminum gate electrode layer +shading ring also covers described P +shading ring 1-2 micron.
Preferably, the width of the field oxide of the gate oxide same thickness of described and nmos pass transistor is less than the width of gate oxide.
According on the other hand of the present utility model, a kind of alum gate cmos semiconductor device through radiation hardening is provided, comprise
Nmos pass transistor and PMOS transistor,
Surround respectively the N of described PMOS transistor and described nmos pass transistor +shading ring and P +shading ring,
It is characterized in that, be formed under the aluminum gate electrode layer of described nmos pass transistor the thickness of the thickness of field oxide and the gate oxide of described nmos pass transistor identical.
Provide a kind of alum gate cmos semiconductor device through radiation hardening more on the one hand according to of the present utility model, comprise
N type semiconductor substrate and be formed on P type well region in N type semiconductor substrate;
Be formed on the P in N type semiconductor substrate +source region and P +drain region,
Be formed on the N in P type well region +source region and N +drain region,
Surround described P +source region and P +the N in drain region +shading ring and surround described N +source region and N +the P in drain region +shading ring;
Be formed on the oxide skin(coating) in described Semiconductor substrate; And
Be formed on the aluminum gate electrode layer that is respectively used to form the interconnect electrode layer of source electrode and drain electrode and is used to form grid on described oxide skin(coating),
It is characterized in that,
Be formed under the aluminum gate electrode layer of nmos pass transistor the thickness of the thickness of field oxide and the gate oxide of described nmos pass transistor identical.
The beneficial effects of the utility model are as follows:
Utilize the strong feature of thin gate oxide anti-integral dose radiation ability, thin gate oxide is extended and expands to P +on shading ring, thereby block the conductive path between the drain region, source region forming because of high dose radiation, improved the ability of circuit anti-integral dose radiation.
Brief description of the drawings
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail;
Fig. 1 is the CMOS inverter chip longitudinal profile schematic diagram of prior art;
Fig. 2 is the CMOS inverter chip longitudinal profile schematic diagram according to the utility model embodiment;
Fig. 3 is the CMOS inverter chip schematic top plan view of prior art;
Fig. 4 is the CMOS inverter chip schematic top plan view according to the utility model embodiment;
Fig. 5 is the longitudinal profile schematic diagram along L1-1 line in the chip of inverter shown in Fig. 3;
Fig. 6 is the longitudinal profile schematic diagram along L2-1 line in the inverter chip of the embodiment of the utility model shown in Fig. 4;
Fig. 7 is the longitudinal profile schematic diagram along L1-2 line in the chip of inverter shown in Fig. 3;
Fig. 8 is the longitudinal profile schematic diagram along L2-2 line in the inverter chip of the embodiment of the utility model shown in Fig. 4;
Fig. 9 is NMOS pipe cut-in voltage (V tN) resolution chart;
Figure 10 is PMOS pipe cut-in voltage (V tP) resolution chart.
Embodiment
For understanding better the utility model, will further illustrate scheme of the present utility model by specific embodiment below, protection range of the present utility model should comprise the full content of claim, but is not limited to this.
In accompanying drawing, same or analogous Reference numeral represents same or analogous architectural feature.For design feature of the present utility model is clearly described, each several part does not draw in proportion.Particularly, in figure, each Reference numeral represents respectively,
101,201:N type substrate;
102,202:P well region;
103,203:P +district (P raceway groove source region, drain region);
113,213:P +district (P +shading ring);
104,204:N +district (N raceway groove source region, drain region);
114,214:N +district (N +shading ring);
105a, 205a: gate oxide;
105b, 205b: field oxide district;
106,206: fairlead;
107,207: gate electrode;
108,208: electrode interconnection line;
209: gate oxide expansion area.
First with reference to figure 1, Fig. 3, Fig. 5 and Fig. 7 taking N-type substrate and CMOS device as example, the CMOS inverter structure of prior art is described.Fig. 1 is the longitudinal profile schematic diagram of the CMOS inverter chip of prior art, and Fig. 3 is its schematic top plan view; Fig. 5 illustrates that a along L1-1 line in the chip of inverter shown in Fig. 3 is to longitudinal profile schematic diagram; Fig. 3 illustrates that b along L1-2 line in the chip of inverter shown in Fig. 3 is to longitudinal profile schematic diagram.This inverter comprises N-type substrate from bottom to up successively, is formed on oxide skin(coating) on substrate and is formed on the grid electrode layer on oxide skin(coating) and is communicated with respectively the interconnect electrode layer in source region and drain region.N-type substrate 1 is for example N-type (100) silicon single crystal flake, and resistivity is for example ρ=2～4 Ω cm, and for example its surface concentration of P well region being formed on is wherein for example 8 × 10 15/ cm 3～1 × 10 16/ cm 3, junction depth is for example 7～9 microns.This CMOS inverter comprises nmos pass transistor and PMOS transistor.Particularly, the part that PMOS transistor is formed in N-type substrate comprises the P that is used to form source/drain regions 103 +district is channel region therebetween.The part that nmos pass transistor is formed in P well region comprises the N that is used to form source/drain regions 104 +district is channel region therebetween.In substrate, be further formed with for isolating respectively the transistorized N of PMOS +the P of shading ring 114 and isolation nmos pass transistor +shading ring 113.The thickness of gate oxide 105a on the Thickness Ratio channel region of the insulation oxide layer of cmos device is thick, so that desirable insulation and performance parameter to be provided.The gate electrode 107 that is formed on the transistorized gate oxide 105a of NMOS and PMOS top communicates with each other and forms the input IN of inverter, and the drain electrode 108 of the transistorized drain electrode of PMOS and nmos pass transistor is communicated with the output OUT that forms CMOS inverter.The transistorized source electrode of PMOS and hot end V dDconnect the source electrode of nmos pass transistor and cold end V sSconnect.Gate electrode interconnection line is formed by the metal aluminium lamination being formed on oxide skin(coating) conventionally, below also referred to as aluminum gate electrode layer.Conventionally, in MOS device, the region of playing buffer action between source region and drain region and shading ring is called as place, and the oxide skin(coating) on place is called as field oxide.On field oxide, at least part of region is used to form the aluminum gate electrode layer covering of gate electrode.In the CMOS of prior art shown in Fig. 1 inverter, for obtaining desirable insulation and isolation effect, the field oxide 105b that is positioned at aluminum gate electrode layer below has the thickness thicker than gate oxide 105a conventionally, as shown in Figure 7.As above introduced, in the time of cmos device experience radiation irradiation, the thickness of the intensity of total dose irradiation effect and radiation sensitive region oxide layer square proportional, the oxide layer of sensitizing range is thicker, and total dose irradiation effect will be a square increase.And for adopting in the CMOS technique circuit of shading ring isolation, radiation sensitive region is divided into gate oxidation district and field oxide region.Because the oxide layer 105b thickness of field oxide isolation region is far longer than the thickness of gate oxide 105a, be conventionally greater than 600nm, as shown in Fig. 3, Fig. 5 and Fig. 7, be lightly doped P-district at the substrate of nmos pass transistor, surface impurity concentration is 1 × 10 16/ cm 3situation under, the electric charge that integral dose radiation produces can cause gate voltage to increase, make nmos pass transistor substrate transoid, surface becomes N-type district, make to form between source-drain area conducting channel, nmos pass transistor cut-off leakage current increases, thus the impact of the total dose irradiation effect that the total dose irradiation effect that causes field oxide isolation region is far longer than gate oxide to the impact of device on device, cause device in the time of experience radiation, nmos pass transistor field oxide below P type well region transoid forms N-type conducting channel.
, illustrate according to CMOS inverter structure of the present utility model taking N-type substrate and CMOS device as example below with reference to Fig. 2, Fig. 4, Fig. 6 and Fig. 8.Fig. 2 is that Fig. 4 is its schematic top plan view according to the longitudinal profile schematic diagram of the CMOS inverter chip of the utility model embodiment; Fig. 6 illustrates that a along L2-1 line in the chip of inverter shown in Fig. 4 is to longitudinal profile schematic diagram; Fig. 8 illustrates that b along L2-2 line in the chip of inverter shown in Fig. 4 is to longitudinal profile schematic diagram.The thickness of the field oxide layer covering except aluminum gate electrode layer, other parts are all same or similar with the inverter structure of the prior art shown in Fig. 1, and in each figure, corresponding Reference numeral represents same or analogous structure.For simplicity's sake, identical structure and content repeat no more here.
Be different from prior art, in this embodiment of the present utility model, for obtaining the effect of radiation hardening, the field oxide 209 that is positioned at aluminum gate electrode layer below has the thickness the same with grid oxic horizon 205a, and hereinafter in field oxide, the part identical with gate oxide thickness is also referred to as gate oxide expansion area.
Fig. 4, Fig. 6 and Fig. 8 have specifically illustrated according to the layout of the field oxide of the attenuate of nmos pass transistor in the CMOS inverter of the utility model embodiment.In this embodiment, the place insulation oxide layer that has a same thickness with thin gate oxide extends to P from gate oxide district 205a +diffusion region is also P +on shading ring 213, the part of extension illustrates with 209.For inverter when radiation hardening effect is provided has good insulation and isolation characteristic, there is the width that is less than gate oxide with the width of the field oxide of gate oxide same thickness.Preferably, in the scope allowing at lithographic accuracy, the width of this extension should be as far as possible little.Due to P +shading ring region surface impurity concentration is higher, is greater than 1 × 10 18/ cm 3, than P well region impurity concentration (1 × 10 16/ cm 3high two orders of magnitude, cover P so the expansion of thin gate oxide layer expansion area should extend +on shading ring.But extension is to P +the covering of shading ring 213 should be lacked as far as possible, is preferably less than 2 microns.
As previously mentioned, the substrate of conventional nmos pass transistor is lightly doped P-district, and surface impurity concentration is 1 × 10 16/ cm 3, because the oxide layer of place part is thicker, being greater than 600nm, the electric charge that integral dose radiation produces can cause gate voltage to increase, and makes nmos pass transistor substrate transoid, and surface becomes N-type district, makes to form conducting channel between the leakage of source, and nmos pass transistor cut-off leakage current increases.The utility model is changed into the thick oxide layer of place part the thickness of thin gate oxide, or in other words, the utility model is by extending to P+ shading ring by having in nmos pass transistor compared with the gate oxide layers of minimal thickness, its anti-integral dose radiation ability is identical with gate oxide, and anti-integral dose radiation energy force rate improves nearly two magnitudes before improving.
Illustrate according to the making of CMOS inverter of the present utility model and method of testing below with reference to example.
1) prepared by backing material 201: select N-type (100) silicon single crystal flake, electricalresistivityρ=2-4 Ω cm.
2) growth field oxide 205b: oxidated layer thickness is for example 800nm left and right.
3) make P trap 202: carry out photoetching for the first time with photo etched mask and form P-district figure, then adopt ion injection method doping to form P trap, P trap surface concentration is 8 × 10 15/ cm 3～1 × 10 16/ cm 3.Growth thickness is for example the oxide layer of 500nm subsequently.
4) make P channel MOS transistor source region, drain region and P type shading ring district: carry out mask lithography for the second time, form the figure in PMOS transistor source region, drain region and P type shading ring district, then adopt method of diffusion to form PMOS pipe source region, drain region and P type shading ring district, square resistance 45 ± 9 Ω/, surface concentration >10 18/ cm 3, such as 360nm of growth oxidated layer thickness.
5) make N-channel MOS transistor source region, drain region and N-type shading ring district: carry out mask lithography for the third time, carve the figure in source region, drain region and the N-type shading ring district of NMOS pipe, then adopt method of diffusion, form NMOS pipe source region, drain region and N-type shading ring district, square resistance: 14 ± 3 Ω/, such as 360nm of growth oxidated layer thickness.
6) manufacturing gate oxide layers district 205a and grid oxygen expansion area 208: carry out mask lithography the 4th time, carve figure and the pre-fairlead of carving of gate oxide and gate oxide expansion area, carry out gate oxidation and anneal, the gate oxide thickness of the expansion obtaining is for example 50 ± 5nm.The grid region figure of this expansion comprises that the gate oxide part of corresponding gate electrode and the direction that extend along gate electrode in grid region extend to the gate oxide expansion area part of P type shading ring.Preferably, have with the expansion of gate oxide same thickness and extend to described P +shading ring also covers described P +shading ring 1-2 micron.Preferably, the width of described expansion is narrower than the width of gate oxide.
7) carry out the 5th photoetching, carve fairlead 206.
8) make gate electrode and interconnecting line.Sputtered aluminum layer, carries out the 6th photoetching, carves gate electrode 207 and interconnecting line 208, carries out alloy.
Adopt following method to test known CC4000 series of products and the CC4000 series of products with radiation hardening structure, respectively before radiation, apply after 3000Gy (Si) dosage irradiation, apply after 1500Gy (Si) dosage irradiation again, and carry out, after accelerated ageing, obtaining following test data.
1) cut-in voltage
Adopt 10 μ A top-up injection methods of testing, measure respectively the cut-in voltage V of sample tP/ V tN.The test of pair nmos transistor and the transistorized cut-in voltage of PMOS respectively as shown in Figure 9 and Figure 10.
2) function and electrical quantity
Function and the electrical quantity of difference test component under 5V, 10V, 15V.
3) static father leakage current
At supply voltage V dDin=15V situation, the quiescent power supply current in semiconductor integrated circuit I when testing respectively all inputs and be high level and all inputs and being low level dD.
4) failure criteria
1. require function normal, electrical quantity meets code requirement;
2. device quiescent power supply current in semiconductor integrated circuit is less than or equal to 100 times of maximum specification value;
3. NMOS pipe cut-in voltage V tNbe more than or equal to 0.3V, PMOS pipe cut-in voltage | V tP| be less than or equal to 2.8V, and require radiation front and back cut-in voltage variable quantity | △ V t| be less than or equal to 1.4V.
Test result
Table 1.CMOS integrated circuit cut-in voltage is with irradiation dose situation of change (taking eight kinds of circuit as example)
Table 2.CMOS integrated circuit static father leakage current is with irradiation dose situation of change (taking eight kinds of circuit as example)
Product is after above test, and electrical quantity and cut-in voltage all meet standard-required, and product anti-integral dose radiation ability reaches 3 × 10 3more than GY (Si).
Can find out, structure of the present utility model only need be improved the litho pattern in the four mask of cmos circuit, do not change existing process equipment and do not increase on the basis of processing step, can eliminate nmos pass transistor source leak between leakage current.
There is the cmos circuit of the utility model structure and the anti-integral dose radiation ability of inverter brings up to 3 × 10 3more than GY (Si), than unguyed product anti-integral dose radiation ability 1 × 10 2gY (Si) has improved 1～1.5 magnitude.
To sum up, use the utility model to manufacture alum gate cmos circuit and inverter, ensureing that under the constant prerequisite of circuit function, the anti-integral dose radiation ability of circuit is greatly improved, and the method is convenient to implement, do not increase production cost, technology stability is good.
Obviously; above-described embodiment of the present utility model is only for the utility model example is clearly described; and be not the restriction to execution mode of the present utility model; for those of ordinary skill in the field; can also make other changes in different forms on the basis of the above description; here cannot give all execution modes exhaustively, everyly belong to apparent variation or the still row in protection range of the present utility model of variation that the technical solution of the utility model extends out.

Claims (9)

1. through the alum gate CMOS of a radiation hardening inverter, comprise
Comprise respectively PMOS transistor and the nmos pass transistor of source electrode, drain and gate,
Surround respectively the N of described PMOS transistor and described nmos pass transistor +shading ring and P +shading ring,
The grid of the transistorized grid of described PMOS and described nmos pass transistor is communicated with the input that forms inverter,
The drain electrode of the transistorized drain electrode of described PMOS and described nmos pass transistor is communicated with the output that forms inverter,
The transistorized source electrode of described PMOS forms the hot end of inverter,
The source electrode of described nmos pass transistor forms the cold end of inverter,
It is characterized in that,
The thickness of field oxide of aluminum gate electrode layer below that is formed on nmos pass transistor is identical with the thickness of the gate oxide of described nmos pass transistor.
2. as claimed in claim 1ly it is characterized in that through the alum gate CMOS of radiation hardening inverter, extend to described P with the field oxide of the gate oxide same thickness of nmos pass transistor along the bearing of trend of aluminum gate electrode layer +shading ring.
3. as claimed in claim 1ly it is characterized in that through the alum gate CMOS of radiation hardening inverter, extend to described P with the field oxide of the gate oxide same thickness of nmos pass transistor along the bearing of trend of aluminum gate electrode layer +shading ring also covers described P +shading ring 1-2 micron.
4. as claimed in claim 2ly it is characterized in that through the alum gate CMOS of radiation hardening inverter, be less than the width of gate oxide with the width of the field oxide of the gate oxide same thickness of nmos pass transistor.
5. through an alum gate cmos semiconductor device for radiation hardening, comprise
Nmos pass transistor and PMOS transistor,
Surround respectively the N of described PMOS transistor and described nmos pass transistor +shading ring and P +shading ring,
It is characterized in that,
Be formed under the aluminum gate electrode layer of described nmos pass transistor the thickness of the thickness of field oxide and the gate oxide of described nmos pass transistor identical.
6. through an alum gate cmos semiconductor device for radiation hardening, comprise
N type semiconductor substrate and be formed on P type well region in N type semiconductor substrate;
Be formed on the P in N type semiconductor substrate +source region and P +drain region,
Be formed on the N in P type well region +source region and N +drain region,
Surround described P +source region and P +the N in drain region +shading ring and surround described N +source region and N +the P in drain region +shading ring;
Be formed on the oxide skin(coating) in described Semiconductor substrate; And
Be formed on the aluminum gate electrode layer that is respectively used to form the interconnect electrode layer of source electrode and drain electrode and is used to form grid on described oxide skin(coating),
It is characterized in that,
Be formed under the aluminum gate electrode layer of nmos pass transistor the thickness of the thickness of field oxide and the gate oxide of described nmos pass transistor identical.
7. the alum gate cmos semiconductor device through radiation hardening as described in claim 5 or 6, is characterized in that, extends to described P with the field oxide of the gate oxide same thickness of nmos pass transistor along the bearing of trend of aluminum gate electrode layer from channel region +shading ring.
8. the alum gate cmos semiconductor device through radiation hardening as described in claim 5 or 6, is characterized in that, extends to described P with the field oxide of the gate oxide same thickness of nmos pass transistor along the bearing of trend of aluminum gate electrode layer from channel region +shading ring also covers described P +shading ring 1-2 micron.
9. the alum gate cmos semiconductor device through radiation hardening as described in claim 5 or 6, is characterized in that, is less than the width of gate oxide with the width of the field oxide of the gate oxide same thickness of nmos pass transistor.
CN201320882202.4U 2013-12-30 2013-12-30 Anti-radiation reinforced aluminium-grid CMOS phase inverter and CMOS semiconductor device Withdrawn - After Issue CN203760475U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762215A (en) * 2013-12-30 2014-04-30 北京宇翔电子有限公司 Aluminum gate CMOS phase inverter and CMOS semiconductor device strengthened through radiation resistance

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762215A (en) * 2013-12-30 2014-04-30 北京宇翔电子有限公司 Aluminum gate CMOS phase inverter and CMOS semiconductor device strengthened through radiation resistance

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