CN203733109U - VGA signal test fixture - Google Patents
VGA signal test fixture Download PDFInfo
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- CN203733109U CN203733109U CN201420007401.5U CN201420007401U CN203733109U CN 203733109 U CN203733109 U CN 203733109U CN 201420007401 U CN201420007401 U CN 201420007401U CN 203733109 U CN203733109 U CN 203733109U
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- Prior art keywords
- pin
- male interface
- sub male
- resistance
- sub
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- 238000012360 testing method Methods 0.000 title claims abstract description 27
- QWCRAEMEVRGPNT-UHFFFAOYSA-N buspirone Chemical compound C1C(=O)N(CCCCN2CCN(CC2)C=2N=CC=CN=2)C(=O)CC21CCCC2 QWCRAEMEVRGPNT-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000005259 measurement Methods 0.000 claims description 30
- 238000003860 storage Methods 0.000 abstract description 13
- 239000003990 capacitor Substances 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The utility model discloses a VGA signal test fixture comprising a D-Sub male interface circuit, an impedance matching circuit, and a resolution storage circuit. The D-Sub male interface circuit comprises a D-Sub male interface having 15 connection pins; the pins R, G, B, H and V of the D-Sub male interface are connected to the impedance matching circuit; the I2C bus pin and power pin of the D-Sub male interface are connected to the resolution storage circuit; the other pins of the D-Sub male interface are grounded. The VGA signal test fixture is low in cost, good in stability, low in signal distortion, and high in testing efficiency, and by the use of an E2PROM, the VGA signal test fixture is applicable to testing computers manufactured by various manufacturers.
Description
Technical field
The utility model relates to signal testing field, relates in particular to a kind of measurement jig of VGA signal.
Background technology
Along with the development of computing machine is more and more advanced, also more and more important to the test of the demonstration output signal VGA signal of computing machine (R, G, B, H, V signal, wherein R, G, B are tricolor signal, H, V are row, field signal).Testing scheme for VGA signal in prior art has two kinds:
Existing solution one: obtain VGA signal by the mode of external connection of computer display, and survey this VGA signal at the VGA of computing machine interface point.
The shortcoming of such scheme is:
(1) in order to test VGA signal, need an external display, cause test inconvenience;
(2) because test is higher to the resolution requirement of external-connection displayer, cause testing cost too high;
(3) reliability of signal is poor;
(4) testing efficiency is lower.
Existing solution two: by the R of VGA interface, G, B, H, V signal source welding resistance, draw VGA signal.
The shortcoming of such scheme is:
(1) poor reliability of signal;
(2) testing efficiency is lower;
(3) measuring stability is lower.
Utility model content
The purpose of this utility model is to provide a kind of measurement jig of VGA signal, and the test VGA signal that described tool can be reliable and stable, can reduce testing cost again, and can improve the efficiency of test.
For achieving the above object, the utility model proposes a kind of measurement jig of VGA signal, described tool comprises D-Sub male interface circuit, impedance matching circuit and resolution memory circuit, wherein said D-Sub male interface circuit comprises that one has 15 D-Sub male interfaces that connect pin, R, G, B, H, V pin in described D-Sub male interface are connected to described impedance matching circuit, the I in described D-Sub male interface
2c bus pin and power pins are connected to described resolution memory circuit, all the other the pin ground connection in described D-Sub male interface.
Preferably, described impedance matching circuit comprises five build-out resistors, the resistance that is wherein connected in the R pin in described D-Sub male interface is configured to 75ohm, the resistance that is connected in the G pin in described D-Sub male interface is configured to 75ohm, the resistance that is connected in the B pin in described D-Sub male interface is configured to 75ohm, the resistance that is connected in the H pin in described D-Sub male interface is configured to 2.2Kohm, and the resistance that is connected in the V pin in described D-Sub male interface is configured to 2.2Kohm.
Preferably, described resolution memory circuit comprises an E
2pROM, described E
2the I of PROM
2c bus pin is connected to respectively the I in described D-Sub male interface
2c bus pin; And from described E
2the I of PROM
2c bus pin is drawn respectively the 7th resistance, and the 8th resistance is connected to the power pins in described D-Sub male interface; Described E
2the WP pin of PROM is connected to the power pins in described D-Sub male interface through the 9th resistance; Described E
2the power pins of PROM is connected to the power pins in described D-Sub male interface, and through the second electric capacity of parallel connection, the 3rd capacity earth; Described E
2all the other pin ground connection of PROM.
Preferably, described E
2the resolution information of pre-stored resolution control information and test use in PROM.
Preferably, described measurement jig also comprises an anti-static circuit, described anti-static circuit comprises five ESD diodes, and one end of described five ESD diodes is connected with R, G, B, H, V pin in described D-Sub male interface respectively, its other end ground connection.
The beneficial effects of the utility model are, the measurement jig cost of the VGA signal that the utility model is related is lower, good stability, and the degree of distortion of signal is lower, and testing efficiency is higher, and E
2the use of PROM makes this measurement jig be applicable to the test of the computing machine of each manufacturers produce.
Accompanying drawing explanation
Fig. 1 shows the block diagram of the related measurement jig of the utility model.
Fig. 2 shows the related D-Sub male interface circuit figure of the utility model.
Fig. 3 shows the related impedance matching circuit figure of the utility model.
Fig. 4 shows the related resolution memory circuit figure of the utility model.
Fig. 5 shows the related anti-static circuit figure of the utility model.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further.
As shown in Figure 1, the measurement jig according to the related VGA signal of the utility model comprises D-Sub male interface circuit 10, impedance matching circuit 20, resolution memory circuit 30 and anti-static circuit 40.Wherein said impedance matching circuit 20, resolution memory circuit 30 and anti-static circuit 40 are connected to described D-Sub male interface circuit 10 by the corresponding pin of the pin with described D-Sub male interface circuit 10 respectively.
As shown in Figure 2, described D-Sub male interface circuit 10 comprises a D-Sub male interface JP1, the first resistance R 1 and the first capacitor C 1 to concrete D-Sub male interface circuit 10.Described D-Sub male interface JP1 comprises 15 pin and the first grounding pin and the second grounding pins that are connected with corresponding D-Sub female interface, the parallel circuit ground connection forming by the first resistance R 1 and the first capacitor C 1 after above-mentioned two grounding pins interconnect.The first pin in described 15 pins is the introducing pin of CRT_R signal, the second pin is the introducing pin of CRT_G signal, the 3rd pin is the introducing pin of CRT_B signal, fourth, fifth, six, seven, eight, ten, 11 pin ground connection, the 9th pin is power supply CRT_VCC pin, and the 12 pin is I
2cRT_DAT pin in C bus, the 13 pin is the introducing pin of HSYNC signal, and the 14 pin is VSYNC signal leading pin, and the 15 pin is I
2cRT_CLK pin in C bus.
Concrete impedance matching circuit 20 as shown in Figure 3, described impedance matching circuit 20 comprises the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the five resistance R 5 and the 6th resistance R 6, one end of described five resistance respectively with the first pin of described D-Sub male interface JP1, the second pin, the 3rd pin, the 13 pin is connected with the 14 pin, other end ground connection.
As shown in Figure 4, described resolution memory circuit 30 comprises a storage chip U1 to concrete resolution memory circuit 30, the 7th resistance R 7, the eight resistance R 8, the nine resistance R 9, the second capacitor C 2 and the 3rd capacitor C 3.It is the E of AT24C02BN-SH-T that described storage chip U1 can adopt model
2pROM, its NC_1, NC_2, PORT# and GND pin ground connection, the SCL pin of described storage chip U1 and SDA pin are connected to respectively the 15 pin and the 12 pin of described D-Sub male interface JP1, as I
2c bus interface, and draw respectively from SCL pin and the SDA pin of this storage chip U1 the 9th pin that the 7th resistance R 7, the eight resistance R 8 are connected to described D-Sub male interface JP1; The WP pin of described storage chip U1 is connected to the 9th pin of described D-Sub male interface JP1 through the 9th resistance R 9; The VCC pin of described storage chip U1 is connected to the 9th pin of described D-Sub male interface JP1, and through the second capacitor C 2, the three capacitor C 3 ground connection of parallel connection.
Concrete anti-static circuit 40 as shown in Figure 5, described anti-static circuit 40 comprises an ESD(static discharge) diode D1, the 2nd ESD diode D2, the 3rd ESD diode D3, the 4th ESD diode D4 and the 5th ESD diode D5, one end of described five diodes respectively with the first pin of described D-Sub male interface JP1, the second pin, the 3rd pin, the 13 pin is connected with the 14 pin, other end ground connection.Described anti-static circuit 40 is too high for preventing electrostatic potential, damages tool.
Due to R, the G of computer export, the output impedance of B signal is 75ohm, the H of its output, the output impedance of V signal are 2.2Kohm, in order to make measurement jig, can be identified by computing machine, need to the resistance in impedance matching circuit 20 be arranged, the resistance of concrete the second resistance R 2 is 75ohm, and the resistance of the 3rd resistance R 3 is 75ohm, and the resistance of the 4th resistance R 4 is 75ohm, the resistance of the 5th resistance R 5 is 2.2Kohm, and the resistance of the 6th resistance R 6 is 2.2Kohm.
In resolution memory circuit 30; the WP pin of described storage chip U1 is connected to the 9th pin CRT_VCC end of described D-Sub male interface JP1; therefore described storage chip U1 has started writing protection function, can only carry out read operation to the content in described storage chip U1.
In the manufacturing process of this measurement jig, in described storage chip U1 burning in advance the control information DDC(display data passage of resolution)/EDID(extending display identification data), and burning test the required resolution of respectively organizing.
Concrete test philosophy is: the D-Sub female interface that the D-Sub male interface JP1 of measurement jig is inserted to computing machine, computer motherboard is by mating to identify described measurement jig by R, G, B, H, V five output impedance of road signal and the impedance of measurement jig, after impedance is mated completely, computing machine has been identified described measurement jig.Pass through I
2c bus, computing machine reads the resolution consistent resolution current with computing machine in storage chip U1 in described measurement jig, the resolution of computing machine and described measurement jig is consistent, just can be by the R of computer export, G, B, H, V five road signal leadings in measurement jig by described D-Sub male interface JP1.Can in described measurement jig, weld afterwards probe point survey row surveys, and result of detection is shown on oscillograph for described R, G, B, H, V five road signals.
The measurement jig cost of the VGA signal that the utility model is related is lower, and average every cover measurement jig is no more than 100 yuans; Employing machinery re-packs, and welds, and makes the good stability of measurement jig, and the degree of distortion of signal reduces; Adopt the related measurement jig of the utility model to save the test duration, improved testing efficiency; E
2the use of PROM makes this measurement jig be applicable to the test of the computing machine of each manufacturers produce.
Claims (5)
1. the measurement jig of a VGA signal, it is characterized in that: described tool comprises D-Sub male interface circuit, impedance matching circuit and resolution memory circuit, wherein said D-Sub male interface circuit comprises that one has 15 D-Sub male interfaces that connect pin, R, G, B, H, V pin in described D-Sub male interface are connected to described impedance matching circuit, the I in described D-Sub male interface
2c bus pin and power pins are connected to described resolution memory circuit, all the other the pin ground connection in described D-Sub male interface.
2. the measurement jig of VGA signal according to claim 1, it is characterized in that: described impedance matching circuit comprises five build-out resistors, the resistance that is wherein connected in the R pin in described D-Sub male interface is configured to 75ohm, the resistance that is connected in the G pin in described D-Sub male interface is configured to 75ohm, the resistance that is connected in the B pin in described D-Sub male interface is configured to 75ohm, the resistance that is connected in the H pin in described D-Sub male interface is configured to 2.2Kohm, the resistance that is connected in the V pin in described D-Sub male interface is configured to 2.2Kohm.
3. the measurement jig of VGA signal according to claim 1, is characterized in that: described resolution memory circuit comprises an E
2pROM, described E
2the I of PROM
2c bus pin is connected to respectively the I in described D-Sub male interface
2c bus pin; And from described E
2the I of PROM
2c bus pin is drawn respectively the 7th resistance, and the 8th resistance is connected to the power pins in described D-Sub male interface; Described E
2the WP pin of PROM is connected to the power pins in described D-Sub male interface through the 9th resistance; Described E
2the power pins of PROM is connected to the power pins in described D-Sub male interface, and through the second electric capacity of parallel connection, the 3rd capacity earth; Described E
2all the other pin ground connection of PROM.
4. the measurement jig of VGA signal according to claim 3, is characterized in that: described E
2the resolution information of pre-stored resolution control information and test use in PROM.
5. the measurement jig of VGA signal according to claim 1, it is characterized in that: described measurement jig also comprises an anti-static circuit, described anti-static circuit comprises five ESD diodes, one end of described five ESD diodes is connected with R, G, B, H, V pin in described D-Sub male interface respectively, its other end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420007401.5U CN203733109U (en) | 2014-01-06 | 2014-01-06 | VGA signal test fixture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420007401.5U CN203733109U (en) | 2014-01-06 | 2014-01-06 | VGA signal test fixture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203733109U true CN203733109U (en) | 2014-07-23 |
Family
ID=51203167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420007401.5U Expired - Lifetime CN203733109U (en) | 2014-01-06 | 2014-01-06 | VGA signal test fixture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203733109U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109425817A (en) * | 2017-08-22 | 2019-03-05 | 鸿富锦精密工业(武汉)有限公司 | Signal test circuit |
| CN110376456A (en) * | 2019-06-27 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of VGA signal testing jig |
-
2014
- 2014-01-06 CN CN201420007401.5U patent/CN203733109U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109425817A (en) * | 2017-08-22 | 2019-03-05 | 鸿富锦精密工业(武汉)有限公司 | Signal test circuit |
| CN110376456A (en) * | 2019-06-27 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of VGA signal testing jig |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140723 |