CN203691278U - Double-load three-phase nine-switch-block MMC (Modular Multilevel Converter) inverter - Google Patents

Double-load three-phase nine-switch-block MMC (Modular Multilevel Converter) inverter Download PDF

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CN203691278U
CN203691278U CN201420056544.5U CN201420056544U CN203691278U CN 203691278 U CN203691278 U CN 203691278U CN 201420056544 U CN201420056544 U CN 201420056544U CN 203691278 U CN203691278 U CN 203691278U
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brachium pontis
switches set
switch unit
power switch
phase
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张波
付坚
丘东元
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South China University of Technology SCUT
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South China University of Technology SCUT
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Abstract

The utility model provides a double-load three-phase nine-switch-block MMC (Modular Multilevel Converter) inverter. The inverter comprises a direct-current power supply, a first bridge arm, a second bridge arm, a third bridge arm, a first three-phase load and a second three-phase load. Each of the first bridge arm, the second bridge arm and the third bridge arm is formed by connecting an upper switch group, a middle switch group, a lower switch group and coupling inductors in series. The three ends of the first three-phase load are connected with the upper ends of the middle switch blocks of the first bridge arm, the second bridge arm and the third bridge arm respectively. The three ends of the second three-phase load are connected with the lower ends of the middle switch blocks of the first bridge arm, the second bridge arm and the third bridge arm respectively. The inverter is controlled by carrier phase-shifting PWM and has two circuits of three-phase alternating-current output of line voltage of 2N+1 level, the voltage stress borne by each switching tube in each power switch unit is only 1/N of the voltage of the direct-current power supply, and the inverter is suitable for high-voltage, large-power, three-phase alternating-current and double-load occasions. Each pair of coupling inductors in the inverter can be replaced by two independent inductors.

Description

Two load three-phase nine switches set MMC inverters
Technical field
The module that relates to the utility model combines many level (MMC) converter field, is specifically related to a kind of dual output three-phase nine switches set MMC inverters.
Background technology
, under this trend, there is the direction of two kinds of improvement converters: reduce passive device or improve converter topology structure to reduce active device as the new development that reduces active device direction at present power inverter forward miniaturization, high reliability and low-loss future development.Three-phase nine switch converters close converter with respect to traditional twelvemo and have reduced three switches and corresponding drive circuit, in the application of considering cost and volume, occupy certain advantage.But the single-phase output of two-way of nine switch converters is two level, output AC waveform is poor.In addition, the half that the voltage stress that in nine switches, each switch bears is DC bus-bar voltage, and there is the voltage-sharing of switching tube, this has limited the application of three-phase nine switch converters in high pressure and large-power occasions greatly.
In recent years, multilevel technology is constantly promoted, and successful Application is at the industrial circle such as such as high voltage direct current transmission, Electric Drive, active power filtering, static synchroballistic, common voltage-type multi-level converter topology is broadly divided into case bit-type and the large class of unit cascaded type two at present.Module combination multi-level converter (Modular Multilevel Converter, MMC) as a kind of novel many level topology, except having advantages of traditional multi-level converter, module combination multi-level converter adopts Modular Structure Design, is convenient to System Expansion and redundancy of effort; Have unbalanced operation ability, fault traversing and recovery capability, system reliability is high; Owing to having common DC bus, module combination multi-level converter is particularly useful for HVDC (High Voltage Direct Current) transmission system application.But, in the time of the alternating current circuit of two different frequencies connected, needing 2 MMC converters, this has increased engineering cost greatly.
Utility model content
The purpose of this utility model is to overcome above-mentioned the deficiencies in the prior art, proposes a kind of dual output three-phase nine switches set MMC inverters.
The technical solution adopted in the utility model is as follows.
Dual output three-phase nine switches set MMC inverters comprise DC power supply, the first brachium pontis, the second brachium pontis, the 3rd brachium pontis, the first threephase load and the second threephase load, described the first brachium pontis, the second brachium pontis and the 3rd brachium pontis are in series by upper switches set, middle switches set, lower switches set and coupling inductance, the upper switches set of the first brachium pontis is in series by N power switch unit, the middle switches set of the first brachium pontis is in series by N power switch unit, the lower switches set of the first brachium pontis is connected by N power switch unit, the upper switches set of the second brachium pontis is in series by N power switch unit, the middle switches set of the second brachium pontis is in series by N power switch unit, the lower switches set of the second brachium pontis is in series by N power switch unit, the upper switches set of the 3rd brachium pontis is in series by N power switch unit, the middle switches set of the 3rd brachium pontis is in series by N power switch unit, the lower switches set of the 3rd brachium pontis is in series by N power switch unit, three ends of the first threephase load are connected with upper end, the upper end of middle switches set of the second brachium pontis and the upper end of the middle switches set of the 3rd brachium pontis of the middle switches set of the first brachium pontis respectively, and three ends of the second threephase load are connected with lower end, the lower end of middle switches set of the second brachium pontis and the lower end of the middle switches set of the 3rd brachium pontis of the middle switches set of the first brachium pontis respectively.The former and deputy limit of the coupling inductance of the coupling inductance of the first brachium pontis, the coupling inductance of the second brachium pontis and the 3rd brachium pontis substitutes by the first inductance and two separate inductors of the second inductance.
In described dual output three-phase nine switches set MMC inverters, the positive pole of DC power supply is connected with upper end, the upper end of upper switches set of the second brachium pontis and the upper end of the upper switches set of the 3rd brachium pontis of the upper switches set of the first brachium pontis; The lower end of the upper switches set of the first brachium pontis is connected with the Same Name of Ends on the former limit of the coupling inductance of the first brachium pontis, the non-same polarity on the former limit of the coupling inductance of the first brachium pontis is connected with the upper end of the middle switches set of the first brachium pontis, the lower end of the middle switches set of the first brachium pontis is connected with the Same Name of Ends of the coupling inductance secondary of the first brachium pontis, and the non-same polarity of the coupling inductance secondary of the first brachium pontis is connected with the upper end of the lower switches set of the first brachium pontis; The structure of the structure of the structure of the second brachium pontis and the 3rd brachium pontis and the first brachium pontis is in full accord; The lower end of the lower end of the lower end of the negative pole of DC power supply and the lower switches set of the first brachium pontis, the lower switches set of the second brachium pontis, the lower switches set of the 3rd brachium pontis and ground end are connected; Three ends of the first threephase load are connected with upper end, the upper end of middle switches set of the second brachium pontis and the upper end of the middle switches set of the 3rd brachium pontis of the middle switches set of the first brachium pontis respectively, and three ends of the second threephase load are connected with lower end, the lower end of middle switches set of the second brachium pontis and the lower end of the middle switches set of the 3rd brachium pontis of the middle switches set of the first brachium pontis respectively.
In above-mentioned dual output three-phase nine switches set MMC inverters, power switch unit is made up of the first switching tube, second switch pipe, the first diode, the second diode and electric capacity; Wherein, the positive pole of electric capacity is connected with the collector electrode of the first switching tube, the negative electrode of the first diode, the emitter of the first switching tube is connected with the anode of the first diode, the collector electrode of second switch pipe, the negative electrode of the second diode, and the emitter of second switch pipe is connected with the anode of the second diode, the negative pole of electric capacity; The collector electrode of second switch pipe is as the first output, and the emitter of second switch pipe is as the second output.
The second output of i power switch unit of each switches set is connected with the first output of i+1 power switch unit, and wherein the value of i is 1～N-1.
In the control method of above-mentioned dual output three-phase nine switches set MMC inverters, adopt phase-shifting carrier wave PWM to control the opening and turn-offing of switching tube of each switches set; I power switch unit of i power switch unit of i power switch unit of i power switch unit of i power switch unit of i power switch unit of the upper switches set of the first brachium pontis, the lower switches set of the first brachium pontis, the upper switches set of the second brachium pontis, the lower switches set of the second brachium pontis, the upper switches set of the 3rd brachium pontis and the lower switches set of the 3rd brachium pontis adopts identical triangular wave as i carrier wave C i, wherein the value of i is 1～N; N carrier wave 360 °/N of lagging phase angle successively; The upper switches set of the first brachium pontis adopts primary sinusoid R authe first direct current biasing R superposes doaas the first modulating wave R of the first brachium pontis au+ R doa, the lower switches set of the first brachium pontis adopts the second sinusoidal wave R buthe second direct current biasing R superposes dobas the second modulating wave R of the first brachium pontis bu+ R dob, the upper switches set of the second brachium pontis adopts the 3rd sinusoidal wave R avthe first direct current biasing R superposes doaas the first modulating wave R of the second brachium pontis av+ R doa, the lower switches set of the second brachium pontis adopts the 4th sinusoidal wave R bvthe second direct current biasing R superposes dobas the second modulating wave R of the second brachium pontis bv+ R dob, the upper switches set of the 3rd brachium pontis adopts the 5th sinusoidal wave R awthe first direct current biasing R superposes doaas the first modulating wave R of the 3rd brachium pontis aw+ R doa, the lower switches set of the 3rd brachium pontis adopts the 6th sinusoidal wave R bwthe second direct current biasing R superposes dobas the second modulating wave R of the 3rd brachium pontis bw+ R dob.
In above-mentioned control method, the first modulating wave R of the first brachium pontis au+ R doawith i carrier wave C iobtain the control level of the second switch pipe gate pole of i power switch unit of the upper switches set of the first brachium pontis by the first comparator, as the first modulating wave R of the first brachium pontis au+ R doabe greater than i carrier wave C itime, the first comparator output high level, as the first modulating wave R of the first brachium pontis au+ R doabe less than i carrier wave C itime, the first comparator output low level, wherein the value of i is 1～N; The second modulating wave R of the first brachium pontis bu+ R dobwith i carrier wave C iobtain the control level of second switch pipe gate pole in i the power switch unit of lower switches set of the first brachium pontis by the second comparator, as the second modulating wave R of the first brachium pontis bu+ R dobbe less than i carrier wave C itime, the second comparator output high level, as the second modulating wave R of the first brachium pontis bu+ R dobbe greater than i carrier wave C itime, the second comparator output low level; In the control level of second switch pipe gate pole of i power switch unit of the upper switches set of the first brachium pontis and i power switch unit of the lower switches set of the first brachium pontis, the control level of second switch pipe gate pole is by the first XOR gate, obtains the control level of second switch pipe gate pole in i the power switch unit of middle switches set of the first brachium pontis; The first modulating wave R of the second brachium pontis av+ R doawith i carrier wave C iobtain the control level of second switch pipe gate pole in i the power switch unit of upper switches set of the second brachium pontis by the 3rd comparator, as the first modulating wave R of the second brachium pontis av+ R doabe greater than i carrier wave C itime, the 3rd comparator output high level, as the first modulating wave R of the second brachium pontis av+ R doabe less than i carrier wave C itime, the 3rd comparator output low level; The second modulating wave R of the second brachium pontis bv+ R dobwith i carrier wave C iobtain the control level of second switch pipe gate pole in i the power switch unit of lower switches set of the second brachium pontis by the 4th comparator, as the second modulating wave R of the second brachium pontis bv+ R dobbe less than i carrier wave C i, the 4th comparator output high level, as the second modulating wave R of the second brachium pontis bv+ R dobbe greater than i carrier wave C i, the 4th comparator output low level; In i power switch unit of the upper switches set of the second brachium pontis, in i power switch unit of the control level of second switch pipe gate pole and the lower switches set of the second brachium pontis, the control level of second switch pipe gate pole by the second XOR gate, obtains the control level of second switch pipe gate pole in i the power switch unit of middle switches set of second brachium pontis; The first modulating wave R of the 3rd brachium pontis aw+ R doawith i carrier wave C iobtain the control level of second switch pipe gate pole in i the power switch unit of upper switches set of the 3rd brachium pontis by the 5th comparator, as the first modulating wave R of the 3rd brachium pontis aw+ R doabe greater than i carrier wave C i, the 5th comparator output high level, as the first modulating wave R of the 3rd brachium pontis aw+ R doabe less than i carrier wave C i, the 5th comparator output low level; The second modulating wave R of the 3rd brachium pontis bw+ R dobwith i carrier wave C iobtain the control level of second switch pipe gate pole in i the power switch unit of lower switches set of the 3rd brachium pontis by the 6th comparator, as the second modulating wave R of the 3rd brachium pontis bw+ R dobbe less than i carrier wave C i, the 6th comparator output high level, as the second modulating wave R of the 3rd brachium pontis bw+ R dobbe greater than i carrier wave C i, the 6th comparator output low level; In i power switch unit of the upper switches set of the 3rd brachium pontis, in i power switch unit of the control level of second switch pipe gate pole and the lower switches set of the 3rd brachium pontis, the control level of second switch pipe gate pole by the 3rd XOR gate, obtains the control level of second switch pipe gate pole in i the power switch unit of middle switches set of the 3rd brachium pontis.
The mode of operation of dual output three-phase nine switches set MMC inverters comprises same pattern and alien frequencies pattern frequently, and in CF pattern, first via output is identical with the frequency of the second tunnel output, and amplitude is not identical; In DF pattern, frequency and the amplitude of first via output and the output of the second tunnel are all not identical.
Compared with prior art, the advantage the utlity model has is: having two-route wire voltage is the three-phase alternating current output of 2N+1 level, output current wave is of high quality, the voltage stress that in power switch unit, each switching tube bears is only the 1/N of DC bus-bar voltage, can guarantee that the voltage that in the converter course of work, all switching tubes bear equates, has well solved the voltage-sharing of switching tube simultaneously.Compare with existing three-phase nine switch converters, the two-way output line voltage of dual output three-phase nine switches set MMC inverters provided by the utility model is 2N+1 level and exchanges output, and the quality of output AC waveform is greatly improved.In addition, the voltage stress bearing of each switching tube is only the 1/N of DC bus-bar voltage, and control method provided by the utility model equates the voltage that in the converter course of work, all switching tubes bear, well solved the voltage-sharing of switching tube, this will be very beneficial for the application of dual output three-phase nine switches set MMC inverters in high pressure and large-power occasions.Compare with existing MMC converter, dual output three-phase nine switches set MMC inverters provided by the utility model have two-way exchange output, can be directly used in two different frequencies alternating current circuit be connected, greatly reduce engineering cost.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of dual output three-phase nine switches set MMC inverters of the present utility model;
Fig. 2 is the circuit structure diagram of the power switch unit of the dual output three-phase nine switches set MMC inverters shown in Fig. 1;
Fig. 3 is the phase-shifting carrier wave PWM control structure figure of the dual output three-phase nine switches set MMC inverters shown in Fig. 1;
Fig. 4 a, 4b are that the dual output three-phase nine switches set MMC inverters shown in Fig. 1 work in respectively the modulating wave under CF pattern and DF pattern;
Fig. 5 a1, Fig. 5 a2,5b1, Fig. 5 b2 are that two load three-phase five level nine switches set MMC inverters work in the simulation waveform figure under CF pattern and DF pattern.
Embodiment
For further setting forth content of the present utility model and feature, below in conjunction with accompanying drawing, concrete enforcement of the present utility model is described, but enforcement of the present utility model is not limited to this.
With reference to figure 1, dual output three-phase nine switches set MMC inverters of the present utility model, comprise DC power supply U dc, the first brachium pontis, the second brachium pontis, the 3rd brachium pontis, the first threephase load and the second threephase load; Described the first brachium pontis, the second brachium pontis and the 3rd brachium pontis are by upper switches set (H u, H v, H w), middle switches set (M u, M v, M w), lower switches set (L u, L v, L w) and coupling inductance (L hu: L lu, L hv: L lv, L hw: L lw) be in series; The upper switches set H of the first brachium pontis uby N power switch unit (SM hu1, SM hu2..., SM huN) be in series, the middle switches set M of the first brachium pontis uby N power switch unit (SM mu1, SM mu2..., SM muN) be in series, the lower switches set L of the first brachium pontis uby N power switch unit (SM lu1, SM lu2..., SM luN) series connection, the upper switches set H of the second brachium pontis vby N power switch unit (SM hv1, SM hv2..., SM hvN) be in series, the middle switches set M of the second brachium pontis vby N power switch unit (SM mv1, SM mv2..., SM mvN) be in series, the lower switches set L of the second brachium pontis vby N power switch unit (SM lv1, SM lv2..., SM lvN) be in series, the upper switches set H of the 3rd brachium pontis wby N power switch unit (SM hw1, SM hw2..., SM hwN) be in series, the middle switches set M of the 3rd brachium pontis wby N power switch unit (SM mw1, SM mw2..., SM mwN) be in series, the lower switches set L of the 3rd brachium pontis wby N power switch unit (SM lw1, SM lw2..., SM lwN) be in series; Three ends of the first threephase load respectively with the middle switches set M of the first brachium pontis uupper end o, the middle switches set M of the second brachium pontis vupper end o and the middle switches set M of the 3rd brachium pontis wupper end o connect, three ends of the second threephase load respectively with the middle switches set M of the first brachium pontis ulower end p, the middle switches set M of the second brachium pontis vlower end p and the middle switches set M of the 3rd brachium pontis wlower end p connect.
DC power supply U dcpositive pole and the upper switches set H of the first brachium pontis uupper end o, the upper switches set H of the second brachium pontis vupper end o and the upper switches set H of the 3rd brachium pontis wupper end o connect; The upper switches set H of the first brachium pontis ulower end p and the coupling inductance (L of the first brachium pontis hu: L lu) former limit L husame Name of Ends w uconnect the coupling inductance (L of the first brachium pontis hu: L lu) former limit L hunon-same polarity a umiddle switches set M with the first brachium pontis uupper end o connect, the middle switches set M of the first brachium pontis ulower end p and the coupling inductance (L of the first brachium pontis hu: L lu) secondary L lusame Name of Ends b uconnect the coupling inductance (L of the first brachium pontis hu: L lu) secondary L lunon-same polarity z ulower switches set L with the first brachium pontis uupper end o connect; The structure of the structure of the structure of the second brachium pontis and the 3rd brachium pontis and the first brachium pontis is in full accord; DC power supply U dcnegative pole and the lower switches set L of the first brachium pontis ulower end p, the lower switches set L of the second brachium pontis vlower end p, the lower switches set L of the 3rd brachium pontis wlower end p be connected with ground end n; Three ends of the first threephase load respectively with the middle switches set M of the first brachium pontis uupper end o, the middle switches set M of the second brachium pontis vupper end o and the middle switches set M of the 3rd brachium pontis wupper end o connect, three ends of the second threephase load respectively with the middle switches set M of the first brachium pontis ulower end p, the middle switches set M of the second brachium pontis vlower end p and the middle switches set M of the 3rd brachium pontis wlower end p connect.
Fig. 2 illustrates the circuit structure of the power switch unit of the three-phase of dual output shown in Fig. 1 nine switches set MMC inverters.Power switch unit is by the first switching tube S 1, second switch pipe S 2, the first diode D 1, the second diode D 2and capacitor C sMform; Wherein, capacitor C sMpositive pole and the first switching tube S 1collector electrode, the first diode D 1negative electrode connect, the first switching tube S 1emitter and the first diode D 1anode, second switch pipe S 2collector electrode, the second diode D 2negative electrode connect, second switch pipe S 2emitter and the second diode D 2anode, capacitor C sMnegative pole connect; Second switch pipe S 2collector electrode as the first output, second switch pipe S 2emitter as the second output.
As shown in Figure 1, the second output of i power switch unit of each switches set is connected with the first output of i+1 power switch unit, and wherein the value of i is 1～N-1.
As shown in Figure 1,
The line voltage of the first threephase load, the second threephase load is respectively:
u uva = u Lu + u Mu - u Hu 2 - u Lv + u Mv - u Hv 2 u vwa = u Lv + u Mv - u Hv 2 - u Lw + u Mw - u Hw 2 u wua = u Lw + u Mw - u Hw 2 - u Lu + u Mu - u Hu 2
u uvb = u Lu - u Mu - u Hu 2 - u Lv - u Mv - u Hv 2 u vwb = u Lv - u Mv - u Hv 2 - u Lw - u Mw - u Hw 2 u wua = u Lw - u Mw - u Hw 2 - u Lu - u Mu - u Hu 2
In formula, u hu, u hv, u hwbe respectively the upper switches set H of the first brachium pontis u, the second brachium pontis upper switches set H vupper switches set H with the 3rd brachium pontis woutput voltage, u mu, u mv, u mwbe respectively the middle switches set M of the first brachium pontis u, the second brachium pontis middle switches set M vmiddle switches set M with the 3rd brachium pontis woutput voltage, u lu, u lv, u lwbe respectively the lower switches set L of the first brachium pontis u, the second brachium pontis lower switches set L vlower switches set L with the 3rd brachium pontis woutput voltage.
Dual output three-phase nine switches set MMC inverters shown in Fig. 1 adopt phase-shifting carrier wave PWM to control, as shown in Figure 3.The upper switches set H of the first brachium pontis ui power switch unit SM hui, the first brachium pontis lower switches set L ui power switch unit SM lui, the second brachium pontis upper switches set H vi power switch unit SM hvi, the second brachium pontis lower switches set L vi power switch unit SM lvi, the 3rd brachium pontis upper switches set H wi power switch unit SM hwilower switches set L with the 3rd brachium pontis wi power switch unit SM lwiadopt identical triangular wave as i carrier wave C i, wherein the value of i is 1～N; N carrier wave C 1, C 2..., C n360 °/N of lagging phase angle successively; The upper switches set H of the first brachium pontis uadopt primary sinusoid R authe first direct current biasing R superposes doaas the first modulating wave R of the first brachium pontis au+ R doa, the lower switches set L of the first brachium pontis uadopt the second sinusoidal wave R buthe second direct current biasing R superposes dobas the second modulating wave R of the first brachium pontis bu+ R dob, the upper switches set H of the second brachium pontis vadopt the 3rd sinusoidal wave R avthe first direct current biasing R superposes doaas the first modulating wave R of the second brachium pontis av+ R doa, the lower switches set L of the second brachium pontis vadopt the 4th sinusoidal wave R bvthe second direct current biasing R superposes dobas the second modulating wave R of the second brachium pontis bv+ R dob, the upper switches set H of the 3rd brachium pontis wadopt the 5th sinusoidal wave R awthe first direct current biasing R superposes doaas the first modulating wave R of the 3rd brachium pontis aw+ R doa, the lower switches set L of the 3rd brachium pontis wadopt the 6th sinusoidal wave R bwthe second direct current biasing R superposes dobas the second modulating wave R of the 3rd brachium pontis bw+ R dob.
The first modulating wave R of the first brachium pontis au+ R doawith i carrier wave C iobtain the upper switches set H of the first brachium pontis by the first comparator ui power switch unit SM huisecond switch pipe S 2the control level S of gate pole hui, as the first modulating wave R of the first brachium pontis au+ R doabe greater than i carrier wave C itime, the first comparator output high level, as the first modulating wave R of the first brachium pontis au+ R doabe less than i carrier wave C itime, the first comparator output low level, wherein the value of i is 1～N; The second modulating wave R of the first brachium pontis bu+ R dobwith i carrier wave C iobtain the lower switches set L of the first brachium pontis by the second comparator ui power switch unit SM luimiddle second switch pipe S 2the control level S of gate pole lui, as the second modulating wave R of the first brachium pontis bu+ R dobbe less than i carrier wave C itime, the second comparator output high level, as the second modulating wave R of the first brachium pontis bu+ R dobbe greater than i carrier wave C itime, the second comparator output low level; The upper switches set H of the first brachium pontis ui power switch unit SM huisecond switch pipe S 2the control level S of gate pole huilower switches set L with the first brachium pontis ui power switch unit SM luimiddle second switch pipe S 2the control level S of gate pole luiby the first XOR gate, obtain the middle switches set M of the first brachium pontis ui power switch unit SM muimiddle second switch pipe S 2the control level S of gate pole mui; The first modulating wave R of the second brachium pontis av+ R doawith i carrier wave C iobtain the upper switches set H of the second brachium pontis by the 3rd comparator vi power switch unit SM hvimiddle second switch pipe S 2the control level S of gate pole hvi, as the first modulating wave R of the second brachium pontis av+ R doabe greater than i carrier wave C itime, the 3rd comparator output high level, as the first modulating wave R of the second brachium pontis av+ R doabe less than i carrier wave C itime, the 3rd comparator output low level; The second modulating wave R of the second brachium pontis bv+ R dobwith i carrier wave C iobtain the lower switches set L of the second brachium pontis by the 4th comparator vi power switch unit SM lvimiddle second switch pipe S 2the control level S of gate pole lvi, as the second modulating wave R of the second brachium pontis bv+ R dobbe less than i carrier wave C i, the 4th comparator output high level, as the second modulating wave R of the second brachium pontis bv+ R dobbe greater than i carrier wave C i, the 4th comparator output low level; The upper switches set H of the second brachium pontis vi power switch unit SM hvimiddle second switch pipe S 2the control level S of gate pole hvilower switches set L with the second brachium pontis vi power switch unit SM lvimiddle second switch pipe S 2the control level S of gate pole lviby the second XOR gate, obtain the middle switches set M of second brachium pontis vi power switch unit SM mvimiddle second switch pipe S 2the control level S of gate pole mvi; The first modulating wave R of the 3rd brachium pontis aw+ R doawith i carrier wave C iobtain the upper switches set H of the 3rd brachium pontis by the 5th comparator wi power switch unit SM hwimiddle second switch pipe S 2the control level S of gate pole hwi, as the first modulating wave R of the 3rd brachium pontis aw+ R doabe greater than i carrier wave C i, the 5th comparator output high level, as the first modulating wave R of the 3rd brachium pontis aw+ R doabe less than i carrier wave C i, the 5th comparator output low level; The second modulating wave R of the 3rd brachium pontis bw+ R dobwith i carrier wave C iobtain the lower switches set L of the 3rd brachium pontis by the 6th comparator wi power switch unit SM lwimiddle second switch pipe S 2the control level S of gate pole lwi, as the second modulating wave R of the 3rd brachium pontis bw+ R dobbe less than i carrier wave C i, the 6th comparator output high level, as the second modulating wave R of the 3rd brachium pontis bw+ R dobbe greater than i carrier wave C i, the 6th comparator output low level; The upper switches set H of the 3rd brachium pontis wi power switch unit SM hwimiddle second switch pipe S 2the control level S of gate pole hwilower switches set L with the 3rd brachium pontis wi power switch unit SM lwimiddle second switch pipe S 2the control level S of gate pole lwiby the 3rd XOR gate, obtain the middle switches set M of the 3rd brachium pontis wi power switch unit SM mwimiddle second switch pipe S 2the control level S of gate pole mwi.
Described control method can guarantee the upper switches set H of the first brachium pontis of described converter u, the first brachium pontis middle switches set M ulower switches set L with the first brachium pontis uat the output voltage u of total N power switch unit of each moment sM=E, the output voltage u of total 2N power switch unit sM=0, meet u hu+ u mu+ u lu=U dc; Guarantee the upper switches set H of the second brachium pontis v, the second brachium pontis middle switches set M vlower switches set L with the second brachium pontis vat the output voltage u of total N power switch unit of each moment sM=E, the output voltage u of total 2N power switch unit sM=0, meet u hv+ u mv+ u lv=U dc; Guarantee the upper switches set H of the 3rd brachium pontis w, the 3rd brachium pontis middle switches set M wlower switches set L with the 3rd brachium pontis wat the output voltage u of total N power switch unit of each moment sM=E, the output voltage u of total 2N power switch unit sM=0, meet u hw+ u mw+ u lw=U dc; Capacitor C in each power switch unit that wherein E is each switches set sMvoltage, and have E=U dc/ N.
Fig. 4 a illustrates that dual output three-phase nine switches set MMC inverters work in the first modulating wave R of the first brachium pontis under CF pattern au+ R doa, the first brachium pontis the second modulating wave R bu+ R dobwith i carrier wave C irelation.Can find out primary sinusoid R from Fig. 4 a auwith the second sinusoidal wave R buelectric voltage frequency identical, and primary sinusoid R auwith the second sinusoidal wave R buvoltage magnitude maximum be 1, wherein the value of i is 1～N.Fig. 4 b illustrates that dual output three-phase nine switches set MMC inverters work in the first modulating wave R of the first brachium pontis under DF pattern au+ R doa, the first brachium pontis the second modulating wave R bu+ R dobwith i carrier wave C irelation.Can find out primary sinusoid R from Fig. 4 b auwith the second sinusoidal wave R buelectric voltage frequency not identical, and primary sinusoid R auwith the second sinusoidal wave R buvoltage magnitude peaked and be 1/2.The first modulating wave R of the second brachium pontis av+ R doa, the 3rd brachium pontis the first modulating wave R aw+ R doathe first modulating wave R with the first brachium pontis au+ R doawith i carrier wave C irelation identical, the second modulating wave R of the second brachium pontis bv+ R dob, the 3rd brachium pontis the second modulating wave R bw+ R dobthe second modulating wave R with the first brachium pontis b1+ R dobwith i carrier wave C irelation identical.
Fig. 5 a1 and Fig. 5 a2 are the simulation waveform figure that dual output three-phase five level nine switches set MMC inverters work in CF pattern, are the three-phase line voltage (u of the first threephase load from top to bottom successively uva, u vwa, u wua), the triple line electric current (i of the first threephase load ua, i va, i wa), the three-phase line voltage (u of the second threephase load uvb, u vwb, u wub) and the triple line electric current (i of the second threephase load ub, i vb, i wb), identical from scheming the line current frequency of visible the first threephase load and the second threephase load, the line current amplitude of the first threephase load and the second threephase load is not identical; Fig. 5 b1, Fig. 5 b2 are the simulation waveform figure that dual output three-phase five level nine switches set MMC inverters work in DF pattern, the three-phase line voltage of the first threephase load, triple line electric current, the three-phase line voltage of the second threephase load and the triple line electric current of the second threephase load of the first threephase load from top to bottom successively, all not identical from scheming line current frequency and the amplitude of visible the first threephase load and the second threephase load.
Above-described embodiment is preferably execution mode of the utility model; but execution mode of the present utility model is not limited by the examples; other any do not deviate from change, the modification done under Spirit Essence of the present utility model and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection range of the present utility model.

Claims (5)

1. dual output three-phase nine switches set MMC inverters, is characterized in that: comprise DC power supply (U dc), the first brachium pontis, the second brachium pontis, the 3rd brachium pontis, the first threephase load and the second threephase load; Described the first brachium pontis, the second brachium pontis and the 3rd brachium pontis are by upper switches set (H u, H v, H w), middle switches set (M u, M v, M w), lower switches set (L u, L v, L w) and coupling inductance (L hu: L lu, L hv: L lv, L hw: L lw) be in series; Upper switches set (the H of the first brachium pontis u) by N power switch unit (SM hu1, SM hu2..., SM huN) be in series, the middle switches set (M of the first brachium pontis u) by N power switch unit (SM mu1, SM mu2..., SM muN) be in series, the lower switches set (L of the first brachium pontis u) by N power switch unit (SM lu1, SM lu2..., SM luN) series connection, the upper switches set (H of the second brachium pontis v) by N power switch unit (SM hv1, SM hv2..., SM hvN) be in series, the middle switches set (M of the second brachium pontis v) by N power switch unit (SM mv1, SM mv2..., SM mvN) be in series, the lower switches set (L of the second brachium pontis v) by N power switch unit (SM lv1, SM lv2..., SM lvN) be in series, the upper switches set (H of the 3rd brachium pontis w) by N power switch unit (SM hw1, SM hw2..., SM hwN) be in series, the middle switches set (M of the 3rd brachium pontis w) by N power switch unit (SM mw1, SM mw2..., SM mwN) be in series, the lower switches set (L of the 3rd brachium pontis w) by N power switch unit (SM lw1, SM lw2..., SM lwN) be in series; Three ends of the first threephase load respectively with the middle switches set (M of the first brachium pontis u) upper end, the middle switches set (M of the second brachium pontis v) upper end and the middle switches set (M of the 3rd brachium pontis w) upper end connect, three ends of the second threephase load respectively with the middle switches set (M of the first brachium pontis u) lower end, the middle switches set (M of the second brachium pontis v) lower end and the middle switches set (M of the 3rd brachium pontis w) lower end connect.
2. dual output three-phase nine switches set MMC inverters according to claim 1, is characterized in that: the coupling inductance (L of the first brachium pontis hu: L lu), the coupling inductance (L of the second brachium pontis hv: L lv) and the coupling inductance (L of the 3rd brachium pontis hw: L lw) former limit and secondary by the first inductance (L hu, L hv, L hw) and the second inductance (L lu, L lv, L lw) two separate inductors substitute.
3. dual output three-phase nine switches set MMC inverters according to claim 1, is characterized in that: DC power supply (U dc) positive pole and the upper switches set (H of the first brachium pontis u) upper end, the upper switches set (H of the second brachium pontis v) upper end and the upper switches set (H of the 3rd brachium pontis w) upper end connect; Upper switches set (the H of the first brachium pontis u) lower end and the coupling inductance (L of the first brachium pontis hu: L lu) former limit (L hu) Same Name of Ends (w u) connect the coupling inductance (L of the first brachium pontis hu: L lu) former limit (L hu) non-same polarity (a u) with the middle switches set (M of the first brachium pontis u) upper end connect, the middle switches set (M of the first brachium pontis u) lower end and the coupling inductance (L of the first brachium pontis hu: L lu) secondary (L lu) Same Name of Ends (b u) connect the coupling inductance (L of the first brachium pontis hu: L lu) secondary (L lu) non-same polarity (z u) with the lower switches set (L of the first brachium pontis u) upper end connect; The structure of the structure of the structure of the second brachium pontis and the 3rd brachium pontis and the first brachium pontis is in full accord; DC power supply (U dc) negative pole and the lower switches set (L of the first brachium pontis u) lower end, the lower switches set (L of the second brachium pontis v) lower end, the lower switches set (L of the 3rd brachium pontis w) lower end be connected with ground end (n); Three ends of the first threephase load respectively with the middle switches set (M of the first brachium pontis u) upper end, the middle switches set (M of the second brachium pontis v) upper end and the middle switches set (M of the 3rd brachium pontis w) upper end connect, three ends of the second threephase load respectively with the middle switches set (M of the first brachium pontis u) lower end, the middle switches set (M of the second brachium pontis v) lower end and the middle switches set (M of the 3rd brachium pontis w) lower end connect.
4. dual output three-phase nine switches set MMC inverters according to claim 1, is characterized in that: power switch unit is by the first switching tube (S 1), second switch pipe (S 2), the first diode (D 1), the second diode (D 2) and electric capacity (C sM) form; Wherein, electric capacity (C sM) positive pole and the first switching tube (S 1) collector electrode, the first diode (D 1) negative electrode connect, the first switching tube (S 1) emitter and the first diode (D 1) anode, second switch pipe (S 2) collector electrode, the second diode (D 2) negative electrode connect, second switch pipe (S 2) emitter and the second diode (D 2) anode, electric capacity (C sM) negative pole connect; Second switch pipe (S 2) collector electrode as the first output, second switch pipe (S 2) emitter as the second output.
5. dual output three-phase nine switches set MMC inverters according to claim 1, it is characterized in that: the second output of i power switch unit of each switches set is connected with the first output of i+1 power switch unit, wherein the value of i is 1 ~ N-1.
CN201420056544.5U 2014-01-28 2014-01-28 Double-load three-phase nine-switch-block MMC (Modular Multilevel Converter) inverter Expired - Lifetime CN203691278U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762874A (en) * 2014-01-28 2014-04-30 华南理工大学 Double-load three-phase nine-switch-block MMC inverter and control method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762874A (en) * 2014-01-28 2014-04-30 华南理工大学 Double-load three-phase nine-switch-block MMC inverter and control method thereof
CN103762874B (en) * 2014-01-28 2017-01-11 华南理工大学 Double-load three-phase nine-switch-block MMC inverter and control method thereof

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