CN203722504U - N-output three-phase 3N+3 switch group MMC inverter - Google Patents

Abstract

The utility model provides an N-output three-phase 3N+3 switch group MMC inverter. The inverter includes a DC power supply, a first bridge arm, a second bridge arm, a third bridge arm, and N three-phase loads; the three bridge arms are all composed of N+1 switch groups and 2 inductors connected in series, Each switch group of each bridge arm is composed of n power switch units in series; the three terminals of the kth three-phase load are respectively connected to the upper ends of the k+1th switch group of the three bridge arms, where k is taken as The value is 1~N-1; the three terminals of the Nth three-phase load are respectively connected to the lower ends of the Nth switch group of the three bridge arms. The inverter adopts carrier phase-shift PWM control, and has a three-phase AC output with N line voltage of 2n+1 level. The voltage stress of each switch tube in the MMC power switch unit is only 1/n of the DC power supply voltage. Suitable for high voltage, high power, three-phase AC dual load occasions.

Description

N output three-phase 3N+3 switch group MMC inverter

technical field

The utility model relates to the field of module combined multilevel (MMC) converters, in particular to an N output three-phase 3N+3 switch group MMC inverter.

Background technique

At present, power converters are developing in the direction of miniaturization, high reliability and low loss. Under this trend, there are two directions for improving the converter: reducing passive components or improving the topology of the converter to reduce active components. New progress in the direction of source devices. Compared with the traditional 6N switching converter, the three-phase 3N+3 switching converter reduces 3N-3 switches and corresponding driving circuits, and has certain advantages in applications considering cost and volume. However, the N single-phase outputs of the 3N+3 switching converter are all two-level, and the output AC waveform is relatively poor. In addition, the voltage stress of each switch in the 3N+3 switches is half of the DC bus voltage, and there is a voltage equalization problem among the 3N+3 switches, which greatly limits the three-phase 3N+3 switching converter in Applications in high voltage and high power occasions.

In recent years, multi-level conversion technology has been continuously promoted, and has been successfully applied in industrial fields such as high-voltage direct current transmission, power transmission, active filtering, and static synchronous compensation. The current common topology of voltage-type multi-level converters can be roughly divided into There are two types of box type and unit cascade type. Modular Multilevel Converter (MMC) is a new type of multilevel topology. In addition to the advantages of traditional multilevel converters, the modular multilevel converter adopts a modular structure design, which is convenient for the system Capacity expansion and redundant work; with unbalanced operation capability, fault ride-through and recovery capability, high system reliability; due to the common DC bus, the module combined multilevel converter is especially suitable for high-voltage direct current transmission system applications. However, when N three-phase AC lines with different frequencies are connected, 2N MMC converters are needed, which greatly increases the engineering cost.

Utility model content

The purpose of the utility model is to overcome the above-mentioned deficiencies in the prior art, and propose an N-output three-phase 3N+3 switch group MMC inverter.

The purpose of this utility model is achieved through the following technical solutions.

N output three-phase 3N+3 switch group MMC inverter includes a DC power supply, a first bridge arm, a second bridge arm, a third bridge arm, and N three-phase loads; the first bridge arm is composed of N+1 switches group and 2 inductors in series, the second bridge arm is composed of N+1 switch groups and 2 inductors in series, and the third bridge arm is composed of N+1 switch groups and 2 inductors in series ; The i-th switch group of the first bridge arm is composed of n power switch units in series, the i-th switch group of the second bridge arm is formed of n power switch units in series, the i-th switch of the third bridge arm The group consists of n power switch units in series, where the value of i is 1 to N+1; the three terminals of the kth three-phase load are respectively connected to the upper end of the k+1th switch group of the first bridge arm, the The upper end of the k+1th switch group of the second bridge arm is connected to the upper end of the k+1th switch group of the third bridge arm, where the value of k is 1 to N-1; the three-phase load of the Nth three-phase load The terminals are respectively connected to the lower end of the Nth switch group of the first bridge arm, the lower end of the Nth switch group of the second bridge arm, and the lower end of the Nth switch group of the third bridge arm; the three terminals of the kth load As the k-th three-phase output, where k ranges from 1 to N, N>2, and n is a positive integer.

In the above-mentioned N-output three-phase 3N+3 switch group MMC inverter, the two inductors of the first bridge arm are coupled to each other to form a pair of coupled inductors; the two inductors of the second bridge arm are coupled to each other to form a pair of coupled inductors ; The two inductors of the third bridge arm are coupled with each other to form a pair of coupled inductors.

In the above-mentioned N output three-phase 3N+3 switch group MMC inverter, the positive pole of the DC power supply is connected to the upper end of the first switch group of the first bridge arm, the upper end of the first switch group of the second bridge arm, and the third The upper end of the first switch group of the bridge arm is connected; the lower end of the first switch group of the first bridge arm is connected with one end of the first inductor of the first bridge arm, and the other end of the first inductor of the first bridge arm It is connected to the upper end of the second switch group of the first bridge arm; the lower end of the i-th switch group of the first bridge arm is connected to the upper end of the i+1th switch group of the first bridge arm, where the value of i is 2～N-1; the lower end of the Nth switch group of the first bridge arm is connected to one end of the second inductance of the first bridge arm, and the other end of the second inductance of the first bridge arm is connected to the The upper end of the N+1th switch group is connected; the circuit structure of the second bridge arm and the circuit structure of the third bridge arm are completely consistent with the circuit structure of the first bridge arm; the three terminals of the kth three-phase load are respectively connected to the first The upper end of the k+1th switch group of the bridge arm, the upper end of the k+1th switch group of the second bridge arm, and the upper end of the k+1th switch group of the third bridge arm are connected, wherein the value of k is 1～N-1; the three terminals of the Nth three-phase load are respectively connected to the lower end of the Nth switch group of the first bridge arm, the lower end of the Nth switch group of the second bridge arm, and the Nth end of the third bridge arm The lower end of a switch group is connected.

In the above-mentioned N-output three-phase 3N+3 switch group MMC inverter, the power switch unit is composed of a first switch tube, a second switch tube, a first diode, a second diode and a capacitor. Wherein, the anode of the capacitor is connected to the collector of the first switch tube and the cathode of the first diode, the emitter of the first switch tube is connected to the anode of the first diode, the collector of the second switch tube, the second two The cathode of the pole tube is connected, the emitter of the second switch tube is connected with the anode of the second diode and the negative pole of the capacitor; the collector of the second switch tube is used as the first output terminal, and the emitter of the second switch tube is used as the second output.

In the above-mentioned N-output three-phase 3N+3 switch group MMC inverter, the second output terminal of the j-th power switch unit of the i-th switch group of the first bridge arm is connected to the i-th switch group of the first bridge arm The first output terminal of the j+1th power switch unit of the second bridge arm is connected to the first output terminal, where j takes a value from 1 to n-1, and i takes a value from 1 to N+1; the jth of the i-th switch group of the second bridge arm The second output end of a power switch unit is connected to the first output end of the j+1th power switch unit of the i-th switch group of the second bridge arm; the j-th power switch unit of the i-th switch group of the third bridge arm The second output end of the power switch unit is connected to the first output end of the j+1th power switch unit of the i-th switch group of the third bridge arm.

In the control method of the above-mentioned N output three-phase 3N+3 switch group MMC inverter, each switch group of the first bridge arm, each switch group of the second bridge arm and each switch group of the third bridge arm are controlled by carrier phase-shift PWM. The turn-on and turn-off of each switch tube of each switch group, where the value of i is 1 to N+1; the j-th power switch unit of the i-th switch group of the first bridge arm, the j-th power switch unit of the second bridge arm Both the j-th power switch unit of the i-th switch group and the j-th power switch unit of the i-th switch group of the third bridge arm use the same triangular wave as the j-th carrier C _j , where the value of j is 1~n ; The phase angle of n carrier waves lags by 360°/n in turn; the end of the first bridge arm of the kth load adopts the kth sine wave R _Luk of the first bridge arm to superimpose the kth DC offset R _dok to obtain the first bridge The kth modulation wave R _Luk +R _dok of the arm, where the value of k is 1 to N; the end of the second bridge arm of the kth load adopts the kth sine wave R _Lvk of the second bridge arm to superimpose the kth The kth modulation wave R _Lvk +R _dok of the second bridge arm is obtained by a DC bias R _dok ; the end of the third bridge arm of the kth load adopts the kth sine wave R _Lwk of the third bridge arm to superimpose the kth The kth modulation wave R _Lwk +R _dok of the third bridge arm is obtained by a DC bias R _dok ; the kth sine wave R _Luk of the first bridge arm, the kth sine wave R _Lvk of the second bridge arm and the The phases of the kth sine wave R _Lwk of the three bridge arms are sequentially different by 120 ^° .

In the above control method, the kth modulation wave R _Luk + R _dok of the first bridge arm and the jth carrier C _j pass through the kth comparator, when the kth modulation wave R _Luk + R _dok of the first bridge arm When it is greater than the j-th carrier C _j , the k-th comparator outputs a high level, and when the k-th modulation wave R _Luk + R _dok of the first bridge arm is smaller than the j-th carrier C _j , the k-th comparator outputs Low level, where the value of k is 1 to N; the output of the first comparator is used as the control level of the second switch gate of the jth power switch unit of the first switch group of the first bridge arm ;The output of the k-1th comparator passes through the k-1th NOT gate, and the output of the k-1th NOT gate and the output of the kth comparator pass through the k-1th XOR gate to obtain the first bridge arm The control level of the second switch gate of the jth power switch unit of the kth switch group, where the value of k is 2 to N; the output of the Nth comparator is obtained through the Nth NOT gate The control level of the second switch gate of the jth power switch unit of the N+1th switch group of a bridge arm; the kth modulation wave R _Lvk +R _dok of the second bridge arm and the jth carrier wave C _j passes through the N+kth comparator, when the kth modulation wave R _Lvk +R _dok of the second bridge arm is greater than the jth carrier C _j , the N+kth comparator outputs a high level, when the When the kth modulation wave R _Lvk +R _dok of the second bridge arm is smaller than the jth carrier C _j , the N+kth comparator outputs a low level, where the value of k is 1 to N; the N+1th The output of the comparator is used as the control level of the second switch gate of the jth power switch unit of the first switch group of the second bridge arm; the output of the N+k-1th comparator is passed through the N+kth -1 NOT gate, the output of the N+k-1th NOT gate and the output of the N+kth comparator pass through the N-1+k-1th XOR gate to get the kth switch of the second bridge arm The control level of the gate of the second switching tube of the jth power switching unit in the group, where the value of k is 2 to N; the output of the 2*Nth comparator is obtained through the 2*Nth NOT gate to obtain the second The control level of the second switch gate of the jth power switch unit of the N+1th switch group of the bridge arm; the kth modulation wave R _Lwk +R _dok of the third bridge arm and the jth carrier C _j passes through the 2*N+k comparator, when the kth modulation wave R _Lwk +R _dok of the third bridge arm is greater than the jth carrier C _j , the 2*N+k comparator outputs a high level , when the kth modulation wave R _Lwk +R _dok of the third bridge arm is smaller than the jth carrier C _j , the 2*N+kth comparator outputs a low level, where the value of k is 1 to N; The output of the 2*N+1th comparator is used as the control level of the second switch gate of the jth power switch unit of the first switch group of the third bridge arm; the 2*N+k-1th The output of the comparator passes through the 2*N+k-1 NOT gate, the output of the 2*N+k-1 NOT gate and the output of the 2*N+k comparator pass through the 2* (N-1)+k-1 XOR gates to obtain the control level of the second switch gate of the j-th power switch unit of the k-th switch group of the third bridge arm, wherein the value of k is 2 ~N; the output of the 3*Nth comparator is passed through the 3*Nth NOT gate to obtain the control voltage of the second switch gate of the jth power switch unit of the N+1th switch group of the third bridge arm flat.

The working modes include the same frequency working mode (CF mode) and different frequency working mode (DF mode). In CF mode, the frequency of N-way three-phase output is the same, but the amplitude is different; in DF mode, the frequency of N-way three-phase output and amplitudes are different.

Compared with the prior art, the utility model has the advantages that: it has an AC output with an N line voltage of 2n+1 level, the output current waveform quality is very high, and the voltage stress that each switch tube in the power switch unit bears is only 1/n of the DC bus voltage, and at the same time, it can ensure that the voltages of all switching tubes are equal during the working process of the converter, which solves the problem of voltage equalization of the switching tubes. Compared with the existing three-phase 3N+3 switching converter, the N-way outputs of the N-output three-phase 3N+3 switch group MMC inverter provided by the utility model are all AC outputs of 2n+1 level line voltage , the quality of the output AC waveform has been greatly improved. In addition, the voltage stress of each switching tube is only 1/n of the DC bus voltage, and the control method provided by the utility model makes the voltages of all switching tubes equal during the working process of the converter, which solves the problem of switching This will be very beneficial to the application of N-output three-phase 3N+3 switch group MMC inverters in high-voltage and high-power occasions. Compared with the existing MMC converter, the N output three-phase 3N+3 switch group MMC inverter provided by the utility model has N three-phase AC outputs, which can be directly used for N three-phase AC lines with different frequencies connection, which greatly reduces the engineering cost.

Description of drawings

Fig. 1 is the circuit structural diagram of N output three-phase 3N+3 switch group MMC inverter of the present utility model;

Fig. 2 is a circuit structure diagram of the switching power unit of the N output three-phase 3N+3 switch group MMC inverter shown in Fig. 1;

Figures 3a to 3c are the carrier phase-shift PWM control structure diagrams of the N-output three-phase 3N+3 switch group MMC inverter shown in Figure 1;

Figures 4a and 4b are the modulation waves of the three-output three-phase twelve-switch group nine-level MMC inverter working in CF mode and DF mode respectively;

Fig. 5a1, Fig. 5a2, Fig. 5a3, Fig. 5b1, Fig. 5b2, Fig. 5b3 are simulation waveform diagrams of three-output three-phase twelve-switch group nine-level MMC inverter working in CF mode and DF mode.

Detailed ways

In order to further illustrate the content and characteristics of the utility model, the specific implementation of the utility model will be described in detail below in conjunction with the accompanying drawings. But the implementation of the present utility model is not limited thereto.

Referring to Fig. 1, the N output three-phase 3N+3 switch group MMC inverter of the present invention includes a DC power supply U _dc , a first bridge arm, a second bridge arm, a third bridge arm, and N three-phase loads; The first bridge arm is composed of N+1 switch groups (B _u1 , B _u2 , ..., _Bu(N+1) ) and two inductors (L _u1 , L _u2 ) connected in series, and the second bridge arm It is composed of N+1 switch groups (B _v1 , B _v2 ,..., B _v(N+1 )) and 2 inductors (Lv1, Lv2) in series, and the third bridge arm is composed of N+1 switch groups (B _w1 , B _w2 ,..., B _w(N+1) ) and two inductors (L _w1 , L _w2 ) in series; the i-th switch group B _ui of the first bridge arm consists of n power switch units (SM _Bui1 , SM _Bui2 , ..., SM _Buin ) are connected in series, and the i-th switch group B _vi of the second bridge arm is formed by connecting n power switch units (SM _Bvi1 , SM _Bvi2 , ..., SM _Bvin ) in series, The i-th switch group B _wi of the third bridge arm is composed of n power switch units (SM _Bwi1 , SM _Bwi2 , ..., SM _Bwin ) in series, where the value of i is 1 to N+1; the k-th three The three terminals of the phase load are respectively connected to the upper end o of the k+1th switch group B _u(k+1) of the first bridge arm, and the upper end o of the k+1th switch group B _v(k+1) of the second bridge arm The upper end o is connected to the upper end o of the k+1th switch group B _w(k+1) of the third bridge arm, where the value of k is 1 to N-1; the three terminals of the Nth three-phase load are respectively connected to The lower end p of the Nth switch group B _uN of the first bridge arm, the lower end p of the Nth switch group B _vN of the second bridge arm, and the lower end p of the Nth switch group B _wN of the third bridge arm are connected; The three terminals of the k loads are used as the k-th three-phase output, where the value of k is 1 to N.

The positive pole of the DC power supply U _dc is connected to the upper end o of the first switch group B _u1 of the first bridge arm, the upper end o of the first switch group B _v1 of the second bridge arm, and the first switch group B of the third bridge arm The upper end o of _w1 is connected; the lower end p of the first switch group B _u1 of the first bridge arm is connected with one end of the first inductor L _u1 of the first bridge arm, and the other end of the first inductor L _u1 of the first bridge arm One end is connected to the upper end o of the second switch group B _u2 of the first bridge arm; the lower end p of the i-th switch group B _ui of the first bridge arm is connected to the i+1th switch group B _{u of the first bridge arm (} The upper end o of _i+1) is connected, where the value of i is 2 to N-1; the lower end p of the Nth switch group B _uN of the first bridge arm is connected to one end of the second inductor L _u2 of the first bridge arm connection, the other end of the second inductance L _u2 of the first bridge arm is connected to the upper end o of the N+1th switch group B _u(N+1) of the first bridge arm; the circuit structure of the second bridge arm, the first The circuit structure of the three bridge arms is exactly the same as that of the first bridge arm; the three terminals of the kth three-phase load are respectively connected to the upper end of the k+1th switch group _Bu(k+1) of the first bridge arm o , the upper end o of the k+1th switch group Bv(k+1) of the second bridge arm, and the upper end o of the k+1th switch group _Bw(k+1) of the third bridge arm are connected, wherein k The value is 1 to N-1; the three terminals of the Nth three-phase load are respectively connected to the lower end p of the Nth switch group B _uN of the first bridge arm, and the lower end of the Nth switch group B _vN of the second bridge arm p. The lower end p of the Nth switch group B _wN of the third bridge arm is connected.

FIG. 2 shows a circuit structure diagram of a switching power unit of the N-output three-phase 3N+3 switch group MMC inverter shown in FIG. 1 . The power switch unit is composed of a first switch tube S ₁ , a second switch tube S ₂ , a first diode D ₁ , a second diode D ₂ and a capacitor C _SM . Wherein, the anode of the capacitor _CSM is connected to the collector of the first switching transistor _S1 and the cathode of the first diode _D1 , and the emitter of the first switching transistor _S1 is connected to the anode of the first diode D1 and the first diode _D1 . The collector of the second switching tube _S2 is connected to the cathode of the second diode _D2 , and the emitter of the second switching tube _S2 is connected to the anode of the second diode _D2 and the negative pole of the capacitor _CSM ; the second switch The collector of the transistor _S2 serves as the first output terminal, and the emitter of the second switching transistor _S2 serves as the second output terminal.

As shown in Figure 1, the second output terminal of the jth power switch unit SM Buij of the i-th switch group B _ui of the first bridge arm is connected to the j+1th power switch unit SM _Buij of the i-th switch group B _ui of the first bridge arm The first output terminal of a power switch unit S _MBui(j+1) is connected, where j takes a value from 1 to n-1, and i takes a value from 1 to N+1; the i-th switch group Bvi of the second bridge arm The second output end of the jth power switch unit SM _Bvij of the second bridge arm is connected to the first output end of the j+1th power switch unit SM _Bvi(j+1) of the ith switch group Bvi of the second bridge arm; The second output terminal of the j-th power switch unit SM _Bvij of the i-th switch group Bvi of the three-bridge arm and the j+1-th power switch unit SM _{Bvi(j+ 1)} The first output terminal is connected.

As shown in Figure 1, the k-way AC output line voltage is:

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; uvk</span>}}<span\; class="notranslate">\; =</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; K</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bui</span>}}<span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bui</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bvi</span>}}<span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bvi</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1,2</span>}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; vwk</span>}}<span\; class="notranslate">\; =</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; K</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bui</span>}}<span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bui</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bvi</span>}}<span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bvi</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1,2</span>}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; wuk</span>}}<span\; class="notranslate">\; =</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; K</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bui</span>}}<span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bui</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; k</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bvi</span>}}<span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Bvi</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1,2</span>}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

In formulas (1) to (3), u _Bui is the output voltage of the i-th switch group of the first bridge arm, u _Bvi is the output voltage of the i-th switch group of the second bridge arm, and u Bwi is the output voltage of the i-th switch group of the second bridge arm, and u _Bwi is the output voltage of the third bridge arm The output voltage of the ith switch group of the arm.

The N-output three-phase 3N+3 switch group MMC inverter shown in Figure 1 adopts carrier phase-shift PWM control, as shown in Figure 3a to Figure 3c. The j-th power switch unit SM _Bu i _j of the i-th switch group _Bui of the first bridge arm, the j-th power switch unit SM Bvij of the i-th switch group Bvi of the second bridge arm, and the j-th power switch unit SM _Bvij of the third bridge arm The j-th power switch unit SM _Bwij of the i-th switch group B _wi uses the same triangular wave as the j-th carrier C _j , where i takes a value from 1 to N+1, and j takes a value from 1 to n; n The carrier wave (C ₁ , C ₂ ,..., C _n ) lags behind the phase angle by 360°/n in turn; the terminal a _uk of the first bridge arm of the kth load adopts the kth sine wave R _Luk of the first bridge arm to superimpose the first k DC bias R _dok to obtain the kth modulated wave R _Luk +R _dok of the first bridge arm, where the value of k is 1 to N; the terminal a _vk of the second bridge arm of the kth load adopts the second The kth sine wave R _Lvk of the bridge arm superimposes the kth DC offset R _dok to obtain the kth modulation wave R _Lvk +R _dok of the second bridge arm; the terminal a _wk of the third bridge arm of the kth load adopts The kth sine wave R _Lwk of the third bridge arm superimposes the kth DC offset R _dok to obtain the kth modulation wave R _Lwk +R _dok of the third bridge arm; the kth sine wave R _Luk of the first bridge arm , The kth sine wave R _Lvk of the second bridge arm and the kth sine wave R _Lwk of the third bridge arm have a phase difference of 120° in sequence.

The control method can ensure that each bridge arm of the converter has output voltage u _SM =E of n power switch units at each moment, and output voltage u _SM =0 of N*n power switch units, that is, satisfies and Where E is the voltage on the capacitor C _SM in each power switch unit, and E=U _dc /n.

Taking the three-output three-phase twelve-switch group nine-level MMC inverter as an example, Figure 4a shows the first modulation wave R _Lu1 +R _do1 of the first bridge arm and the first bridge arm’s The relationship between the second modulated wave R _Lu2 +R _do1 , the third modulated wave R _Lu3 +R _do1 of the first bridge arm, and the j-th carrier C _j . It can be seen from Figure 4a that the frequency of the first sine wave R _Lu1 of the first bridge arm, the second sine wave R _Lu2 of the first bridge arm and the third sine wave R _Lu3 of the first bridge arm are the same, and the amplitude The values are not the same. Figure 4b shows the first modulation wave R _Lu1 +R _do1 of the first bridge arm, the second modulation wave R _Lu2 +R _do1 of the first bridge arm, and the third modulation wave of the first bridge arm when it works in DF mode The relationship between the modulated wave R _Lu3 +R _do1 and the jth carrier C _j . It can be seen from Figure 4b that the frequencies and amplitudes of the first sine wave R _Lu1 of the first bridge arm, the second sine wave R _Lu2 of the first bridge arm and the third sine wave R _Lu3 of the first bridge arm All are different. The first and first modulation wave R _Lv1 +R _do1 of the second bridge arm, the second modulation wave R _Lv2 +R _do1 of the second bridge arm, the third modulation wave R _Lv3 +R _do1 of the second bridge arm The relationship with the jth carrier C _j and the first modulation wave R _Lu1 +R _do1 of the first bridge arm, the second modulation wave R _Lu2 +R _do1 of the first bridge arm, the third modulation wave of the first bridge arm The relationship between the first modulation wave R _Lu3 +R _do1 and the jth carrier C _j is exactly the same; the first modulation wave R _Lw1 +R _do1 of the third bridge arm, the second modulation wave R of the third bridge arm _Lw2 +R _do1 , the relationship between the third modulation wave R _Lw3 +R _do1 of the third bridge arm and the jth carrier C _j and the first modulation wave R _Lu1 +R _do1 of the first bridge arm, the first bridge The relationship between the second modulating wave R _Lu2 +R _do1 of the bridge arm, the third modulating wave R _Lu3 +R _do1 of the first bridge arm and the jth carrier C _j is exactly the same.

Figure 5a1, Figure 5a2, and Figure 5a3 are the simulation waveform diagrams of the three-output three-phase twelve-switch group nine-level MMC inverter working in CF mode, which are the three line voltages of the first three-phase load, the first 3 line currents of 3-phase load, 3 line-to-line voltages of 2nd 3-phase load, 3 line currents of 2nd 3-phase load, 3 line-to-line voltages of 3rd 3-phase load and 3rd 3-phase The three line currents of the load, it can be seen from the figure that the line current frequency of the first three-phase load, the second three-phase load and the third three-phase load are the same, the first three-phase load, the second three-phase load and the The line current amplitude of the third three-phase load is different; Figure 5b1, Figure 5b2, and Figure 5b3 are the simulation waveform diagrams of the three-output three-phase twelve-switch group nine-level MMC inverter working in DF mode, followed by the first 3 line voltages for 1 three-phase load, 3 line currents for the first three-phase load, 3 line voltages for the second three-phase load, 3 line currents for the second three-phase load, 3 line currents for the 3rd three-phase load The 3 line voltages of the three-phase load and the 3 line currents of the third three-phase load, the current frequency and amplitude of the first three-phase load, the second three-phase load and the third three-phase load can be seen from the figure All are different.

The above-mentioned embodiment is a preferred implementation mode of the present utility model, but the implementation mode of the present utility model is not limited by the described embodiment, and any other changes, modifications, modifications, Substitution, combination, and simplification should all be equivalent replacement methods, and are all included in the protection scope of the present utility model.

Claims (5)

1.N output three-phase 3N+3 switches set MMC inverter, is characterized in that: comprise DC power supply (U _dc), the first brachium pontis, the second brachium pontis, the 3rd brachium pontis and N threephase load; Described the first brachium pontis is by N+1 switches set (B _u1, B _u2..., B _{u (N+1)}) and 2 inductance (L _u1, L _u2) be in series, described the second brachium pontis is by N+1 switches set (B _v1, B _v2..., B _{v (N+1)}) and 2 inductance (L _v1, L _v2) be in series, described the 3rd brachium pontis is by N+1 switches set (B _w1, B _w2..., B _{w (N+1)}) and 2 inductance (L _w1, L _w2) be in series; I switches set (B of the first brachium pontis _ui) by n power switch unit (SM _bui1, SM _bui2..., SM _buin) be in series, i switches set (B of the second brachium pontis _vi) by n power switch unit (SM _bvi1, SM _bvi2..., SM _bvin) be in series, i switches set (B of the 3rd brachium pontis _wi) by n power switch unit (SM _bwi1, SM _bwi2..., SM _bwin) be in series, wherein the value of i is 1 ~ N+1; Three ends of k threephase load respectively with k+1 switches set (B of the first brachium pontis _{u (k+1)}) upper end (o), k+1 switches set (B of the second brachium pontis _{v (k+1)}) upper end (o), k+1 switches set (B of the 3rd brachium pontis _{w (k+1)}) upper end (o) connect, wherein the value of k is 1 ~ N-1; Three ends of N threephase load respectively with N switches set (B of the first brachium pontis _uN) lower end (p), N switches set (B of the second brachium pontis _vN) lower end (p), N switches set (B of the 3rd brachium pontis _wN) lower end (p) connect; Three ends of k load are as the output of k road three-phase, and wherein the value of k is 1 ~ N, N>2, and n is positive integer.

2. N output three-phase 3N+3 switches set MMC inverter according to claim 1, is characterized in that: two inductance (L of the first brachium pontis _u1, L _u2) intercouple, form a pair of coupling inductance; Two inductance (L of the second brachium pontis _v1, L _v2) intercouple, form a pair of coupling inductance; Two inductance (L of the 3rd brachium pontis _w1, L _w2) intercouple, form a pair of coupling inductance.

3. N output three-phase 3N+3 switches set MMC inverter according to claim 1, is characterized in that: DC power supply (U _dc) positive pole and the 1st switches set (B of the first brachium pontis _u1) upper end (o), the 1st switches set (B of the second brachium pontis _v1) upper end (o), the 1st switches set (B of the 3rd brachium pontis _w1) upper end (o) connect; The 1st switches set (B of the first brachium pontis _u1) the 1st inductance (L of lower end (p) and the first brachium pontis _u1) one end connect, the 1st inductance (L of the first brachium pontis _u1) the other end and the 2nd switches set (B of the first brachium pontis _u2) upper end (o) connect; I switches set (B of the first brachium pontis _ui) i+1 switches set (B of lower end (p) and the first brachium pontis _{u (i+1)}) upper end (o) connect, wherein the value of i is 2 ~ N-1; N switches set (B of the first brachium pontis _uN) the 2nd inductance (L of lower end (p) and the first brachium pontis _u2) one end connect, the 2nd inductance (L of the first brachium pontis _u2) the other end and N+1 switches set (B of the first brachium pontis _{u (N+1)}) upper end (o) connect; The circuit structure of the circuit structure of the second brachium pontis, the circuit structure of the 3rd brachium pontis and the first brachium pontis is in full accord; Three ends of k threephase load respectively with k+1 switches set (B of the first brachium pontis _{u (k+1)}) upper end (o), k+1 switches set (B of the second brachium pontis _{v (k+1)}) upper end (o), k+1 switches set (B of the 3rd brachium pontis _{w (k+1)}) upper end (o) connect, wherein the value of k is 1 ~ N-1; Three ends of N threephase load respectively with N switches set (B of the first brachium pontis _uN) lower end (p), N switches set (B of the second brachium pontis _vN) lower end (p), N switches set (B of the 3rd brachium pontis _wN) lower end (p) connect.

4. N output three-phase 3N+3 switches set MMC inverter according to claim 1, is characterized in that: power switch unit is by the first switching tube (S ₁), second switch pipe (S ₂), the first diode (D ₁), the second diode (D ₂) and electric capacity (C _sM) form, wherein, electric capacity (C _sM) positive pole and the first switching tube (S ₁) collector electrode, the first diode (D ₁) negative electrode connect, the first switching tube (S ₁) emitter and the first diode (D ₁) anode, second switch pipe (S ₂) collector electrode, the second diode (D ₂) negative electrode connect, second switch pipe (S ₂) emitter and the second diode (D ₂) anode, electric capacity (C _sM) negative pole connect; Second switch pipe (S ₂) collector electrode as the first output, second switch pipe (S ₂) emitter as the second output.

5. N output three-phase 3N+3 switches set MMC inverter according to claim 1, is characterized in that: i switches set (B of the first brachium pontis _ui) j power switch unit (SM _buij) the second output and i switches set (B of the first brachium pontis _ui) j+1 power switch unit (SM _{bui (j+1)}) first output connect, wherein j value is 1 ~ n-1, i value is 1 ~ N+1; I switches set (B of the second brachium pontis _vi) j power switch unit (SM _bvij) the second output and i switches set (B of the second brachium pontis _vi) j+1 power switch unit (SM _{bvi (j+1)}) first output connect; I switches set (B of the 3rd brachium pontis _vi) j power switch unit (SM _bvij) the second output and i switches set (B of the 3rd brachium pontis _vi) j+1 power switch unit (SM _{bvi (j+1)}) first output connect.