CN203674213U - Series-connection boosting solar cell unit - Google Patents

Series-connection boosting solar cell unit Download PDF

Info

Publication number
CN203674213U
CN203674213U CN201420017192.2U CN201420017192U CN203674213U CN 203674213 U CN203674213 U CN 203674213U CN 201420017192 U CN201420017192 U CN 201420017192U CN 203674213 U CN203674213 U CN 203674213U
Authority
CN
China
Prior art keywords
substrate
solar cell
type
prepared
active area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201420017192.2U
Other languages
Chinese (zh)
Inventor
谢生
毛陆虹
张世林
侯贺刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin University
Original Assignee
Tianjin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University filed Critical Tianjin University
Priority to CN201420017192.2U priority Critical patent/CN203674213U/en
Application granted granted Critical
Publication of CN203674213U publication Critical patent/CN203674213U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

The utility model relates to a series-connection boosting solar cell unit. Shallow trench isolation zones are prepared on a lightly doped P- type silicon substrate; a medium doped N well is prepared in a device active zone between the shallow trench isolation zones; a large-area and heavily doped P+ active zone is prepared in an N type base by using the ion implantation technology; a heavily doped N+ contact zone is prepared on the N type base at the outer side of the P+ active zone by using the ion implantation technology; a dielectric layer of proper thickness is deposited on the surface of the wafer; anodic electrodes and cathodic electrodes of the two solar cells are prepared on the upper surface of the device; and an anode and a cathode of the series-connection boosting solar cell unit are manufactured. The series-connection boosting solar cell unit provided by the utility model is mainly applied to design and manufacture of solar cells.

Description

Series boosting solar battery cell
Technical field
The utility model belongs to technical field of solar, relates to micro solar battery structure a kind of and complementary metal oxide semiconductors (CMOS) (CMOS) process compatible; Relate to the preparation method that series of standards CMOS technologies such as utilizing oxidation, photoetching, etching, Implantation, metallization realizes this kind of device, specifically, relate to series boosting solar battery cell and preparation method thereof.
Background technology
Along with global ecological environment constantly worsens, and traditional fossil energy worsening shortages, in the urgent need to a kind of clean, pollution-free and supply with abundant new forms of energy and promote human civilization and socioeconomic sustainable development, this has become one of problem in science that countries in the world give more sustained attention and constantly explore.
Along with the lasting reduction of integrated circuit technology node, for the micro-system of the periodic duty such as radio-frequency (RF) identification and radio sensing network node, operating voltage and the power consumption of System on Chip/SoC constantly reduce.Therefore,, for above-described micro-power consumption system chip, the supply certainly that utilizes external environment energy to realize the system energy becomes possibility.At present, academia has reported the multiple kinds of energy obtain manners such as employing mechanical oscillation, temperature gradient and solar energy.Compared with other energy harvesting modes, solar cell conversion efficiency using light as energy source is high, technology maturation, without AC-DC conversion, is a kind of inexhaustible, nexhaustible environmental protection energy.
Can realize the supply certainly of the electronic system energy although adopt conventional discrete solar battery cell, but the conventional manufacturing process of solar cell makes it cannot be integrated with the electronic circuit monolithic based on standard CMOS process, thereby the volume of total system is large, cost is high, be difficult to adapt to microminiaturized growth requirement.
Summary of the invention
For overcoming the deficiencies in the prior art, realize the energy automatic acquisition of micro-power consumption system chip of the periodic duty such as radio-frequency (RF) identification, radio sensing network node, the technical solution adopted in the utility model is that series boosting solar battery cell preparation method, comprises the steps:
1) at lightly doped P -on type silicon substrate, prepare shallow channel isolation area, its effect is to realize between solar cell, and electric isolation between solar cell and CMOS electronic circuit, avoids influencing each other;
2) in the device active region between shallow channel isolation area, prepare the N trap of a medium-doped, this region is as P +/ N trap type solar cell D 1n-type substrate;
3) utilize ion implantation technology in N-type substrate, to prepare a large area, heavily doped P +active area is prepared a substrate contact region, described P simultaneously on substrate +active area and N-type substrate form P +/ N trap type solar cell D 1;
4) utilize ion implantation technology at described P +in the N-type substrate in outside, active area, prepare heavily doped N +contact zone, prepares heavily doped N simultaneously on the basolateral substrate of N-type +active area, described N +active area and P type substrate form N +/ P substrate-type solar cell D 2;
5) at the dielectric layer of wafer surface deposit suitable thickness, described dielectric layer doubles as the anti-reflective film of solar cell simultaneously, increases the incident efficiency of sunlight;
6) utilize photoetching and metallization process step, prepare anode electrode and the cathode electrode of described two kinds of solar cells at device upper surface;
7) utilize interconnection process by P +/ N trap type solar cell D 1cathode electrode and N +/ P substrate-type solar cell D 2anode electrode short circuit connect, and by P +/ N trap type solar cell D 1anode electrode and N +/ P substrate-type solar cell D 2cathode electrode draw, respectively as anode and the negative electrode of series boosting battery unit.
At the P in <100> crystal orientation -the silica of deposit 50nm and 200nm silicon nitride medium layer successively on type silicon substrate, then adopt photoetching, etching technics step in standard CMOS process to define shallow channel isolation area, gash depth is at 0.5～1 μ m, groove width is 0.5 μ m, adopt high-density plasma chemical vapor deposition technology (HDP CVD) deposited oxide filling groove, the thickness of oxide slightly exceedes gash depth, finally implement overall situation leveling by CMP (Chemical Mechanical Polishing) process, remove surface nitrogen SiClx with hot phosphoric acid, prepare shallow channel isolation area.
Carry out the N-type substrate photoetching of solar cell to preparing the substrate of shallow trench isolation region, the window area of N-type substrate is 50 × 50 μ m 2, utilize the N trap injection of standard CMOS process to carry out N-type doping and annealing heat treatment to described window, the average doping content in described region is 1 × 10 17cm -3, the degree of depth is about 1 μ m.
The P of photoetching solar cell +active area window and substrate contact region window, utilize the transistorized P of PMOS in standard CMOS process +source/leakage is injected described P +the heat treatment of adulterating and anneal of active area and substrate contact region, the average doping content in described region is 1 × 10 19cm -3, junction depth is about 0.1～0.2 μ m.
Make N trap contact zone and the N of solar cell by lithography +active area, utilizes the N of nmos pass transistor in standard CMOS process +source/leakage is injected described N trap contact zone and N +the active area heat treatment of adulterating and anneal, the average doping content in described region is 1 × 10 19cm -3, junction depth is about 0.1～0.2 μ m.
By high-density plasma chemical vapor deposition technology (HDP CVD) at surface deposition one deck compact structure, thickness the silica medium layer at 80～140nm, described deielectric-coating doubles as the anti-reflective film of solar cell simultaneously, for strengthening the incident efficiency of 400～800nm scope solar spectrum; Utilize contact hole mask plate to carry out photoetching, and on dielectric layer, etch several P with reactive ion etching technology +active area, N trap contact zone, N +the contact hole of active area and substrate contact region, contact hole area is 0.5 × 0.5 μ m 2.
Utilize sputtering deposit technology in the thick silicide metals of surface deposition 50nm, and carry out rapid thermal treatment, form silicide, reduce contact resistance.Described silicide metals includes, but are not limited to Ti, Co, W and Ni; Adopt hydrogen peroxide and sulfuric acid mixture liquid to corrode unreacted Ti, Co, the metals such as W or Ni; Deposition of electrode metal material, and adopt the metallization process of standard CMOS to prepare P +/ N trap type solar cell D 1anode electrode and cathode electrode, and N +/ P substrate-type solar cell D 2anode electrode and cathode electrode, described electrode metal material includes, but are not limited to Al, Cu, W, Pt, TaN and combination thereof or alloy.
Series boosting solar battery cell, at lightly doped P -on type silicon substrate, be prepared with shallow channel isolation area, be prepared with the N trap of medium-doped in the active area between shallow channel isolation area, this region is as P +/ N trap type solar cell D 1n-type substrate; In N-type substrate, be prepared with large area, heavily doped P +active area is prepared with substrate contact region, described P simultaneously on substrate +active area and N-type substrate form P +/ N trap type solar cell D 1; At described P +in the N-type substrate in outside, active area, be prepared with heavily doped N +contact zone, is prepared with heavily doped N simultaneously on the basolateral substrate of N-type +active area, described N +active area and P type substrate form N +/ P substrate-type solar cell D 2; At surface deposition dielectric layer, described dielectric layer doubles as the anti-reflective film of solar cell simultaneously, increases the incident efficiency of sunlight; Be prepared with anode electrode and the cathode electrode of described two kinds of solar cells in surface portion; The cathode electrode of P+/N trap type solar cell D1 is connected with the anode electrode short circuit of N+/P substrate-type solar cell D2, the anode electrode of P+/N trap type solar cell D1 and the cathode electrode of N+/P substrate-type solar cell D2 are drawn, respectively as anode and the negative electrode of series boosting battery unit.
Be silica medium layer at surface deposition dielectric layer, on dielectric layer, be etched with several P +active area, N trap contact zone, N +the contact hole of active area and substrate contact region, contact hole area is 0.5 × 0.5 μ m 2.
Technical characterstic of the present utility model and effect:
1, the solar battery cell the utility model proposes utilizes the design feature of standard CMOS process to carry out Design and implementation, in NMOS and PMOS device preparation process, can realize P +/ N trap, N +the PN junction type solar cell of the various structures such as P substrate and N trap/P substrate, without the extra manufacturing process that increases.
2, described solar cell preparation technology and CMOS electronic circuitry process are completely compatible, and the monolithic that can realize micro solar battery and electronic circuit on same chip is integrated, reduce system bulk and cost, improve integrated level.
3, the solar battery cell the utility model proposes can be realized series boosting, more than Open Output Voltage reaches 0.9V, is expected to directly drive Low-voltage Electronic circuit, avoids the increasing apparatus such as charge pump, simplifies electric power system.
Brief description of the drawings
Fig. 1: the equivalent circuit diagram of the series boosting unit the utility model proposes.
Fig. 2: P of the present utility model +/ N trap type and N +/ P substrate-type solar cell series boosting unit section figure.
Fig. 3: P of the present utility model +/ N trap type and N +/ P substrate-type solar cell series boosting unit top view.
Embodiment
If adopt with micro solar battery and micro-power consumption system chip monolithic of standard CMOS process compatibility integrated, can realize on sheet and powering, reduce system bulk and cost, make again the integrated level of system and function improve constantly, realize the self-contained electric system chip of real meaning.
In order to overcome, conventional solar cell volume is large, high in cost of production unfavorable factor, realize the energy automatic acquisition of micro-power consumption system chip of the periodic duty such as radio-frequency (RF) identification, radio sensing network node, the utility model proposes on a kind of sheet of and standard CMOS process compatibility the integrated series solar battery cell that boosts, this battery unit is expected to directly drive the low pressure such as radio-frequency (RF) identification, radio sensing network node, micro-power consumption electronic system.
The series boosting solar battery cell the utility model proposes as shown in Figure 1, by P +/ N trap type solar cell D 1and N +/ P substrate-type solar cell D 2connected in series, realize output voltage multiplication.Specifically can be achieved by following technical solution:
1) at lightly doped P -on type silicon substrate, prepare shallow channel isolation area, its effect is to realize between solar cell, and electric isolation between solar cell and CMOS electronic circuit, avoids influencing each other.
2) in the device active region between shallow channel isolation area, prepare the N trap of a medium-doped, this region is as P +/ N trap type solar cell D 1n-type substrate.
3) utilize ion implantation technology in N-type substrate, to prepare a large area, heavily doped P +active area is prepared a substrate contact region, described P simultaneously on substrate +active area and N-type substrate form P +/ N trap type solar cell D 1.
4) utilize ion implantation technology at described P +in the N-type substrate in outside, active area, prepare heavily doped N +contact zone, prepares heavily doped N simultaneously on the basolateral substrate of N-type +active area, described N +active area and P type substrate form N +/ P substrate-type solar cell D 2.
5) at the dielectric layer of wafer surface deposit suitable thickness, described dielectric layer doubles as the anti-reflective film of solar cell simultaneously, increases the incident efficiency of sunlight.
6) utilize photoetching and metallization process step, prepare anode electrode and the cathode electrode of described two kinds of solar cells at device upper surface.
7) utilize interconnection process by P +/ N trap type solar cell D 1cathode electrode and N +/ P substrate-type solar cell D 2anode electrode short circuit connect, and by P +/ N trap type solar cell D 1anode electrode and N +/ P substrate-type solar cell D 2cathode electrode draw, respectively as anode and the negative electrode of series boosting battery unit.
Below in conjunction with accompanying drawing 2 and accompanying drawing 3, to P +/ N trap type and N +the preparation technology of/P substrate-type solar cell series boosting unit is described in detail.
1, at the P in <100> crystal orientation -the silica of deposit 50nm and 200nm silicon nitride medium layer successively on type silicon substrate 1, then adopt the processing step such as photoetching, etching in standard CMOS process to define shallow channel isolation area 2, gash depth is at 0.5～1 μ m, groove width is 0.5 μ m, adopt high-density plasma chemical vapor deposition technology (HDP CVD) deposited oxide filling groove, the thickness of oxide slightly exceedes gash depth, finally implement overall situation leveling by CMP (Chemical Mechanical Polishing) process, remove surface nitrogen SiClx with hot phosphoric acid, prepare shallow channel isolation area 2.
2, carry out the N-type substrate photoetching of solar cell to preparing the substrate 1 of shallow trench isolation region 2, the window area of N-type substrate 3 is 50 × 50 μ m 2, utilize the N trap injection of standard CMOS process to carry out N-type doping and annealing heat treatment to described window, the average doping content in described region is 1 × 10 17cm -3, the degree of depth is about 1 μ m.
3, the P of photoetching solar cell +active area 4 windows and substrate contact region 7 windows, utilize the transistorized P of PMOS in standard CMOS process +source/leakage is injected described P +the heat treatment of adulterating and anneal of active area 4 and substrate contact region 7, the average doping content in described region is 1 × 10 19cm -3, junction depth is about 0.1～0.2 μ m.
4, make N trap contact zone 5 and the N of solar cell by lithography + active area 6, utilizes the N of nmos pass transistor in standard CMOS process +source/leakage is injected described N trap contact zone 5 and N + active area 6 heat treatment of adulterating and anneal, the average doping content in described region is 1 × 10 19cm -3, junction depth is about 0.1～0.2 μ m.
5, by high-density plasma chemical vapor deposition technology (HDP CVD) at wafer surface deposit one deck compact structure, thickness the silica medium layer 8 at 80～140nm, described deielectric-coating 8 doubles as the anti-reflective film of solar cell simultaneously, for strengthening the incident efficiency of 400～800nm scope solar spectrum; Utilize contact hole mask plate to carry out photoetching, and on dielectric layer 8, etch several P with reactive ion etching technology +active area 4, N trap contact zone 5, N +the contact hole of active area 6 and substrate contact region 7, contact hole area is 0.5 × 0.5 μ m 2.
6, utilize sputtering deposit technology in the thick silicide metals of upper wafer surface deposit 50nm, and carry out rapid thermal treatment, form silicide, reduce contact resistance.Described silicide metals includes, but are not limited to Ti, Co, W and Ni.
7, adopt hydrogen peroxide and sulfuric acid mixture liquid to corrode unreacted Ti, Co, the metals such as W or Ni.
8, deposition of electrode metal material, and adopt the metallization process of standard CMOS to prepare P +/ N trap type solar cell D 1anode electrode 9 and cathode electrode 10, and N +/ P substrate-type solar cell D 2anode electrode 11 and cathode electrode 12.Described electrode metal material includes, but are not limited to Al, Cu, W, Pt, TaN and combination thereof or alloy.
9, adopt the interconnection process of standard CMOS process to realize P +/ N trap type solar cell D 1cathode electrode 10 and N +/ P substrate-type solar cell D 2anode electrode 11 short circuits connect, and by P +/ N trap type solar cell D 1anode electrode 9 and N +/ P substrate-type solar cell D 2cathode electrode 12 draw, respectively as anode 14 and the negative electrode 15 of series boosting battery unit.
Described interconnecting metal material includes, but are not limited to Al, Cu, W, Pt, TaN and combination thereof or alloy.
The silicide metals of sputtering deposit is positioned on oxide skin(coating) in the place that has oxide dielectric layer, and at contact window place, silicide metals is positioned at silicon face.In annealing heat treatment process subsequently, metal and silicon form silicide, reduce contact resistance, and metal on oxide does not react with oxide, is eroded subsequently by chemical solution.

Claims (2)

1. a series boosting solar battery cell, is characterized in that, at lightly doped P -on type silicon substrate, be prepared with shallow channel isolation area, be prepared with the N trap of medium-doped in the active area between shallow channel isolation area, this region is as P +/ N trap type solar cell D 1n-type substrate; In N-type substrate, be prepared with large area, heavily doped P +active area is prepared with substrate contact region, described P simultaneously on substrate +active area and N-type substrate form P +/ N trap type solar cell D 1; At described P +in the N-type substrate in outside, active area, be prepared with heavily doped N +contact zone, is prepared with heavily doped N simultaneously on the basolateral substrate of N-type +active area, described N +active area and P type substrate form N +/ P substrate-type solar cell D 2; At surface deposition dielectric layer, described dielectric layer doubles as the anti-reflective film of solar cell simultaneously, increases the incident efficiency of sunlight; Be prepared with anode electrode and the cathode electrode of described two kinds of solar cells in surface portion; P +/ N trap type solar cell D 1cathode electrode and N +/ P substrate-type solar cell D 2anode electrode short circuit connect, P +/ N trap type solar cell D 1anode electrode and N +/ P substrate-type solar cell D 2cathode electrode draw, respectively as anode and the negative electrode of series boosting battery unit.
2. series boosting solar battery cell as claimed in claim 1, is characterized in that, is silica medium layer at surface deposition dielectric layer, is etched with several P on dielectric layer +active area, N trap contact zone, N +the contact hole of active area and substrate contact region, contact hole area is 0.5 × 0.5 μ m 2.
CN201420017192.2U 2014-01-10 2014-01-10 Series-connection boosting solar cell unit Expired - Fee Related CN203674213U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420017192.2U CN203674213U (en) 2014-01-10 2014-01-10 Series-connection boosting solar cell unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420017192.2U CN203674213U (en) 2014-01-10 2014-01-10 Series-connection boosting solar cell unit

Publications (1)

Publication Number Publication Date
CN203674213U true CN203674213U (en) 2014-06-25

Family

ID=50970478

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420017192.2U Expired - Fee Related CN203674213U (en) 2014-01-10 2014-01-10 Series-connection boosting solar cell unit

Country Status (1)

Country Link
CN (1) CN203674213U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762219A (en) * 2014-01-10 2014-04-30 天津大学 Series boosting solar cell unit and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762219A (en) * 2014-01-10 2014-04-30 天津大学 Series boosting solar cell unit and manufacturing method thereof
CN103762219B (en) * 2014-01-10 2016-08-24 天津大学 Series boosting solar battery cell and preparation method thereof

Similar Documents

Publication Publication Date Title
CN101587913B (en) Novel SINP silicone blue-violet battery and preparation method thereof
CN106098839B (en) A kind of preparation method of efficiently crystal silicon PERC batteries
CN105845747A (en) Solar cell structure
US20160094072A1 (en) Hybrid energy harvesting device
CN102664197B (en) JFET (Junction Field Effect Transistor) and manufacturing method thereof, and micro inverter using JFET
CN102376789A (en) Selective emitter solar battery and preparation method
CN109585600A (en) A kind of production method of the efficient crystal silicon solar batteries of two-sided PERC
CN111463283A (en) DMOS (double-diffusion metal oxide semiconductor) structure integrating starting tube, sampling tube and diode and preparation method thereof
CN111477720A (en) Passivated contact N-type back junction solar cell and preparation method thereof
CN107221579B (en) Solar battery film plating process and solar battery
CN203674213U (en) Series-connection boosting solar cell unit
CN203325916U (en) Novel double-layer film back surface passivated solar cell structure
CN106024933A (en) Crystalline silicon solar battery back side local double mass impurity doped structure and doping method thereof
CN102694049A (en) Silicon thin film solar cell with novel intermediate layer structure
CN101752455A (en) Manufacturing method of solar cell
TW201010115A (en) Method for depositing an amorphous silicon film for photovoltaic devices with reduced light-induced degradation for improved stabilized performance
CN107112371A (en) Solar cell with improved life-span, passivation and/or efficiency
CN107302029B (en) Silicon-based MOSFET device with thermoelectric conversion function and oriented to Internet of things
CN103094420B (en) A kind of back of solar cell processing method
CN104616986A (en) Preparation method of fast recovery diode
CN103762219A (en) Series boosting solar cell unit and manufacturing method thereof
CN115692516A (en) Novel TOPCON battery and manufacturing method thereof
CN104064606A (en) Metal-insulator layer-semiconductor solar cell
CN104051052A (en) Trench isolation type alpha irradiation battery with PIN type GaN extension layer and manufacturing method
Lu et al. Above-CMOS a-Si and CIGS solar cells for powering autonomous microsystems

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140625

Termination date: 20170110