CN203587716U - Server test fixture board - Google Patents
Server test fixture board Download PDFInfo
- Publication number
- CN203587716U CN203587716U CN201320652484.9U CN201320652484U CN203587716U CN 203587716 U CN203587716 U CN 203587716U CN 201320652484 U CN201320652484 U CN 201320652484U CN 203587716 U CN203587716 U CN 203587716U
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- CN
- China
- Prior art keywords
- board
- plate
- motherboard
- bmc
- chip
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model provides a server test fixture board, which comprises a motherboard test board and a BMC-class board test board. The motherboard test board is connected with a motherboard and is configured to send a UAGT signal to an external machine station, wherein the external machine station is communicated with a chip on the motherboard. The BMC-class board test board is configured to send a UART signal to the external machine station. Then the external machine station sends out a test instruction to test a chip on a BMC-class board and the network transmission function.
Description
[Ji Intraoperative field]
The utility model relates to the measurement jig plate of semiconductor element, relates in particular to a kind of server test jig plate.
[Bei Jing Ji Intraoperative]
In server test framework, when production test, must utilize the UART(Universal Asynchronous Receiver/Transmitter on motherboard, Universal Asynchronous Receiver & dispensing device) signal is connected to the Test with BFT(Board Function that assigns that tester table carries out instruction) test, if but treat that by various the joint of brake all designs on motherboard, not only can increase plate space of planes, increase the cost of parts of producing, more cannot once carry out the checking of various functions, while causing testing, often get half the result with twice the effort.
[summary of the invention]
Therefore, the purpose of this utility model is mainly to provide a kind of server test jig plate that host board testing in production procedure is simplified.
For achieving the above object, the utility model provides a kind of server test jig plate, comprise host board testing plate and class BMC board test plate, wherein, host board testing plate is connected with a motherboard, this host board testing plate sends the outside board of UART signal to, and by this outside board, the chip on this motherboard is linked up; Class BMC board test plate sends UART signal to this outside board, and sends test instruction by this outside board, chip and network conduction function on checking class BMC plate.
Especially, boost to provide this outside board to use UART signal, this UART signal of integrating on All hosts plate enters one first joint, again the winding displacement of this joint is cut into one second joint, make all UART signals on this motherboard be sent to this outside board, by this outside board, the chip on this motherboard is linked up and test.
Especially, this motherboard provides UART signal to described host board testing plate, and this host board testing plate connects a USB debug plate, and this USB debug plate converts this UART signal to USB signal.
Especially, boost to provide this outside board to use UART signal, and the TX of such BMC board chip and RX are docked mutually, the correctness of the operation signal of checking class BMC chip on board.
Especially, each interface of one the 3rd joint external on such BMC plate is connected in series, tests the network conduction function of each interface.
Compared to prior art, server test jig plate of the present utility model, has improved the test process of the server in existing production procedure, makes the formation of test macro simpler, has more reduced the cost of manufactured parts simultaneously.
[accompanying drawing explanation]
Fig. 1 is the connection block diagram of the host board testing plate of the utility model server test jig plate;
Fig. 2 is the connection block diagram of the class BMC board test plate of the utility model server test jig plate.
[embodiment]
Below, by reference to the accompanying drawings shown in, specific embodiment of the utility model is elaborated:
The utility model provides a kind of server test jig plate, improve the testing process of server in existing production procedure, the formation of test macro is simplified, described server test jig plate comprises host board testing plate 1 and class BMC board test plate 2, wherein, host board testing plate 1 is connected with a motherboard 4, and this host board testing plate 1 sends the outside board 3 of UART signal to, and is linked up by the chip on 3 pairs of these motherboards 4 of this outside board; Class BMC board test plate 2 sends UART signal to this outside board 3, and by this outside board 3, sends test instruction, chip and network conduction function on checking one class BMC plate 5.
In the present embodiment, the UART signal that is 3.3V by original voltage boosts to 9V to provide this outside board 3 to use, due to each BFT(Board Function Test) four motherboards 4 of test, therefore this UART signal of integrating on All hosts plate 4 enters one first joint, again 4 groups of winding displacements of this joint are cut into one second joint that adds up to 44 groups, make all UART signals on this motherboard 4 be sent to this outside board 3, by the chip on 3 pairs of these motherboards 4 of this outside board, linked up, lower to a great extent the mistake that artificial plug causes, and accelerated test speed, lower test required time.
In the present embodiment, this motherboard 4 provides UART signal to described host board testing plate 1, and this host board testing plate 1 connects a USB debug plate, and this USB debug plate converts this UART signal to USB signal.
In the present embodiment, boost to provide this outside board 3 to use UART signal, and TX and the RX of chip on such BMC plate 5 are docked mutually, the correctness of the operation signal of chip on checking class BMC plate 5.
In the present embodiment, each interface of one the 3rd joint external on such BMC plate 5 is connected in series, test the network conduction function of each interface.
By reference to the accompanying drawings embodiment of the present utility model and embodiment are described in detail above, but the utility model is not limited to the above-described embodiment and examples, in the ken possessing those skilled in the art, can also make a variety of changes without departing from the concept of the premise utility.
Claims (5)
1. a server test jig plate, in order to a motherboard is tested, is characterized in that, comprising:
Host board testing plate, it is connected with a motherboard, and this host board testing plate sends the outside board of UART signal to, and by this outside board, the chip on this motherboard is linked up;
Class BMC board test plate, it sends UART signal to this outside board, and sends test instruction by this outside board, operation and the network conduction function of checking one class BMC chip on board.
2. server test jig plate according to claim 1, it is characterized in that, boost to provide this outside board to use UART signal, this UART signal of integrating on All hosts plate enters one first joint, again the winding displacement of this joint is cut into one second joint, make all UART signals on this motherboard be sent to this outside board, by this outside board, the chip on this motherboard is linked up.
3. server test jig plate according to claim 1, is characterized in that, this motherboard provides UART signal to described host board testing plate, and this host board testing plate connects a USB debug plate, and this USB debug plate converts this UART signal to USB signal.
4. server test jig plate according to claim 1, is characterized in that, boosts to provide this outside board to use UART signal, and the TX of such BMC board chip and RX are docked mutually, the correctness of the operation signal of checking class BMC chip on board.
5. server test jig plate according to claim 1, is characterized in that, each interface of one the 3rd joint external on such BMC plate is connected in series, and tests the network conduction function of each interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320652484.9U CN203587716U (en) | 2013-10-22 | 2013-10-22 | Server test fixture board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320652484.9U CN203587716U (en) | 2013-10-22 | 2013-10-22 | Server test fixture board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203587716U true CN203587716U (en) | 2014-05-07 |
Family
ID=50585616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320652484.9U Expired - Fee Related CN203587716U (en) | 2013-10-22 | 2013-10-22 | Server test fixture board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203587716U (en) |
-
2013
- 2013-10-22 CN CN201320652484.9U patent/CN203587716U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140507 Termination date: 20161022 |