CN203561985U

CN203561985U - FPGA (field programmable gate array) chip and BMC (baseboard management controller) chip coordinated power management system for ATCA (advanced telecom computing architecture) blade

Info

Publication number: CN203561985U
Application number: CN201320713756.1U
Authority: CN
Inventors: 袁海滨; 张克功; 邵宗有; 沙超群; 郑臣明; 王晖
Original assignee: Dawning Information Industry Beijing Co Ltd
Current assignee: Dawning Information Industry Beijing Co Ltd
Priority date: 2013-11-13
Filing date: 2013-11-13
Publication date: 2014-04-23
Anticipated expiration: 2023-11-13

Abstract

The utility model provides an FPGA (field programmable gate array) chip and BMC (baseboard management controller) chip coordinated power management system for an ATCA (advanced telecom computing architecture) blade. The system comprises an FPGA chip, a BMC chip, N power modules and a case manager, wherein enabling pins and Power Good pins of the N power modules are connected with IO (input/output) pins of the FPGA chip respectively; output ends of the N power modules are connected with AD voltage sampling interfaces of the BMC chip; the FPGA chip communicates with the BMC chip through an I2C (inter-integrated circuit) bus; and the case manager is in bidirectional connection with the BMC chip. The FPGA chip and BMC chip coordinated power management system for the ATCA blade indicates whether the FPGA chip is electrified normally or not according to the state of an LED (light-emitting diode) indicating lamp, and finding of power failures with hardware means is avoided whenever possible, so that troubleshooting is simple and efficient.

Description

A kind of for the fpga chip on ATCA blade and the collaborative power-supply management system of BMC chip

Technical field

The utility model belongs to field of computer technology, is specifically related to a kind of for the fpga chip on ATCA blade and the collaborative power-supply management system of BMC chip.

Background technology

On comparatively complicated ATCA blade, between each acp chip and each power requirement of each chip itself possess certain electrifying timing sequence and could normally work.Conventionally we,, with the output enable end of programming device control power module, reach the electrifying timing sequence requirement between each power supply by different delays.

With the programming device control output that powers on, be mainly the output enable end of controlling power module, do not opening in the same time each power module output.Electrifying timing sequence between each power supply of some chip requires stricter, exists two power supplys of electrifying timing sequence can not occur phenomena of inversion.Otherwise the probability that chip is damaged is very large.Therefore, when certain power supply in power up, export when undesired, power supply below just can not continue to power on, and has avoided like this electric sequence phenomena of inversion.Each electric state of power up need to go on record, and when there is certain power fail in power up, which power issue can orient fast according to record is.

Utility model content

In order to overcome above-mentioned the deficiencies in the prior art, it is a kind of for the fpga chip on ATCA blade and the collaborative power-supply management system of BMC chip that the utility model provides, according to the state indication fpga chip of LED light, whether normally power on, also avoided as far as possible use hardware means to search power fail, malfunction elimination is become simply, efficient.

To achieve these goals, the utility model is taked following scheme:

It is a kind of for the fpga chip on ATCA blade and the collaborative power-supply management system of BMC chip that the utility model provides, and described system comprises fpga chip, BMC chip, a N power module and shelf management device; The enable pin of N power module and Power Good pin are connected respectively the IO pin of described fpga chip, and the output terminal of N power module is all received on the AD voltage sample interface of described BMC chip, between described fpga chip and BMC chip, passes through I ²c bus communicates; Described shelf management device and described two-way connection of BMC chip.

Described BMC chip and fpga chip are respectively I ²c main equipment and I ²c is from equipment, and described BMC chip passes through I ²the power-up state register of C bus access fpga chip inside.

Described fpga chip inside is also provided with the control register that powers on.

Whether described system also comprises LED light, indicate described fpga chip to power on and normally complete.

Described shelf management device connects the IPMI interface of described BMC chip, completes with the two-way of described BMC chip and is connected.

Compared with prior art, the beneficial effects of the utility model are:

1) can whether normally power on according to the state indication fpga chip of LED light;

2) by the inner definition of FPGA power-up state register, can preserve the power-up state of each road power supply;

3) when power module powers on, break down, BMC chip can be accessed the FPGA inside control register that powers on, and the position corresponding according to the Power Good signal of each road power module, judges that Shi Na road power module has problem;

4) can check one-board power supply duty by shelf management device, orientation problem, has avoided use hardware means to search power fail as far as possible, and malfunction elimination is become simply, efficient.

Accompanying drawing explanation

Fig. 1 is for the fpga chip on ATCA blade and the collaborative power-supply management system structured flowchart of BMC chip.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail.

As Fig. 1, it is a kind of for ATCA(Advanced Telecom Computing Architecture that the utility model provides) fpga chip and BMC(Baseboard Management Controller on blade) chip works in coordination with power-supply management system, and described system comprises fpga chip, BMC chip, a N power module and shelf management device; The enable pin of N power module and Power Good pin are connected respectively the IO pin of described fpga chip, and the output terminal of N power module is all received on the AD voltage sample interface of described BMC chip, between described fpga chip and BMC chip, passes through I ²c bus communicates; Described shelf management device and described two-way connection of BMC chip.

The principle of work that fpga chip and BMC chip are realized the coordinated management to power supply is as follows:

When in the intact insertion cabinet of ATCA blade, BMC chip self loading system, after chassis management module communication normally, sends starting-up signal to fpga chip.

Fpga chip is received after starting-up signal, according to electrifying timing sequence requirement, send the power module output enable signal powering at first, when detecting after the Power Good signal of this power module, just send the power module output enable signal in next moment, go down successively until send the output enable signal of last power module.

After having powered on, if it is normal to power on, LED light is in normal bright state, if power up breaks down, LED light is in blink states.

BMC chip passes through I ²whether normal the inner power-up state register of C interface access fpga chip, detect each power module output.Simultaneously BMC is also by each the road power supply output of inner AD voltage sample, detects power supply output valve whether in normal range.

If BMC chip is passed to chassis management module by AD voltage sample value by IPMI interface, on shelf management device piece, can demonstrate the size of each voltage.

Finally should be noted that: above embodiment is only in order to illustrate that the technical solution of the utility model is not intended to limit, although the utility model is had been described in detail with reference to above-described embodiment, those of ordinary skill in the field are to be understood that: still can modify or be equal to replacement embodiment of the present utility model, and do not depart from any modification of the utility model spirit and scope or be equal to replacement, it all should be encompassed in the middle of claim scope of the present utility model.

Claims

1. for the fpga chip on ATCA blade and the collaborative power-supply management system of BMC chip, it is characterized in that: described system comprises fpga chip, BMC chip, a N power module and shelf management device; The enable pin of N power module and Power Good pin are connected respectively the IO pin of described fpga chip, and the output terminal of N power module is all received on the AD Sampling Interface of described BMC chip, between described fpga chip and BMC chip, passes through I ²c bus communicates; Described shelf management device and described two-way connection of BMC chip.

2. according to claim 1 for the fpga chip on ATCA blade and the collaborative power-supply management system of BMC chip, it is characterized in that: described BMC chip and fpga chip are respectively I ²c main equipment and I ²c is from equipment, and described BMC chip passes through I ²the power-up state register of C bus access fpga chip inside.

3. according to claim 2 for the fpga chip on ATCA blade and the collaborative power-supply management system of BMC chip, it is characterized in that: described fpga chip inside is also provided with the control register that powers on.

4. according to claim 1ly for the collaborative power-supply management system of the fpga chip on ATCA blade and BMC chip, it is characterized in that: described system also comprises LED light, indicate described fpga chip to power on and whether normally complete.

5. according to claim 1ly for the collaborative power-supply management system of the fpga chip on ATCA blade and BMC chip, it is characterized in that: described shelf management device connects the IPMI interface of described BMC chip, complete with the two-way of described BMC chip and be connected.