CN106649158B - Device and method for reading and writing internal register file through I2C interface - Google Patents
Device and method for reading and writing internal register file through I2C interface Download PDFInfo
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- CN106649158B CN106649158B CN201611234220.6A CN201611234220A CN106649158B CN 106649158 B CN106649158 B CN 106649158B CN 201611234220 A CN201611234220 A CN 201611234220A CN 106649158 B CN106649158 B CN 106649158B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
Abstract
An apparatus and method for reading from and writing to an internal register file via an I2C interface, the apparatus comprising: the I2C master sends signals to the I2C slave and the read-write enabling control unit and reads data in the I2C slave; the I2C slave machine comprises a first I2C read-write register, a second I2C read-write register and an I2C read-only register, and the first I2C read-write register, the second I2C read-write register and the I2C read-only register respectively store write ID and write data, read ID and read data; a read-write operation unit which performs read-write operation on the internal register file; the read-write enabling control unit generates a read-write enabling signal according to a sending signal of the I2C host and controls the read-write operation unit by juxtaposing 1, and when the write enabling signal is 1, the read-write operation unit carries out write operation; when the read enable signal is 1, a read operation is performed and the read data is fed back to the I2C read-only register. The device and the method realize the reading and writing of the register file in the chip on the premise of not additionally increasing the expenditure of an external interface and the consumption of an internal storage circuit, and have important significance on the design of testability.
Description
Technical Field
The invention belongs to the technical field of electric communication, and particularly relates to a device and a method for reading and writing an internal register file through an I2C interface.
Background
The MIPI interface is a new high-speed interface, has the characteristics of low power consumption, high transmission rate and the like, and is widely applied to mobile equipment. MPHY IP is the most critical part of MIPI design, and MPHY has significant advantages over other serial PHYs because it can flexibly configure a variety of optional modes and attributes. This flexibility is achieved by the configuration area of the MPHY, which is made up of a register file, with each register having a specific ID number. Enhancing testability and observability of configuration areas is critical to the design and validation of MPHYs.
However, in the chip design process, the testable solution is limited to a certain extent by the restriction factors such as area, power consumption, and the number of external interfaces. The I2C interface is a bus that uses a minimum number of signal lines among various buses, and data transmission can be realized only by two lines, namely SCL and SDA, and therefore, the I2C interface is a common solution. In chip design, for test purposes, an I2C slave is often added to the chip design, on-chip signals to be observed are registered in an I2C register, and on-chip signals are observed by issuing a read request to an on-chip I2C slave from an off-chip I2C master, and similarly, a rewrite value and a rewrite enable of on-chip signals to be forcibly rewritten may be registered in an I2C register, and on-chip signals may be forcibly rewritten by issuing a write request to an on-chip I2C slave from an off-chip I2C master. For the internal register file, because the number of registers is large, the numeric value stored in each register is respectively registered in the I2C register to realize a testable and observable mode, a large amount of I2C register resources are consumed, and performance indexes such as power consumption and area are further influenced. Therefore, how to read and write the register file inside the chip is realized on the premise of not additionally increasing the external interface overhead and the internal storage resource consumption, and the method has important significance for testability design.
Disclosure of Invention
In view of the above problems, it is a primary object of the present invention to provide an apparatus and method for reading and writing an internal register file via an I2C interface, which is used to solve at least one of the above problems.
In order to achieve the above object, as one aspect of the present invention, the present invention provides an apparatus for reading and writing an internal register file through an I2C interface, including an I2C master, an I2C slave, a read-write enable control unit, and a read-write operation unit, wherein:
the I2C host is used for sending signals to the I2C slave and the read-write enabling control module and reading data in the I2C slave;
the I2C slave machine comprises a first I2C read-write register, a second I2C read-write register and an I2C read-only register, and is used for respectively receiving the sending signal of the I2C host machine and respectively storing the write ID, the write data, the read ID and the read data read and written by the I2C host machine;
the read-write operation unit is used for performing read-write operation on the internal register file;
the read-write enabling control unit is used for generating a read-write enabling signal according to a sending signal of the I2C host and juxtaposing 1 to control the read-write operation unit, and when the write enabling signal is 1, the read-write operation unit carries out write operation according to the write ID and write data; when the read enable signal is 1, the read-write operation unit performs a read operation according to the read ID, and feeds back read data to the I2C read-only register.
Further, the read-write operation unit is further configured to generate a write completion signal or a read completion signal after the write operation or the read operation is completed and feed back the write completion signal or the read completion signal to the read-write enable control unit in parallel with 1, where the write completion signal and the read completion signal are set to 0 after being maintained for one cycle.
Furthermore, the read-write enabling control unit comprises a transmission process judging module, a slave address and transmission direction judging module, a write enabling generating module and a read enabling generating module.
Further, the signal sent by the I2C host to the read/write enable control unit is the change of the state on the SCL and SDA lines, the transmission process determining module determines whether the I2C host performs I2C operation according to the signal and generates a transmission process indicating signal to set 1 after detecting the I2C start signal; after detecting the I2C termination signal, the transfer process indication signal is set to 0.
Further, the slave address and transmission direction determining module determines that the I2C operation is a write operation or a read operation when the transmission process indication signal is 1, and generates a pre-write enable signal and sets 1 when the write operation is performed; when a read operation is performed, a pre-read enable signal is generated and set to 1.
Further, the slave address and transmission direction determining module is further configured to receive a write completion signal or a read enable signal and set the pre-write enable signal or the pre-read enable signal to 0.
Further, the write enable generation module is configured to generate a write enable signal and concatenate the write enable signal and 1 to the read/write operation unit when the pre-write enable signal is 1 and the transmission process indication signal is 0, and is further configured to receive a write complete signal and set the write enable signal to 0;
further, the read enable generation module is configured to generate a read enable signal and transmit the read enable signal to the read/write operation unit in parallel with 1 when the pre-read enable signal is 1 and the transmission process indication signal is 0, and is further configured to receive the read completion signal and set the read enable signal to 0.
Furthermore, the read-write operation unit comprises a write operation module and a read operation module.
Further, the write operation module receives the write ID, the write data and the write enable signal, performs a rewrite operation on a corresponding register in the internal register file when the write enable signal is 1, generates a write completion signal after the rewrite operation is completed, and feeds the write completion signal to the slave address and transfer direction determination module and the write enable generation module in parallel 1.
Further, the read operation module receives the read ID and performs a read operation on a corresponding register in the internal register file when the read enable signal is 1, generates a read completion signal after the read operation is completed, and feeds back the read completion signal to the slave address and transmission direction determination module and the read enable generation module in parallel, and sends the read data to the I2C read-only register for storage.
In order to achieve the above object, as another aspect of the present invention, the present invention proposes a method of rewriting an internal register file through an I2C interface, the method being implemented by an apparatus including an I2C master, an I2C slave, a read-write enable control unit, and a read-write operation unit; the method comprises the following steps:
step 11, the I2C master sends an I2C operation starting signal and a data rewriting signal to the read-write enabling control unit, and sends a write ID and write data for rewriting the data to the I2C slave;
step 12, the read-write enable control unit generates a pre-write enable signal and sets 1 in parallel according to the I2C operation start signal and the data rewriting signal;
step 13, the I2C host sends an I2C operation stop signal to the read-write enabling control unit;
step 14, generating a write enable signal and setting the write enable signal as 1 by the read-write enable control unit according to the I2C operation stop signal and the pre-write enable signal as 1;
step 15, the read-write operation unit receives a write enable signal of 1 according to the write ID and the write data, performs the rewriting operation on the internal register file, generates a write completion signal after completing the rewriting operation, and sets 1 to feed back to the read-write enable control unit;
and step 16, the read-write enabling control unit receives the write completion signal of 1, sets the pre-write enabling signal and the write enabling signal to be 0, and completes the rewriting of the internal register file.
The invention also provides a method for reading the internal register file through the I2C interface, which is realized by a device comprising an I2C host, an I2C slave, a read-write enabling control unit and a read-write operation unit; the method comprises the following steps:
step 21, the I2C host sends an I2C operation starting signal and a data reading signal to the read-write enabling control unit, and sends a read ID for reading data to the I2C slave;
step 22, the read-write enable control unit generates a pre-read enable signal and sets 1 in parallel according to the I2C operation start signal and the data read signal;
step 23, the I2C host transmits an I2C operation stop signal to the read-write enabling control unit;
step 24, the read-write enable control unit generates a read enable signal and sets the read enable signal to be 1 in parallel according to the I2C operation stop signal and the pre-read enable signal which is 1;
step 25, the read-write operation unit receives a read enable signal of 1 according to the read ID, performs read operation on the internal register file, generates a read complete signal after completing the read operation, sets 1 to be fed back to the read-write enable control unit, and transmits the read data to the I2C slave;
step 26, the read-write enable control unit receives the read completion signal of 1 and sets the pre-read enable signal and the read enable signal to 0;
and step 27, the I2C master sends a signal to the I2C slave to read data, and the reading of the internal register file is completed.
Based on the above scheme, the device and the method for reading and writing the internal register file through the I2C interface provided by the invention only need two I2C read-write registers and one I2C read-only register, the I2C slave machines do not need to correspond to the registers of the internal register file one by one, and the read-write operation is performed through the read-write enabling control module and the read-write operation module, so that the read-write of the internal register file can be effectively realized on the premise of not additionally increasing the external interface overhead and the internal storage resource consumption, and the testability and observability of the internal register file are further effectively increased.
Drawings
FIG. 1 is a block diagram of an apparatus for reading from and writing to an internal register file via an I2C interface according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a read/write enable control module according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a read/write operation module according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the relationship of signals rewriting a designated internal register through the I2C interface in accordance with one embodiment of the present invention;
FIG. 5 is a signal diagram illustrating the reading of specified internal registers via the I2C interface according to another embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The invention discloses a device for reading and writing an internal register file through an I2C interface, which comprises an I2C host, an I2C slave, a read-write enabling control unit and a read-write operation unit, wherein:
the I2C host is used for sending signals to the I2C slave and the read-write enabling control module and reading data in the I2C slave;
the I2C slave computer mainly comprises a first I2C read-write register, a second I2C read-write register and an I2C read-only register, and is used for respectively receiving a sending signal of the I2C host computer and respectively storing a write ID, write data, a read ID and read data read and written by the I2C host computer; preferably, the I2C slave is mainly composed of a first I2C read-write register, a second I2C read-write register and an I2C read-only register, and the read-write operation of a plurality of registers in the internal register file can be realized only through the three registers.
The read-write operation unit is used for performing read-write operation on the internal register file;
the read-write enabling control unit is used for generating a read-write enabling signal according to a sending signal of the I2C host and juxtaposing 1 to control the read-write operation unit, and when the write enabling signal is 1, the read-write operation unit carries out write operation according to the write ID and write data; when the read enable signal is 1, the read-write operation unit performs a read operation according to the read ID, and feeds back read data to the I2C read-only register.
The read-write operation unit is also used for generating a write completion signal or a read completion signal after completing the write operation or the read operation and feeding the write completion signal or the read completion signal 1 back to the read-write enabling control unit, and the write completion signal and the read completion signal are set to be 0 after keeping one period.
Preferably, the read/write enable control unit includes a transmission process determining module, a slave address and transmission direction determining module, a write enable generating module, and a read enable generating module. The I2C host sends a signal to the read-write enable control unit as a change of state on the SCL and SDA lines,
the transmission process judging module judges whether the I2C host machine performs I2C operation according to the signal and generates a transmission process indicating signal with 1 after detecting an I2C initial signal; after detecting the I2C termination signal, the transfer process indication signal is set to 0.
The slave address and transmission direction judging module judges whether the operation is write operation or read operation when the transmission process indication signal is 1, and generates a pre-write enable signal to be juxtaposed to 1 when the write operation is performed; generating a pre-reading enable signal and setting 1 in parallel when reading; preferably, the slave address and transfer direction determining module is further configured to receive a write completion signal or a read enable signal and set the pre-write enable signal or the pre-read enable signal to 0.
The write enable generation module is used for generating a write enable signal and transmitting the write enable signal to the read-write operation unit in a juxtaposed manner, namely 1, when the pre-write enable signal is 1 and the transmission process indication signal is 0, and is also used for receiving a write completion signal and setting the write enable signal to be 0;
and the read enable generation module is used for generating a read enable signal and transmitting the read enable signal to the read-write operation unit in a manner of juxtaposing 1 to the read-write operation unit when the pre-read enable signal is 1 and the transmission process indication signal is 0, and is also used for receiving the read completion signal and setting the read enable signal to be 0.
Preferably, the read-write operation unit includes a write operation module and a read operation module.
The write operation module receives the write ID, the write data and the write enable signal, performs rewriting operation on a corresponding register in the internal register file when the write enable signal is 1, generates a write completion signal after the rewriting operation is completed, and feeds the write completion signal to the slave address and transmission direction judgment module and the write enable generation module in a juxtaposed mode 1.
And the read operation module receives the read ID, reads the corresponding register in the internal register file when the read enable signal is 1, generates a read completion signal after the read operation is completed, feeds the read completion signal to the slave address and transmission direction judgment module and the read enable generation module in parallel, and sends the read data to the I2C read-only register for storage.
The invention discloses a method for rewriting an internal register file through an I2C interface, which is realized by a device comprising an I2C host, an I2C slave, a read-write enabling control unit and a read-write operation unit; the method comprises the following steps:
step 11, the I2C master sends an I2C operation starting signal and a data rewriting signal to the read-write enabling control unit, and sends a write ID and write data for rewriting the data to the I2C slave;
step 12, the read-write enable control unit generates a pre-write enable signal and sets 1 in parallel according to the I2C operation start signal and the data rewriting signal;
step 13, the I2C host sends an I2C operation stop signal to the read-write enabling control unit;
step 14, generating a write enable signal and setting the write enable signal as 1 by the read-write enable control unit according to the I2C operation stop signal and the pre-write enable signal as 1;
step 15, the read-write operation unit receives a write enable signal of 1 according to the write ID and the write data, performs the rewriting operation on the internal register file, generates a write completion signal after completing the rewriting operation, and sets 1 to feed back to the read-write enable control unit;
and step 16, the read-write enabling control unit receives the write completion signal of 1, sets the pre-write enabling signal and the write enabling signal to be 0, and completes the rewriting of the internal register file.
The invention also discloses a method for reading the internal register file through the I2C interface, which is realized by a device comprising an I2C host, an I2C slave, a read-write enabling control unit and a read-write operation unit; the method comprises the following steps:
step 21, the I2C host sends an I2C operation starting signal and a data reading signal to the read-write enabling control unit, and sends a read ID for reading data to the I2C slave;
step 22, the read-write enable control unit generates a pre-read enable signal and sets 1 in parallel according to the I2C operation start signal and the data read signal;
step 23, the I2C host transmits an I2C operation stop signal to the read-write enabling control unit;
step 24, the read-write enable control unit generates a read enable signal and sets the read enable signal to be 1 in parallel according to the I2C operation stop signal and the pre-read enable signal which is 1;
step 25, the read-write operation unit receives a read enable signal of 1 according to the read ID, performs read operation on the internal register file, generates a read complete signal after completing the read operation, sets 1 to be fed back to the read-write enable control unit, and transmits the read data to the I2C slave;
step 26, the read-write enable control unit receives the read completion signal of 1 and sets the pre-read enable signal and the read enable signal to 0;
and step 27, the I2C master sends a signal to the I2C slave to read data, and the reading of the internal register file is completed.
The following describes in detail the apparatus and method for reading and writing the internal register file via the I2C interface according to the present invention with specific embodiments.
Example 1
As shown in fig. 1, which is a schematic structural diagram of an apparatus for reading and writing an internal register file through an I2C interface according to embodiment 1, the apparatus includes an I2C host, an I2C slave including three I2C registers, a read-write enable control module, and a read-write operation module, and specific functions of each portion are described below.
The I2C host is used for sending signals to the I2C slave and the read-write enabling control module and reading data in the I2C slave;
three I2C registers, including:
the first I2C read-write register is used for storing the ID value of the internal register to be rewritten and the rewritten data, namely write ID and write data, and the values are the basis of the read-write operation unit in the write operation, and the I2C host can perform read-write control on the first I2C read-write register;
the second I2C read-write register is used for storing an ID value of an internal register to be read, namely a read ID for short, and the value can be used by the read-write operation unit during read operation, and the I2C host can perform read-write control on the second I2C read-write register;
and the I2C read-only register is used for storing data in the specified read ID register returned by the read-write operation unit, the data is read for short, and the I2C host can only read the I2C read-only register.
And the read-write enabling control module is used for generating a read-write enabling signal according to the starting state, the slave address, the transmission direction and the termination state of the SCL and SDA buses and the read-write operation completion feedback output by the read-write operation module.
The read-write operation module is used for realizing read-write operation on the internal register file, writing specified write content into the internal register with specified write ID when the write enable signal is effective, and returning a write operation completion signal after the write operation is completed; at the time when the read enable signal is active, the contents stored in the internal register specifying the read ID are fed back to the I2C read-only register, and a read operation completion signal is returned after the completion of this read operation.
As shown in fig. 2, a schematic structural diagram of the read/write enable control module in this embodiment 1 specifically includes:
a transmission process judging module for judging whether the I2C host is performing I2C operation according to the state change on SCL and SDA lines, and after detecting the I2C start signal, setting the transmission process indicating signal to 1 until detecting the I2C stop signal, and then setting it to 0;
the slave address and transmission direction judging module is used for judging the slave address according to the values of the first seven bits after the transmission process indicating signal is valid, judging whether the transmission direction of the current I2C operation is a read operation or a write operation according to the value of the eighth bit after the transmission process indicating signal is valid, setting the pre-write enable signal to be 1 when the transmission direction of the current I2C operation is detected to be the write operation, and keeping the pre-write enable signal to be reset to be 0 after the write operation completion signal output by the read-write operation unit is valid; when the transmission direction of the current I2C operation is detected to be a read operation, setting a pre-read enable signal to be 1, and keeping the pre-read enable signal to be 0 again until a read operation completion signal output by the read-write operation unit is effective;
the write enable generation module is used for generating a write enable control signal according to the transmission process indication signal, the pre-write enable signal and the write operation completion signal output by the read-write operation unit, setting the write enable control signal to be 1 when the pre-write enable signal is effective and the transmission process indication signal is invalid, and resetting the write enable control signal to be 0 after the write operation completion signal is effective;
and the read enable generation module is used for generating a read enable control signal according to the transmission process indication signal, the pre-read enable signal and the read operation completion signal output by the read-write operation unit, setting the read enable control signal to be 1 when the pre-read enable signal is effective and the transmission process indication signal is invalid, and resetting the read enable control signal to be 0 after the read operation completion signal is effective.
As shown in fig. 3, a schematic structural diagram of the read/write operation module in this embodiment 1 specifically includes:
the write operation module is used for writing the write data into the internal register of the specified write ID according to the write ID and the write data stored in the first I2C read-write register when the write enable signal is valid, setting a write operation completion signal to be 1 after the current write operation is completed, and resetting to be 0 after a period is kept;
and the read operation module is used for writing the value of the internal register of the specified read ID into the I2C read-only register according to the read ID stored in the second I2C read-write register when the read enable signal is valid, setting the read operation completion signal to be 1 after the current read operation is completed, and resetting the value to be 0 after one cycle.
Example 2
As shown in fig. 4, a signal relationship diagram of the method for rewriting the internal register file through the I2C interface proposed in this embodiment is described as follows:
step 11, the transmission process determining module in the read/write enable control module determines the start flag of I2C transmission according to the state changes on the SCL and SDA lines, the SDA signal shows a falling edge when the SCL signal is at a high level, i.e. it indicates that I2C starts to transmit, and the transmission process determining module sets the transmission process indication signal to 1 when detecting the change;
step 12, a slave address and transmission direction judgment module in the read-write enable control module judges according to the slave address value of the first seven bits and the transmission direction value of the eighth bit after the transmission process indication signal is valid, and sets the pre-write enable signal to 1 when detecting that the current I2C operation is the write operation to the first I2C read-write register;
step 13, the transmission process determining module in the read/write enable control module determines the termination flag of I2C transmission according to the state change on the SCL and SDA lines, the SDA signal shows a rising edge when the SCL signal is at a high level, which indicates that I2C transmission is terminated, and the transmission process determining module sets the transmission process indicating signal to 0 when detecting the change; step 14, a write enable generation module in the read-write enable control module sets the write enable signal to be 1 when the pre-write enable signal is 1 and the transmission process indication signal is 0;
step 15, a write operation module in the read-write operation module writes write data into an internal register of a specified write ID according to the write ID and the write data stored in the first I2C read-write register, and sets a write completion signal 1 to be fed back to a slave address and transmission direction judgment module and a write enable generation module of the read-write enable control module after the current write operation is completed;
and step 16, after the write operation completion signal is 1, resetting the pre-write enable signal and the write enable control signal to 0 respectively by the slave address and transmission direction judging module and the write enable generating module in the read-write enable control module, and completing the rewriting of the internal register file.
Example 3
As shown in fig. 5, a signal relationship diagram of the method for reading the internal register file through the I2C interface according to the present embodiment is described as follows:
step 21, the transmission process determining module in the read/write enable control module determines the start flag of I2C transmission according to the state changes on the SCL and SDA lines, the SDA signal shows a falling edge when the SCL signal is at a high level, i.e. it indicates that I2C starts to transmit, and the transmission process determining module sets the transmission process indication signal to 1 when detecting the change;
step 22, the slave address and transmission direction determining module in the read/write enable control module determines according to the slave address value of the first seven bits and the transmission direction value of the eighth bit after the transmission process indication signal is valid, and sets the pre-read enable signal to 1 when detecting that the current I2C operation is the write operation to the second I2C read/write register;
step 23, the transmission process determining module in the read/write enable control module determines the termination flag of I2C transmission according to the state change on the SCL and SDA lines, the SDA signal shows a rising edge when the SCL signal is at a high level, which indicates that I2C transmission is terminated, and the transmission process determining module sets the transmission process indication signal to 0 when detecting the change;
step 24, a read enable generation module in the read-write enable control module sets the read enable signal to be 1 when the pre-read enable signal is 1 and the transmission process indication signal is 0;
step 25, a read operation module in the read-write operation module writes the value of the internal register of the specified read ID into the I2C read-only register according to the read ID stored in the second I2C read-write register when the read enable signal is 1, and sets a read completion signal to 1 and feeds back the read completion signal to a slave address and transmission direction judgment module and a read enable generation module in the read-write enable control module after the read operation is completed;
step 26, resetting the pre-read enable signal and the read enable signal to 0 when the read completion signal is 1 by a slave address and transmission direction judging module and a read enable generating module in the read-write enable control module;
step 27, the host computer of I2C initiates a read operation to the I2C read-only register, and further obtains the value of the internal register of the specified read ID, and finishes reading the internal register file.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. An apparatus for reading and writing an internal register file through an I2C interface, comprising an I2C host, an I2C slave, a read-write enable control unit, and a read-write operation unit, wherein:
the I2C host is used for sending signals to the I2C slave and the read-write enabling control module and reading data in the I2C slave;
the I2C slave machine comprises: the first I2C read-write register is used for receiving a sending signal of the I2C host and storing a write ID and write data read and written by the I2C host; a second I2C read-write register for receiving the transmission signal of the I2C host and storing the read ID, and an I2C read-only register for receiving the transmission signal of the I2C host and storing the read data;
the read-write operation unit is used for performing read-write operation on the internal register file;
the read-write enabling control unit is used for generating a read-write enabling signal according to a sending signal of the I2C host and juxtaposing 1 to control the read-write operation unit, and when the write enabling signal is 1, the read-write operation unit carries out write operation according to the write ID and write data; when the read enable signal is 1, the read-write operation unit performs read operation according to the read ID, and feeds back read data to the I2C read-only register.
2. The apparatus of claim 1, wherein the read/write unit is further configured to generate a write complete signal or a read complete signal after completing a write operation or a read operation and to set 1 to be fed back to the read/write enable control unit, and the write complete signal and the read complete signal set 0 after holding for one cycle.
3. The apparatus of claim 2, wherein the read/write enable control unit comprises a transfer process determining module, a slave address and transfer direction determining module, a write enable generating module, and a read enable generating module;
the I2C host sends signal of SCL and SDA line state change to the read-write enable control unit, the transfer process judging module judges whether the I2C host carries out I2C operation according to the signal and generates transfer process indicating signal and sets 1 after detecting I2C start signal; after detecting the I2C termination signal, the transfer process indication signal is set to 0.
4. The apparatus as claimed in claim 3, wherein the slave address and transfer direction determining module determines whether the I2C operation is a write operation or a read operation when the transfer process indicating signal is 1, and generates a pre-write enable signal to set 1 when the write operation is performed; and when the read operation is carried out, generating a pre-read enable signal and juxtaposing 1, wherein the slave address and transmission direction judging module is also used for receiving the write completion signal or the read enable signal and setting 0 to the pre-write enable signal or the pre-read enable signal.
5. The apparatus of claim 4, wherein the write enable generation module is configured to generate a write enable signal with a set 1 to be transmitted to the read/write operation unit when the pre-write enable signal is 1 and the transfer process indication signal is 0, and further configured to receive the write complete signal and set the write enable signal to be 0; the read enable generation module is configured to generate a read enable signal and transmit the read enable signal to the read/write operation unit with a set 1 when the pre-read enable signal is 1 and the transmission process indication signal is 0, and is further configured to receive the read completion signal and set the read enable signal to 0.
6. The apparatus of claim 5, wherein the read/write unit comprises a write module and a read module.
7. The apparatus of claim 6, wherein the write operation module receives a write ID, write data and a write enable signal, performs a write operation on a corresponding register in the internal register file when the write enable signal is 1, generates a write completion signal after the write operation is completed, and feeds back the write completion signal to the slave address and transfer direction determination module and the write enable generation module in parallel with 1; and the read operation module receives the read ID, performs read operation on a corresponding register in the internal register file when the read enable signal is 1, generates a read completion signal after the read operation is completed, and feeds the read completion signal in parallel 1 back to the slave machine address and transmission direction judgment module and the read enable generation module, and simultaneously sends the read data to the I2C read-only register for storage.
8. A method for rewriting an internal register file through an I2C interface is realized by a device, wherein the device comprises an I2C host computer, an I2C slave computer, a read-write enabling control unit and a read-write operation unit; the method comprises the following steps:
step 11, the I2C master sends an I2C operation starting signal and a data rewriting signal to the read-write enabling control unit, and sends a write ID and write data for rewriting the data to the I2C slave;
step 12, the read-write enable control unit generates a pre-write enable signal and sets 1 in parallel according to the I2C operation start signal and the data rewriting signal;
step 13, the I2C host sends an I2C operation stop signal to the read-write enabling control unit;
step 14, generating a write enable signal and setting the write enable signal to be 1 in parallel by the read-write enable control unit according to the I2C operation stop signal and the pre-write enable signal which is 1;
step 15, the read-write operation unit receives a write enable signal of 1 according to the write ID and the write data, rewrites the internal register file, generates a write complete signal after completing the rewriting operation, and feeds back the write complete signal to the read-write enable control unit in a juxtaposed manner of 1;
and step 16, the read-write enabling control unit receives the write completion signal of 1, sets the pre-write enabling signal and the write enabling signal to be 0, and completes the rewriting of the internal register file.
9. A method for reading an internal register file through an I2C interface is realized by a device, wherein the device comprises an I2C host computer, an I2C slave computer, a read-write enabling control unit and a read-write operation unit; the method comprises the following steps:
step 21, the I2C host sends an I2C operation starting signal and a data reading signal to the read-write enabling control unit, and sends a read ID for data reading to the I2C slave;
step 22, generating a pre-reading enabling signal and setting the pre-reading enabling signal to be 1 in parallel by the read-write enabling control unit according to the I2C operation starting signal and the data reading signal;
step 23, the I2C host transmits an I2C operation stop signal to the read-write enabling control unit;
step 24, the read-write enable control unit generates a read enable signal and sets the read enable signal to be 1 in parallel according to the I2C operation stop signal and the pre-read enable signal which is 1;
step 25, the read-write operation unit receives a read enable signal of 1 according to the read ID, performs a read operation on the internal register file, generates a read complete signal after the read operation is completed, concatenates 1 and feeds back the read complete signal to the read-write enable control unit, and transmits the read data to the I2C slave;
step 26, the read-write enable control unit receives the read completion signal of 1 and sets the pre-read enable signal and the read enable signal to 0;
and 27, sending a signal to the I2C slave machine by the I2C master machine, reading the read data and finishing reading the internal register file.
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| CN110399325B (en) * | 2019-07-30 | 2023-05-30 | 江西理工大学 | Improved IP core based on IIC bus protocol |
| CN112835648B (en) * | 2021-02-25 | 2022-03-25 | 中国科学院西安光学精密机械研究所 | FPGA-based chip internal register high-reliability configuration method |
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