CN203491999U - Pulse width modulating signal receiving circuit - Google Patents
Pulse width modulating signal receiving circuit Download PDFInfo
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- CN203491999U CN203491999U CN201320423697.4U CN201320423697U CN203491999U CN 203491999 U CN203491999 U CN 203491999U CN 201320423697 U CN201320423697 U CN 201320423697U CN 203491999 U CN203491999 U CN 203491999U
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Abstract
The utility model discloses a pulse width modulating signal receiving circuit which comprises the following components: a decoding circuit, and a pulse width signal receiving and controlling circuit which is used for receiving a pulse width signal and generating a decoding circuit operation signal. The decoding circuit converts the received pulse width signal to a digital signal for outputting. The pulse width signal receiving and controlling circuit receives a pulse width modulating signal through a clock input port CLK and a data input port PMW. Then a gated clock signal LOG1-CLK, a reset control signal LOG2 and a latch clock signal LOG4 are output. The decoding circuit receives the gated clock signal, the reset control signal and the latch clock signal; converts the pulse width signal to a binary digital signal; and outputs through output ports D0,D1,D2,D3,D4 and D5; wherein D5 is a highest digit and D0 is a lowest digit. The pulse width modulating signal receiving circuit has the following functions: reducing number of pins for communication, greatly simplifying circuit structure and reducing chip area and power consumption.
Description
Technical field
The utility model relates to technical field of composite signal integrated circuits, is specifically related to a kind of pulse-width signal receiving circuit.
Background technology
Along with the development of integrated circuit technique, the high-speed interface of interchip communication has been proposed to more and more higher requirement, interface circuit that need to realize communication is tried one's best that number of pin is few, simple in structure, area is little and is low in energy consumption.Common interchip communication has SPI and I
2c interface circuit, but their required number of pin are many, complex structure, area is large and power consumption is high.
Summary of the invention
The utility model, in order to solve the deficiencies in the prior art, has proposed a kind of pulse-width signal receiving circuit, can realize the high-speed communication of chip chamber, and required number of pin is few, simple in structure, area is little and low in energy consumption.
Technical solutions of the utility model are: a kind of pulse-width signal receiving circuit, comprise decoding circuit, and for receiving pulse width signal and producing pulse width signal reception and the control circuit of controlling decoding circuit working signal; Described decoding circuit is converted to digital signal output by the pulse width signal receiving.
Described pulse width signal receives and control circuit comprises: the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, first with door, first or, the first NOR gate and the second NOR gate.
Wherein the input end of clock of the first d type flip flop is connected to clock signal input terminal CLK, and the data input pin of the first d type flip flop is connected to pulse width signal input PWM, and the forward output of the first d type flip flop is connected to the data input pin of the second d type flip flop;
The input end of clock of the second d type flip flop is connected to clock signal input terminal CLK, and the data input pin of the second d type flip flop is connected to the forward output of the first d type flip flop, and the forward output of the second d type flip flop is connected to the data input pin of 3d flip-flop;
The input end of clock of 3d flip-flop is connected to clock signal input terminal CLK, the data input pin of 3d flip-flop is connected to the forward output of the second d type flip flop, the forward output of 3d flip-flop is connected to the data input pin of four d flip-flop, and the inverse output terminal of 3d flip-flop is connected to first or input of door and an input of the first NOR gate;
The input end of clock of four d flip-flop is connected to clock signal input terminal CLK, and the data input pin of four d flip-flop is connected to the forward output of 3d flip-flop; The forward output of four d flip-flop is connected to the data input pin of the 5th d type flip flop;
The input end of clock of the 5th d type flip flop is connected to clock signal input terminal CLK, and the data input pin of the 5th d type flip flop is connected to the forward output of four d flip-flop; The forward output of the 5th d type flip flop is connected to the data input pin of the 6th d type flip flop;
The input end of clock of the 6th d type flip flop is connected to clock signal input terminal CLK, the data input pin of the 6th d type flip flop is connected to the forward output of the 5th d type flip flop, and the forward output of the 6th d type flip flop is connected to the data input pin of the 7th d type flip flop, first or input of door and an input of the second NOR gate;
The input end of clock of the 7th d type flip flop is connected to clock signal input terminal CLK, the data input pin of the 7th d type flip flop be connected to the 6th d type flip flop forward output, first or input of door and and an input of the second NOR gate; The forward output of the 7th d type flip flop is connected to the data input pin of the 8th d type flip flop;
The input end of clock of the 8th d type flip flop is connected to clock signal input terminal CLK, and the data input pin of the 8th d type flip flop is connected to the forward output of the 7th trigger; The forward output of the 8th d type flip flop is connected to the data input pin of the 9th d type flip flop;
The input end of clock of the 9th d type flip flop is connected to clock signal input terminal CLK, and the data input pin of the 9th d type flip flop is connected to the forward output of the 8th d type flip flop; The inverse output terminal of the 9th d type flip flop is connected to input of the first NOR gate and an input of the second NOR gate;
First is connected to clock signal input terminal CLK with an input of door, and first is connected to the output LOG3 of the first NOR gate with another input of door, and first is connected to control signal end LOG1_CLK with the output of door;
First or door an input be connected to the inverse output terminal of 3d flip-flop and an input of the first NOR gate, first or another input of door be connected to an input of the data output end of the 6th d type flip flop, the data input pin of the 7th d type flip flop and the second NOR gate, first or the output of door be connected to control signal end LOG2;
An input of the first NOR gate be connected to 3d flip-flop inverse output terminal and first or door an input, another input of the first NOR gate is connected to the inverse output terminal of the 9th d type flip flop and an input of the second NOR gate, and the output of the first NOR gate is connected to control signal end LOG3;
An input of the second NOR gate be connected to the forward output of the 6th d type flip flop, the data input pin of the 7th d type flip flop and first or door an input, another input of the second NOR gate is connected to the inverse output terminal of the 9th d type flip flop and an input of the first NOR gate, and the output of the second NOR gate is connected to control signal end LOG4;
Described decoding circuit comprises: the tenth d type flip flop, the 11 d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the tenth four d flip-flop, the 15 d type flip flop, the 16 d type flip flop, the 17 d type flip flop, the 18 d type flip flop, the 19 d type flip flop, the 20 d type flip flop, the 21 d type flip flop, the 20 2-D trigger, the 20 3d flip-flop and the 3rd NOR gate.
Wherein the input end of clock of the tenth d type flip flop is connected to the output LOG1_CLK of pulse width signal reception and control circuit, the data input pin of the tenth d type flip flop is connected to the output of the 3rd NOR gate, the forward output of the tenth d type flip flop is connected to the data input pin of the 11 d type flip flop and an input of the 3rd NOR gate, and the reset terminal of the tenth d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the 11 d type flip flop is connected to the output LOG1_CLK of pulse width signal reception and control circuit, the data input pin of the 11 d type flip flop is connected to the forward output of the tenth d type flip flop and an input of the 3rd NOR gate, the forward output of the 11 d type flip flop is connected to the input end of clock of the tenth 2-D trigger and another input of the 3rd NOR gate, and the reset terminal of the 11 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the tenth 2-D trigger is connected to the forward output of the 11 d type flip flop and an input of the 3rd NOR gate, the data input pin of the tenth 2-D trigger is connected to the inverse output terminal of self and the input end of clock of the tenth 3d flip-flop, the forward output of the tenth 2-D trigger is connected to the data input pin of the 18 d type flip flop, and the reset terminal of the tenth 2-D trigger is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the tenth 3d flip-flop is connected to the inverse output terminal of the tenth 2-D trigger and the data input pin of the tenth 2-D trigger, the data input pin of the tenth 3d flip-flop is connected to the inverse output terminal of self and the input end of clock of the tenth four d flip-flop, the forward output of the tenth 3d flip-flop is connected to the data input pin of the 19 d type flip flop, and the reset terminal of the tenth 3d flip-flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the tenth four d flip-flop is connected to the inverse output terminal of the tenth 3d flip-flop and the data input pin of the tenth 3d flip-flop, the data input pin of the tenth four d flip-flop is connected to the inverse output terminal of self and the input end of clock of the 15 d type flip flop, the forward output of the tenth four d flip-flop is connected to the data input pin of the 20 d type flip flop, and the reset terminal of the tenth four d flip-flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the 15 d type flip flop is connected to the inverse output terminal of the tenth four d flip-flop and the data input pin of the tenth four d flip-flop, the data input pin of the 15 d type flip flop is connected to the inverse output terminal of self and the input end of clock of the 16 d type flip flop, the forward output of the 15 d type flip flop is connected to the data input pin of the 21 d type flip flop, and the reset terminal of the 15 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the 16 d type flip flop is connected to the 15 inverse output terminal of d type flip flop and the data input pin of the 15 d type flip flop, the data input pin of the 16 d type flip flop is connected to the inverse output terminal of self and the input end of clock of the 17 d type flip flop, the forward output of the 16 d type flip flop is connected to the data input pin of the 20 2-D trigger, and the reset terminal of the 16 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the 17 d type flip flop is connected to the 16 inverse output terminal of d type flip flop and the data input pin of the 16 d type flip flop, the data input pin of the 17 d type flip flop is connected to the inverse output terminal of self, the forward output of the 17 d type flip flop is connected to the data input pin of the 20 3d flip-flop, and the reset terminal of the 17 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the 18 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 18 d type flip flop is connected to the forward output of the tenth 2-D trigger, and the forward output of the 18 d type flip flop is connected to the output D0 of decoding circuit;
The input end of clock of the 19 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 19 d type flip flop is connected to the forward output of the tenth 3d flip-flop, and the forward output of the 19 d type flip flop is connected to the output D1 of decoding circuit;
The input end of clock of the 20 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 20 d type flip flop is connected to the forward output of the tenth four d flip-flop, and the forward output of the 20 d type flip flop is connected to the output D2 of decoding circuit;
The input end of clock of the 21 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 21 d type flip flop is connected to the forward output of the 15 d type flip flop, and the forward output of the 21 d type flip flop is connected to the output D3 of decoding circuit;
The input end of clock of the 20 2-D trigger is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 20 2-D trigger is connected to the forward output of the 16 d type flip flop, and the forward output of the 20 2-D trigger is connected to the output D4 of decoding circuit;
The input end of clock of the 20 3d flip-flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 20 3d flip-flop is connected to the forward output of the 17 d type flip flop, and the forward output of the 20 3d flip-flop is connected to the output D5 of decoding circuit;
An input of the 3rd NOR gate is connected to the tenth d type flip flop forward output and the 11 d type flip flop data input pin, and another input of the 3rd NOR gate is connected to the forward output of the 11 d type flip flop and the input end of clock of the tenth 2-D trigger;
Described pulse width signal receives and control circuit receives pulse-width signal by input end of clock mouth CLK and data-in port PWM, then exports door controling clock signal LOG1_CLK, reseting controling signal LOG2 and latch clock signal LOG4; Decoding circuit receives door controling clock signal LOG1_CLK, reseting controling signal LOG2 and latch clock signal LOG4, be converted to binary digital signal by pulse width signal, by output port D0, D1, D2, D3, D4 and D5, exports, wherein D5 is highest order, and D0 is lowest order;
The utility model is compared with traditional prior art, and the advantage and the effect that have are: reduced the number of pin that signal post uses, greatly simplified circuit structure, reduced chip area and power consumption.
Accompanying drawing explanation
Fig. 1 is a kind of pulse-width signal receiving circuit schematic diagram described in the utility model;
Embodiment
Referring to Fig. 1, a kind of pulse-width signal receiving circuit comprises that pulse width signal receives and control circuit 100 and decoding circuit 200; Pulse width signal receive and control circuit 100 for receiving pulse width signal, and produce control signal and control decoding circuit 200 work; Decoding circuit 200 is converted to digital signal output by the pulse width signal receiving.
Described pulse width signal receives and control circuit 100 comprises: the first d type flip flop DFF1, the second d type flip flop DFF2,3d flip-flop DFF3, four d flip-flop DFF4, the 5th d type flip flop DFF5, the 6th d type flip flop DFF6, the 7th d type flip flop DFF7, the 8th d type flip flop DFF8, the 9th d type flip flop DFF9, first with door AND1, first or OR1, the first NOR gate NOR1 and the second NOR gate NOR2.
Wherein the input end of clock of the first d type flip flop DFF1 is connected to clock signal input terminal CLK, the data input pin of the first d type flip flop DFF1 is connected to pulse width signal input PWM, and the forward output of the first d type flip flop DFF1 is connected to the data input pin of the second d type flip flop DFF2;
The input end of clock of the second d type flip flop DFF2 is connected to clock signal input terminal CLK, the data input pin of the second d type flip flop DFF2 is connected to the forward output of the first d type flip flop DFF1, and the forward output of the second d type flip flop DFF2 is connected to the data input pin of 3d flip-flop DFF3;
The input end of clock of 3d flip-flop DFF3 is connected to clock signal input terminal CLK, the data input pin of 3d flip-flop DFF3 is connected to the forward output of the second d type flip flop DFF2, the forward output of 3d flip-flop DFF3 is connected to the data input pin of four d flip-flop DFF4, and the inverse output terminal of 3d flip-flop DFF3 is connected to first or input of door OR1 and an input of the first NOR gate NOR1;
The input end of clock of four d flip-flop DFF4 is connected to clock signal input terminal CLK, and the data input pin of four d flip-flop DFF4 is connected to the forward output of 3d flip-flop DFF3; The forward output of four d flip-flop DFF4 is connected to the data input pin of the 5th d type flip flop DFF5;
The input end of clock of the 5th d type flip flop DFF5 is connected to clock signal input terminal CLK, and the data input pin of the 5th d type flip flop DFF5 is connected to the forward output of four d flip-flop DFF4; The forward output of the 5th d type flip flop DFF5 is connected to the data input pin of the 6th d type flip flop DFF6;
The input end of clock of the 6th d type flip flop DFF6 is connected to clock signal input terminal CLK, the data input pin of the 6th d type flip flop DFF6 is connected to the forward output of the 5th d type flip flop DFF5, and the forward output of the 6th d type flip flop DFF6 is connected to the data input pin of the 7th d type flip flop DFF7, first or input of door OR1 and an input of the second NOR gate NOR2;
The input end of clock of the 7th d type flip flop DFF7 is connected to clock signal input terminal CLK, the data input pin of the 7th d type flip flop DFF7 be connected to the 6th d type flip flop DFF6 forward output, first or input of door OR1 and and an input of the second NOR gate NOR2; The forward output of the 7th d type flip flop DFF7 is connected to the data input pin of the 8th d type flip flop DFF8;
The input end of clock of the 8th d type flip flop DFF8 is connected to clock signal input terminal CLK, and the data input pin of the 8th d type flip flop DFF8 is connected to the forward output of the 7th trigger DFF7; The forward output of the 8th d type flip flop DFF8 is connected to the data input pin of the 9th d type flip flop DFF9;
The input end of clock of the 9th d type flip flop DFF9 is connected to clock signal input terminal CLK, and the data input pin of the 9th d type flip flop DFF9 is connected to the forward output of the 8th d type flip flop DFF8; The inverse output terminal of the 9th d type flip flop DFF9 is connected to input of the first NOR gate NOR1 and an input of the second NOR gate NOR2;
First is connected to clock signal input terminal CLK with an input of door AND1, and first is connected to the output LOG3 of the first NOR gate NOR2 with another input of door AND1, and first is connected to control signal end LOG1_CLK with the output of door AND1;
First or door OR1 an input be connected to the inverse output terminal of 3d flip-flop DFF3 and an input of the first NOR gate NOR1, first or another input of door OR1 be connected to an input of the data output end of the 6th d type flip flop DFF6, the data input pin of the 7th d type flip flop DFF7 and the second NOR gate NOR2, first or the output of door OR1 be connected to control signal end LOG2;
An input of the first NOR gate NOR1 be connected to 3d flip-flop DFF3 inverse output terminal and first or door OR1 an input, another input of the first NOR gate NOR1 is connected to the inverse output terminal of the 9th d type flip flop DFF9 and an input of the second NOR gate NOR2, and the output of the first NOR gate NOR1 is connected to control signal end LOG3;
An input of the second NOR gate NOR2 be connected to the forward output of the 6th d type flip flop DFF6, the data input pin of the 7th d type flip flop DFF7 and first or door OR1 an input, another input of the second NOR gate NOR2 is connected to the inverse output terminal of the 9th d type flip flop DFF9 and an input of the first NOR gate NOR1, and the output of the second NOR gate NOR2 is connected to control signal end LOG4;
Described decoding circuit 200 comprises: the tenth d type flip flop DFF10, the 11 d type flip flop DFF11, the tenth 2-D trigger DFF12, the tenth 3d flip-flop DFF13, the tenth four d flip-flop DFF14, the 15 d type flip flop DFF15, the 16 d type flip flop DFF16, the 17 d type flip flop DFF17, the 18 d type flip flop DFF18, the 19 d type flip flop DFF19, the 20 d type flip flop DFF20, the 21 d type flip flop DFF21, the 20 2-D trigger DFF22, the 20 3d flip-flop DFF23 and the 3rd NOR gate NOR3.
Wherein the input end of clock of the tenth d type flip flop DFF10 is connected to the output LOG1_CLK of pulse width signal reception and control circuit 100, the data input pin of the tenth d type flip flop DFF10 is connected to the output of the 3rd NOR gate NOR3, the forward output of the tenth d type flip flop DFF10 is connected to the data input pin of the 11 d type flip flop DFF11 and an input of the 3rd NOR gate NOR3, and the reset terminal of the tenth d type flip flop DFF11 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the 11 d type flip flop DFF11 is connected to the output LOG1_CLK of pulse width signal reception and control circuit, the data input pin of the 11 d type flip flop DFF11 is connected to the forward output of the tenth d type flip flop DFF10 and an input of the 3rd NOR gate NOR3, the forward output of the 11 d type flip flop DFF11 is connected to the input end of clock of the tenth 2-D trigger DFF12 and another input of the 3rd NOR gate NOR3, and the reset terminal of the 11 d type flip flop DFF11 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the tenth 2-D trigger DFF12 is connected to the forward output of the 11 d type flip flop DFF11 and an input of the 3rd NOR gate NOR3, the data input pin of the tenth 2-D trigger DFF12 is connected to the inverse output terminal of self and the input end of clock of the tenth 3d flip-flop DFF13, the forward output of the tenth 2-D trigger DFF12 is connected to the data input pin of the 18 d type flip flop DFF18, and the reset terminal of the tenth 2-D trigger DFF12 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the tenth 3d flip-flop DFF13 is connected to the inverse output terminal of the tenth 2-D trigger DFF12 and the data input pin of the tenth 2-D trigger DFF12, the data input pin of the tenth 3d flip-flop DFF13 is connected to the inverse output terminal of self and the input end of clock of the tenth four d flip-flop DFF14, the forward output of the tenth 3d flip-flop DFF13 is connected to the data input pin of the 19 d type flip flop DFF19, and the reset terminal of the tenth 3d flip-flop DFF13 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the tenth four d flip-flop DFF14 is connected to the inverse output terminal of the tenth 3d flip-flop DFF13 and the data input pin of the tenth 3d flip-flop DFF13, the data input pin of the tenth four d flip-flop DFF14 is connected to the inverse output terminal of self and the input end of clock of the 15 d type flip flop DFF15, the forward output of the tenth four d flip-flop DFF14 is connected to the data input pin of the 20 d type flip flop DFF20, and the reset terminal of the tenth four d flip-flop DFF14 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the 15 d type flip flop DFF15 is connected to the inverse output terminal of the tenth four d flip-flop DFF14 and the data input pin of the tenth four d flip-flop DFF14, the data input pin of the 15 d type flip flop DFF15 is connected to the inverse output terminal of self and the input end of clock of the 16 d type flip flop DFF16, the forward output of the 15 d type flip flop DFF15 is connected to the data input pin of the 21 d type flip flop DFF21, and the reset terminal of the 15 d type flip flop DFF15 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the 16 d type flip flop DFF16 is connected to the 15 inverse output terminal of d type flip flop DFF15 and the data input pin of the 15 d type flip flop DFF15, the data input pin of the 16 d type flip flop DFF16 is connected to the inverse output terminal of self and the input end of clock of the 17 d type flip flop DFF17, the forward output of the 16 d type flip flop DFF16 is connected to the data input pin of the 20 2-D trigger DFF22, and the reset terminal of the 16 d type flip flop DFF16 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the 17 d type flip flop DFF17 is connected to the 16 inverse output terminal of d type flip flop DFF16 and the data input pin of the 16 d type flip flop DFF16, the data input pin of the 17 d type flip flop DFF17 is connected to the inverse output terminal of self, the forward output of the 17 d type flip flop DFF17 is connected to the data input pin of the 20 3d flip-flop DFF23, and the reset terminal of the 17 d type flip flop DFF17 is connected to the output LOG2 of pulse width signal reception and control circuit 100;
The input end of clock of the 18 d type flip flop DFF18 is connected to the output LOG4 of pulse width signal reception and control circuit 100, the data input pin of the 18 d type flip flop DFF18 is connected to the forward output of the tenth 2-D trigger DFF12, and the forward output of the 18 d type flip flop DFF18 is connected to the output D0 of decoding circuit 200;
The input end of clock of the 19 d type flip flop DFF19 is connected to the output LOG4 of pulse width signal reception and control circuit 100, the data input pin of the 19 d type flip flop DFF19 is connected to the forward output of the tenth 3d flip-flop DFF13, and the forward output of the 19 d type flip flop DFF19 is connected to the output D1 of decoding circuit 200;
The input end of clock of the 20 d type flip flop DFF20 is connected to the output LOG4 of pulse width signal reception and control circuit 100, the data input pin of the 20 d type flip flop DFF20 is connected to the forward output of the tenth four d flip-flop DFF14, and the forward output of the 20 d type flip flop DFF20 is connected to the output D2 of decoding circuit 200;
The input end of clock of the 21 d type flip flop DFF21 is connected to the output LOG4 of pulse width signal reception and control circuit 100, the data input pin of the 21 d type flip flop DFF21 is connected to the forward output of the 15 d type flip flop DFF15, and the forward output of the 21 d type flip flop DFF21 is connected to the output D3 of decoding circuit 200;
The input end of clock of the 20 2-D trigger DFF22 is connected to the output LOG4 of pulse width signal reception and control circuit 100, the data input pin of the 20 2-D trigger DFF22 is connected to the forward output of the 16 d type flip flop DFF16, and the forward output of the 20 2-D trigger DFF22 is connected to the output D4 of decoding circuit 200;
The input end of clock of the 20 3d flip-flop DFF23 is connected to the output LOG4 of pulse width signal reception and control circuit 100, the data input pin of the 20 3d flip-flop DFF23 is connected to the forward output of the 17 d type flip flop DFF17, and the forward output of the 20 3d flip-flop DFF23 is connected to the output D5 of decoding circuit 200;
An input of the 3rd NOR gate NOR3 is connected to the tenth d type flip flop DFF10 forward output and the 11 d type flip flop DFF11 data input pin, and another input of the 3rd NOR gate NOR3 is connected to the forward output of the 11 d type flip flop DFF11 and the input end of clock of the tenth 2-D trigger DFF12.
Described pulse width signal receives and control circuit 100 receives pulse-width signal by input end of clock mouth CLK and data-in port PWM, then exports door controling clock signal LOG1_CLK, reseting controling signal LOG2 and latch clock signal LOG4; Decoding circuit 200 receives door controling clock signal LOG1_CLK, reseting controling signal LOG2 and latch clock signal LOG4, be converted to binary digital signal by pulse width signal, by output port D0, D1, D2, D3, D4 and D5, exports, wherein D5 is highest order, and D0 is lowest order;
The utility model and traditional prior art (SPI and I
2c) compare and only need 2 pins, structure is also very simple, has reduced the number of pin that signal post uses, has greatly simplified circuit structure, has reduced chip area and power consumption.
More than show and described basic principle of the present utility model and principal character and advantage of the present utility model.The technical staff of the industry should understand; the utility model is not restricted to the described embodiments; that in above-described embodiment and specification, describes just illustrates principle of the present utility model; do not departing under the prerequisite of the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (3)
1. a pulse-width signal receiving circuit, is characterized in that: comprise decoding circuit, and receive and control circuit for receiving the pulse width signal of pulse width signal generation control decoding circuit working signal; Described decoding circuit is converted to digital signal output by the pulse width signal receiving.
2. a kind of pulse-width signal receiving circuit according to claim 1, is characterized in that: described pulse width signal receives and control circuit comprises: the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, first with door, first or, the first NOR gate and the second NOR gate;
The input end of clock of described the first d type flip flop is connected to clock signal input terminal CLK, and the data input pin of the first d type flip flop is connected to pulse width signal input PWM, and the forward output of the first d type flip flop is connected to the data input pin of the second d type flip flop;
The input end of clock of described the second d type flip flop is connected to clock signal input terminal CLK, and the forward output of the second d type flip flop is connected to the data input pin of 3d flip-flop;
The input end of clock of described 3d flip-flop is connected to clock signal input terminal CLK, the forward output of 3d flip-flop is connected to the data input pin of four d flip-flop, and the inverse output terminal of 3d flip-flop is connected to respectively first or input of door and an input of the first NOR gate;
The input end of clock of described four d flip-flop is connected to clock signal input terminal CLK; The forward output of four d flip-flop is connected to the data input pin of the 5th d type flip flop;
The input end of clock of described the 5th d type flip flop is connected to clock signal input terminal CLK; The forward output of the 5th d type flip flop is connected to the data input pin of the 6th d type flip flop;
The input end of clock of described the 6th d type flip flop is connected to clock signal input terminal CLK, and the forward output of the 6th d type flip flop is connected to respectively the data input pin of the 7th d type flip flop, first or input of door and an input of the second NOR gate;
The input end of clock of described the 7th d type flip flop is connected to clock signal input terminal CLK, the data input pin of the 7th d type flip flop be connected to respectively the 6th d type flip flop forward output, first or input of door and and an input of the second NOR gate; The forward output of the 7th d type flip flop is connected to the data input pin of the 8th d type flip flop;
The input end of clock of described the 8th d type flip flop is connected to clock signal input terminal CLK, and the forward output of the 8th d type flip flop is connected to the data input pin of the 9th d type flip flop;
The input end of clock of described the 9th d type flip flop is connected to clock signal input terminal CLK; The inverse output terminal of the 9th d type flip flop is connected to input of the first NOR gate and an input of the second NOR gate;
Described first is connected to clock signal input terminal CLK with an input of door, and first connects with another input of door
Be connected to the output LOG3 of the first NOR gate, first is connected to control signal end LOG1_CLK with the output of door;
First or door an input be connected to the inverse output terminal of 3d flip-flop and an input of the first NOR gate, first or another input of door be connected to an input of the data output end of the 6th d type flip flop, the data input pin of the 7th d type flip flop and the second NOR gate, first or the output of door be connected to control signal end LOG2;
An input of the first NOR gate be connected to 3d flip-flop inverse output terminal and first or door an input, another input of the first NOR gate is connected to the inverse output terminal of the 9th d type flip flop and an input of the second NOR gate, and the output of the first NOR gate is connected to control signal end LOG3;
An input of the second NOR gate be connected to the forward output of the 6th d type flip flop, the data input pin of the 7th d type flip flop and first or door an input, another input of the second NOR gate is connected to the inverse output terminal of the 9th d type flip flop and an input of the first NOR gate, and the output of the second NOR gate is connected to control signal end LOG4.
3. a kind of pulse-width signal receiving circuit according to claim 1, is characterized in that: described decoding circuit comprises: the tenth d type flip flop, the 11 d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the tenth four d flip-flop, the 15 d type flip flop, the 16 d type flip flop, the 17 d type flip flop, the 18 d type flip flop, the 19 d type flip flop, the 20 d type flip flop, the 21 d type flip flop, the 20 2-D trigger, the 20 3d flip-flop and the 3rd NOR gate;
The input end of clock of described the tenth d type flip flop is connected to the output LOG1_CLK of pulse width signal reception and control circuit, the data input pin of the tenth d type flip flop is connected to the output of the 3rd NOR gate, the forward output of the tenth d type flip flop is connected to the data input pin of the 11 d type flip flop and an input of the 3rd NOR gate, and the reset terminal of the tenth d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of described the 11 d type flip flop is connected to the output LOG1_CLK of pulse width signal reception and control circuit, the data input pin of the 11 d type flip flop is connected to an input of the 3rd NOR gate, the forward output of the 11 d type flip flop is connected to the input end of clock of the tenth 2-D trigger and another input of the 3rd NOR gate, and the reset terminal of the 11 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of described the tenth 2-D trigger is connected to an input of the 3rd NOR gate, the data input pin of the tenth 2-D trigger is connected to the inverse output terminal of self and the input end of clock of the tenth 3d flip-flop, the forward output of the tenth 2-D trigger is connected to the data input pin of the 18 d type flip flop, and the reset terminal of the tenth 2-D trigger is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of described the tenth 3d flip-flop is connected to the inverse output terminal of the tenth 2-D trigger and the data input pin of the tenth 2-D trigger, the data input pin of the tenth 3d flip-flop is connected to the inverse output terminal of self and the input end of clock of the tenth four d flip-flop, the forward output of the tenth 3d flip-flop is connected to the data input pin of the 19 d type flip flop, and the reset terminal of the tenth 3d flip-flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of described the tenth four d flip-flop is connected to the inverse output terminal of the tenth 3d flip-flop and the data input pin of the tenth 3d flip-flop, the data input pin of the tenth four d flip-flop is connected to the inverse output terminal of self and the input end of clock of the 15 d type flip flop, the forward output of the tenth four d flip-flop is connected to the data input pin of the 20 d type flip flop, and the reset terminal of the tenth four d flip-flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of described the 15 d type flip flop is connected to the inverse output terminal of the tenth four d flip-flop and the data input pin of the tenth four d flip-flop, the data input pin of the 15 d type flip flop is connected to the inverse output terminal of self and the input end of clock of the 16 d type flip flop, the forward output of the 15 d type flip flop is connected to the data input pin of the 21 d type flip flop, and the reset terminal of the 15 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of described the 16 d type flip flop is connected to the 15 inverse output terminal of d type flip flop and the data input pin of the 15 d type flip flop, the data input pin of the 16 d type flip flop is connected to the inverse output terminal of self and the input end of clock of the 17 d type flip flop, the forward output of the 16 d type flip flop is connected to the data input pin of the 20 2-D trigger, and the reset terminal of the 16 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of the 17 d type flip flop is connected to the 16 inverse output terminal of d type flip flop and the data input pin of the 16 d type flip flop, the data input pin of the 17 d type flip flop is connected to the inverse output terminal of self, the forward output of the 17 d type flip flop is connected to the data input pin of the 20 3d flip-flop, and the reset terminal of the 17 d type flip flop is connected to the output LOG2 of pulse width signal reception and control circuit;
The input end of clock of described the 18 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 18 d type flip flop is connected to the forward output of the tenth 2-D trigger, and the forward output of the 18 d type flip flop is connected to the output D0 of decoding circuit;
The input end of clock of described the 19 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 19 d type flip flop is connected to the forward output of the tenth 3d flip-flop, and the forward output of the 19 d type flip flop is connected to the output D1 of decoding circuit;
The input end of clock of described the 20 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 20 d type flip flop is connected to the forward output of the tenth four d flip-flop, and the forward output of the 20 d type flip flop is connected to the output D2 of decoding circuit;
The input end of clock of described the 21 d type flip flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 21 d type flip flop is connected to the forward output of the 15 d type flip flop, and the forward output of the 21 d type flip flop is connected to the output D3 of decoding circuit;
The input end of clock of described the 20 2-D trigger is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 20 2-D trigger is connected to the forward output of the 16 d type flip flop, and the forward output of the 20 2-D trigger is connected to the output D4 of decoding circuit;
The input end of clock of described the 20 3d flip-flop is connected to the output LOG4 of pulse width signal reception and control circuit, the data input pin of the 20 3d flip-flop is connected to the forward output of the 17 d type flip flop, and the forward output of the 20 3d flip-flop is connected to the output D5 of decoding circuit;
An input of described the 3rd NOR gate is connected to the tenth d type flip flop forward output and the 11 d type flip flop data input pin, and another input of the 3rd NOR gate is connected to the forward output of the 11 d type flip flop and the input end of clock of the tenth 2-D trigger.
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|---|---|---|---|
| CN201320423697.4U CN203491999U (en) | 2013-07-16 | 2013-07-16 | Pulse width modulating signal receiving circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320423697.4U CN203491999U (en) | 2013-07-16 | 2013-07-16 | Pulse width modulating signal receiving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104300959A (en) * | 2013-07-16 | 2015-01-21 | 陕西北斗恒通信息科技有限公司 | Pulse width modulation signal receiving circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104300959A (en) * | 2013-07-16 | 2015-01-21 | 陕西北斗恒通信息科技有限公司 | Pulse width modulation signal receiving circuit |
| CN104300959B (en) * | 2013-07-16 | 2017-03-15 | 陕西北斗恒通信息科技有限公司 | A kind of pulse-width signal receiving circuit |
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