CN203457130U - Gear selection circuit - Google Patents
Gear selection circuit Download PDFInfo
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- CN203457130U CN203457130U CN201320533405.2U CN201320533405U CN203457130U CN 203457130 U CN203457130 U CN 203457130U CN 201320533405 U CN201320533405 U CN 201320533405U CN 203457130 U CN203457130 U CN 203457130U
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- door
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Abstract
The utility model discloses a gear selection circuit. According to the gear selection circuit, gear control is realized according to signals by setting an AND gate and a triode and utilizing the AND gate, and the gear selection circuit with two paths of signal input and four modes of output is realized through a pure hardware circuit, and thus the complexity and the production cost of the product are reduced.
Description
Technical field
The utility model relates to circuit engineering field, relates in particular to a kind of gear and selects circuit.
Background technology
Existing gear selects circuit to need software control, and product is comparatively complicated comparatively speaking, and cost is higher.
Utility model content
The utility model proposes and a kind ofly by pure hardware circuit, realize two paths of signals input, the gear of four kinds of pattern outputs is selected circuit.
For realizing foregoing circuit, the utility model by the following technical solutions:
Gear is selected a circuit, comprising: with door U6, resistance R 2, resistance R 25, resistance R 22, resistance R 19, resistance R 35, resistance R 18, resistance R 20, resistance R 10, resistance R 29, resistance R 21, resistance R 14, diode D1, diode D3, diode D7, triode Q1, triode Q2, triode Q3, triode Q12, tristate buffer U5, electric capacity BC3; Pin 1 and pin 2 described and door U6 access respectively signal SIGA and signal SIGB, pin 3 is connected with the positive pole of diode D3, the negative pole of diode D3 is connected with pin 12, pin 13 with door U6, be connected with one end of resistance R 2 with the pin 11 of door U6, the other end of resistance R 2 is connected with the base stage of triode Q1, the emitter of triode Q1 meets power supply VCC, collector electrode is connected with one end of resistance R 15, the other end of resistance R 15 is connected with the positive pole of diode D7, the negative pole of diode D7 is connected with one end of resistance R 29, the other end ground connection of resistance R 29; The negative pole of diode D1 is connected with the negative pole of diode D7, and positive pole is connected with one end of resistance R 14, and the other end of resistance R 14 is connected with the collector electrode of triode Q1; One end of resistance R 21 is connected with the positive pole of diode D1, other end ground connection; The grounded emitter of triode Q2, collector electrode is connected with the positive pole of diode D1, base stage is connected with one end of resistance R 9, the other end of resistance R 9 is connected with one end of resistance R 10, the other end of resistance R 10 is connected with the base stage of triode Q3, triode Q3 grounded collector, emitter is connected with the positive pole of diode D7; One end ground connection of resistance R 25, the other end is connected with the negative pole of diode D3; The pin 4 of tristate buffer U5 respectively with one end of described resistance R 10, one end of resistance R 20 is connected, the other end of resistance R 20 is connected with the pin 8 with door U6, all meets signal SIGA with pin 9 and the pin 10 of door U6; Pin 3 ground connection of tristate buffer U5, pin 2 connects sensor signal, connect+5V of pin 5 voltage, one end ground connection of electric capacity BC3, another termination+5V voltage; The pin 1 of tristate buffer U5 is connected with the collector electrode of triode Q12, the grounded emitter of triode Q12, and base stage is connected with one end of resistance R 18, and the other end of resistance R 18 is connected with the pin 6 with door U6, all meets signal SIGB with pin 4 and the pin 5 of door U6; The collector electrode of resistance R 19 and resistance R 35 homogeneous termination triode Q12, another termination+5V voltage; Resistance R 22 one end ground connection, the other end is connected with the emitter of triode Q3.
The beneficial effects of the utility model are: by pure hardware circuit, realize two paths of signals input, the gear of four kinds of pattern outputs is selected circuit, has reduced complexity and the production cost of product.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams that a kind of gear of the utility model is selected circuit;
Fig. 2 is input signal and the corresponding input relation table of gear;
Fig. 3 is the element truth table of tristate buffer U5.
Embodiment
Below in conjunction with accompanying drawing and by embodiment, further illustrate the technical solution of the utility model.
Fig. 1 is the circuit theory diagrams that a kind of gear of the utility model is selected circuit.
As shown in Figure 1, gear is selected a circuit, comprising: with door U6, resistance R 2, resistance R 25, resistance R 22, resistance R 19, resistance R 35, resistance R 18, resistance R 20, resistance R 10, resistance R 29, resistance R 21, resistance R 14, diode D1, diode D3, diode D7, triode Q1, triode Q2, triode Q3, triode Q12, tristate buffer U5, electric capacity BC3; Pin 1 and pin 2 described and door U6 access respectively signal SIGA and signal SIGB, pin 3 is connected with the positive pole of diode D3, the negative pole of diode D3 is connected with pin 12, pin 13 with door U6, be connected with one end of resistance R 2 with the pin 11 of door U6, the other end of resistance R 2 is connected with the base stage of triode Q1, the emitter of triode Q1 meets power supply VCC, collector electrode is connected with one end of resistance R 15, the other end of resistance R 15 is connected with the positive pole of diode D7, the negative pole of diode D7 is connected with one end of resistance R 29, the other end ground connection of resistance R 29; The negative pole of diode D1 is connected with the negative pole of diode D7, and positive pole is connected with one end of resistance R 14, and the other end of resistance R 14 is connected with the collector electrode of triode Q1; One end of resistance R 21 is connected with the positive pole of diode D1, other end ground connection; The grounded emitter of triode Q2, collector electrode is connected with the positive pole of diode D1, base stage is connected with one end of resistance R 9, the other end of resistance R 9 is connected with one end of resistance R 10, the other end of resistance R 10 is connected with the base stage of triode Q3, triode Q3 grounded collector, emitter is connected with the positive pole of diode D7; One end ground connection of resistance R 25, the other end is connected with the negative pole of diode D3; The pin 4 of tristate buffer U5 respectively with one end of described resistance R 10, one end of resistance R 20 is connected, the other end of resistance R 20 is connected with the pin 8 with door U6, all meets signal SIGA with pin 9 and the pin 10 of door U6; Pin 3 ground connection of tristate buffer U5, pin 2 connects sensor signal, connect+5V of pin 5 voltage, one end ground connection of electric capacity BC3, another termination+5V voltage; The pin 1 of tristate buffer U5 is connected with the collector electrode of triode Q12, the grounded emitter of triode Q12, and base stage is connected with one end of resistance R 18, and the other end of resistance R 18 is connected with the pin 6 with door U6, all meets signal SIGB with pin 4 and the pin 5 of door U6; The collector electrode of resistance R 19 and resistance R 35 homogeneous termination triode Q12, another termination+5V voltage; Resistance R 22 one end ground connection, the other end is connected with the emitter of triode Q3.
Fig. 2 is input signal and the corresponding input relation table of gear, and Fig. 3 is the element truth table of tristate buffer U5, is elaborating circuit diagram operation principle below.
When selecting high tap position, SIGA and SIGB be low level, as schematic diagram, with 1,2 pin of door U6 be electronegative potential, 3 pin are also electronegative potential, cause that 12,13 pin are electronegative potential, thereby 11 pin are electronegative potential, to make Q1 conducting be that late-class circuit is powered.It is electronegative potential that the electronegative potential of 1 pin of U6 makes 9,10 pin, thereby 8 pin are electronegative potential.4,5 pin of U6 are electronegative potential simultaneously, thereby 6 pin are electronegative potential, make Q12 cut-off, and U51 pin is high potential, and 4 pin are that high impedance does not affect late-class circuit.Now Q2 cut-off, Q3 conducting, having UEQ3 is electronegative potential, D7 cut-off; UCQ2 high potential, exports high voltage by the voltage source of R14 and R21 dividing potential drop through D1 conducting system is worked in high-regime operation.
When selecting low-grade location, SIGA is high level (+5V), and SIGB is low level, as schematic diagram, with 1 pin of door U6 be high potential, 2 pin are electronegative potential, 3 pin are also electronegative potential, cause that 12,13 pin are electronegative potential, thereby 11 pin are electronegative potential, to make Q1 conducting be late-class circuit power supply.It is high potential that the high potential of U61 pin makes 9,10 pin, thereby 8 pin are high potential.The electronegative potential of U64,5 pin, makes Q12 cut-off thereby 6 pin are electronegative potential simultaneously, and U51 pin is high potential, and 4 pin are that high impedance does not affect late-class circuit.Now Q3 cut-off, Q2 conducting, has UCQ2 electronegative potential, D1 cut-off; UEQ3 is high potential, by the voltage source of R15 and R22 dividing potential drop through D7 conducting, because R15, R22 dividing point voltage are much smaller than R14, R21 dividing point voltage, therefore output low voltage makes system in low-regime work.
When selecting automatic transmission position, SIGA is low level, SIGB high level (+5V), as schematic diagram, with 1 pin of door U6 be electronegative potential, 2 pin are high potential, 3 pin are also electronegative potential, cause that 12,13 pin are electronegative potential, thereby 11 pin are electronegative potential, to make Q1 conducting be late-class circuit power supply.It is electronegative potential that the electronegative potential of U61 pin makes 9,10 pin, thereby 8 pin are electronegative potential.The high potential of U64,5 pin, makes Q12 conducting thereby 6 pin are high potential simultaneously, and U51 pin is electronegative potential, and 4 pin output voltages are identical with 2 pin.Signal Sensor outside system is directly connected to U52 pin (because this signal can be high level or low level two states), thereby makes U54 pin output high potential or electronegative potential.This voltage determines conducting and the cut-off of Q2 and Q3, thereby automatically selects high-grade and low-grade.
When selecting to close gear, SIGA and SIGB be high level (+5V), as schematic diagram, with 1,2 pin of door U6 be all high potential, 3 pin be also high potential, cause that 12,13 pin are high potential, thereby 11 pin are high potential, Q1 are ended, cut-out late-class circuit is powered.Due to not power supply, whole system is not worked, in closed condition.
The above; it is only preferably embodiment of the utility model; but protection range of the present utility model is not limited to this; any people who is familiar with this technology is in the disclosed technical scope of the utility model; the variation that can expect easily or replacement, within all should being encompassed in protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of claim.
Claims (1)
1. a gear is selected circuit, it is characterized in that, comprising: with door U6, resistance R 2, resistance R 25, resistance R 22, resistance R 19, resistance R 35, resistance R 18, resistance R 20, resistance R 10, resistance R 29, resistance R 21, resistance R 14, diode D1, diode D3, diode D7, triode Q1, triode Q2, triode Q3, triode Q12, tristate buffer U5, electric capacity BC3; Pin 1 and pin 2 described and door U6 access respectively signal SIGA and signal SIGB, pin 3 is connected with the positive pole of diode D3, the negative pole of diode D3 is connected with pin 12, pin 13 with door U6, be connected with one end of resistance R 2 with the pin 11 of door U6, the other end of resistance R 2 is connected with the base stage of triode Q1, the emitter of triode Q1 meets power supply VCC, collector electrode is connected with one end of resistance R 15, the other end of resistance R 15 is connected with the positive pole of diode D7, the negative pole of diode D7 is connected with one end of resistance R 29, the other end ground connection of resistance R 29; The negative pole of diode D1 is connected with the negative pole of diode D7, and positive pole is connected with one end of resistance R 14, and the other end of resistance R 14 is connected with the collector electrode of triode Q1; One end of resistance R 21 is connected with the positive pole of diode D1, other end ground connection; The grounded emitter of triode Q2, collector electrode is connected with the positive pole of diode D1, base stage is connected with one end of resistance R 9, the other end of resistance R 9 is connected with one end of resistance R 10, the other end of resistance R 10 is connected with the base stage of triode Q3, triode Q3 grounded collector, emitter is connected with the positive pole of diode D7; One end ground connection of resistance R 25, the other end is connected with the negative pole of diode D3; The pin 4 of tristate buffer U5 respectively with one end of described resistance R 10, one end of resistance R 20 is connected, the other end of resistance R 20 is connected with the pin 8 with door U6, all meets signal SIGA with pin 9 and the pin 10 of door U6; Pin 3 ground connection of tristate buffer U5, pin 2 connects sensor signal, connect+5V of pin 5 voltage, one end ground connection of electric capacity BC3, another termination+5V voltage; The pin 1 of tristate buffer U5 is connected with the collector electrode of triode Q12, the grounded emitter of triode Q12, and base stage is connected with one end of resistance R 18, and the other end of resistance R 18 is connected with the pin 6 with door U6, all meets signal SIGB with pin 4 and the pin 5 of door U6; The collector electrode of resistance R 19 and resistance R 35 homogeneous termination triode Q12, another termination+5V voltage; Resistance R 22 one end ground connection, the other end is connected with the emitter of triode Q3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320533405.2U CN203457130U (en) | 2013-08-29 | 2013-08-29 | Gear selection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320533405.2U CN203457130U (en) | 2013-08-29 | 2013-08-29 | Gear selection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203457130U true CN203457130U (en) | 2014-02-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320533405.2U Expired - Lifetime CN203457130U (en) | 2013-08-29 | 2013-08-29 | Gear selection circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441754A (en) * | 2013-08-29 | 2013-12-11 | 福尔斯通电子(昆山)有限公司 | Gear selection circuit |
-
2013
- 2013-08-29 CN CN201320533405.2U patent/CN203457130U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441754A (en) * | 2013-08-29 | 2013-12-11 | 福尔斯通电子(昆山)有限公司 | Gear selection circuit |
| CN103441754B (en) * | 2013-08-29 | 2016-06-15 | 福尔斯通电子(昆山)有限公司 | A kind of gear selection circuit |
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