CN203455409U - Silicon wafer resistivity measuring device - Google Patents
Silicon wafer resistivity measuring device Download PDFInfo
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- CN203455409U CN203455409U CN201320413695.7U CN201320413695U CN203455409U CN 203455409 U CN203455409 U CN 203455409U CN 201320413695 U CN201320413695 U CN 201320413695U CN 203455409 U CN203455409 U CN 203455409U
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- probe
- silicon wafer
- resistivity
- measurement mechanism
- high frequency
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Abstract
The utility model discloses a silicon wafer resistivity measuring device comprising a support, a signal processor and a high frequency oscillator. A first probe is arranged above the support. A second probe is arranged below the support. The first probe and the second probe are respectively connected with the high frequency oscillator. The measuring device also comprises a driving mechanism which adjusts mutual distance between the first probe and the second probe. The driving mechanism is connected with the first probe or the second probe. The first probe and the second probe are respectively connected with the signal processor. An applicable thickness range and a resistivity range of an eddy current method for measuring silicon wafer resistivity can be enhanced, and accuracy of resistivity measurement can be enhanced.
Description
Technical field
The utility model relates to a kind of silicon wafer resistivity test device.
Background technology
At present, semicon industry and photovoltaic industry need silicon wafer resistivity to measure on to the quality control of raw material silicon wafer.In prior art, conventionally adopt the measuring method of contact such as four-point method.The method speed of these contacts is slow, and sample is had to injury, and the probe of adding detection belongs to consumptive material, needs periodic replacement, before replacing, also often can be out of shape, and has greatly affected accuracy of measurement.In contactless measuring method, eddy current is the measuring method of main flow.But existing eddy current non-contact type resistivity measuring device all exists institute's test sample product thickness range, narrow and precision of measurement is not very high shortcoming.
Utility model content
(1) technical matters that will solve
The technical problems to be solved in the utility model is to provide a kind of silicon wafer resistivity test device, Measurement accuracy resistivity.
(2) technical scheme
In order to address the above problem, the utility model provides a kind of silicon wafer resistivity test device, it is characterized in that, described measurement mechanism comprises: support, signal processor, high frequency oscillator, described support top is provided with the first probe, described support below is provided with the second probe, described the first probe is connected with described high frequency oscillator respectively with the second probe, also comprise driving mechanism, be used for adjusting the first probe with second probe between phase mutual edge distance, described driving mechanism is connected with described the first probe or the second probe, described the first probe is connected with described signal processor respectively with the second probe.
Wherein, the top of described support is provided with centralising device, for adjusting the position of silicon wafer.
Wherein, described the first probe and described the second probe coaxial line.
Wherein, described signal processor has the power that shows sheet resistance or resistivity, when silicon wafer is inserted, should have the function that electricity is led zero clearing.
Wherein, described the first probe and the second probe are a pair of eddy current probe, and the variation of the relative distance of described probe can accurately control to micron dimension by driving mechanism.
Wherein, described high frequency oscillator can be measured in optimizing the frequency range of measuring in frequency conversion.
(3) beneficial effect
The utility model can improve eddy current method and measure applicable thickness range and the electrical resistivity range of silicon wafer resistivity, and can improve the accuracy of resistivity measurement.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model;
Fig. 2 is the structural representation of a kind of embodiment of the utility model.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples are used for illustrating the utility model, but are not used for limiting scope of the present utility model.
Shown in Fig. 1～2, described measurement mechanism comprises: support 4, signal processor 7, high frequency oscillator 1, described support 4 tops are provided with the first probe 2, described support 1 below is provided with the second probe 3, described the first probe 2 is connected with described high frequency oscillator 1 respectively with the second probe 3, also comprise driving mechanism 8, be used for adjusting 3 phase mutual edge distances of the first probe 2 and the second probe, described driving mechanism 8 is connected with described the first probe 2, and described the first probe 2 is connected with described signal processor 7 respectively with the second probe 3.
Preferably, the top of described support 4 is provided with centralising device 5, for adjusting the position of silicon wafer 6.
Preferably, described the first probe 2 and described the second probe 3 coaxial lines.
Preferably, described signal processor 7 has the power that shows sheet resistance or resistivity, when silicon wafer 6 is inserted, should have the function that electricity is led zero clearing.
Preferably, described the first probe and the second probe are a pair of high-frequency electrical vortex principle resistivity measurement probe.
Preferably, described high frequency oscillator can be measured in optimizing the frequency range of measuring in frequency conversion.
Preferably, the variation of the relative distance of described upper and lower eddy current probe can accurately control to micron dimension by driving mechanism.
Method of measuring resistivity is:
Silicon wafer samples plug flat is entered in the gap between described first probe the 2 and second probe 3, and the alternating magnetic field between two eddy current probes that are connected with oscillator loop is responded to generation eddy current on silicon wafer.
Adjust the distance of described the first probe and silicon wafer;
The resistivity of the silicon wafer that the distance saturation relational expression that utilization is determined and silicon wafer thickness obtain.Specific algorithm is as follows:
In the process of measuring, except press ordinary procedure, measure the resistivity of sample, more than measured a probe and sample variation apart from after lift from eddy current signal.The signal three of these two signals and original n.s. can form a nondimensional numerical value, and this numerical value is the pop one's head in function of corresponding three impedance theory values of eddy current.
In formula, S represents signal, and I represents the theoretical resistance value of probe, and subscript " sample " indicates the value of sample, and subscript " air " represents the value of not setting-out product, and subscript " is lifted from " and represented that setting-out product have the value of lifting from.In linear Circuits System, above-mentioned f function is a linear function in lifting from scope, can solve theoretical value, also can carry out calibrated linear coefficient by standard model.Originally we can not need to lift from signal, and the molecular moiety left and right in formula (1) is also linear, and transfer function can be corrected by known wafer.But we are more accurate for what measure, added one to lift from signal, make all dimensionless of (1) formula both sides.
The noise bringing in order to reduce Lift-off effect, we only get imaginary part to formula (1) both sides.
After only getting imaginary part, we have just abandoned the signal parallel with lifting from signal, have only chosen the signal vertical with lifting from signal, have so just reduced further the noise of system.Measure the eddy current signal of a sample at every turn and lift from accordingly signal, we just can calculate corresponding eddy current probe impedance theoretical value.This impedance theory value can be used for the anti-resistivity that pushes away wafer easily.Formula (1) and eddy current probe impedance theory value in (2) below off-resonance frequency frequency far away we completed the relevant software (comprising Backstepping software) of analytic formula, I have completed and had tested.
Formula (2) can further be done equivalent transformation:
From this formula, we can clearly see, S in formula
sample-S
airit is exactly the signal that conventional eddy current resistivity instrument is tested.Our system adds and has surveyed a signal S by duplicate program on this basis
improve-S
air, then by suitable signal processing mode, we have greatly improved the Non-Destructive Testing accuracy of eddy current to silicon wafer resistivity.
Formula (3) is the function of survey frequency, silicon wafer thickness and resistivity, frequency conversion by the high frequency oscillator in claim (6) is measured, we can measure the resistivity under a series of different frequencies, because resistivity is not with frequency change, so we can utilize common statistical processing methods that institute's measuring resistance rate is added up and is averaging, thereby further improved the accuracy of measuring.
Above embodiment is only for illustrating the utility model; and be not limitation of the utility model; the those of ordinary skill in relevant technologies field; in the situation that not departing from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.
Claims (6)
1. a silicon wafer resistivity test device, it is characterized in that, described measurement mechanism comprises: support, signal processor, high frequency oscillator, described support top is provided with the first probe, described support below is provided with the second probe, described the first probe is connected with described high frequency oscillator respectively with the second probe, also comprise driving mechanism, be used for adjusting phase mutual edge distance between the first probe and the second probe, described driving mechanism is connected with described the first probe or the second probe, and described first pops one's head in and second pop one's head in and be connected with described signal processor respectively.
2. measurement mechanism as claimed in claim 1, is characterized in that, the top of described support is provided with centralising device, for adjusting the position of silicon wafer.
3. measurement mechanism as claimed in claim 1, is characterized in that, described the first probe and described the second probe coaxial line.
4. measurement mechanism as claimed in claim 1, is characterized in that, described signal processor has the power that shows sheet resistance or resistivity, when silicon wafer is inserted, should have the function that electricity is led zero clearing.
5. measurement mechanism as claimed in claim 1, is characterized in that: described the first probe and the second probe are a pair of eddy current probe, and the variation of the relative distance of described probe can accurately control to micron dimension by driving mechanism.
6. measurement mechanism as desired in right 1, is characterized in that: described high frequency oscillator can be measured in optimizing the frequency range of measuring in frequency conversion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320413695.7U CN203455409U (en) | 2013-07-12 | 2013-07-12 | Silicon wafer resistivity measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320413695.7U CN203455409U (en) | 2013-07-12 | 2013-07-12 | Silicon wafer resistivity measuring device |
Publications (1)
| Publication Number | Publication Date |
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| CN203455409U true CN203455409U (en) | 2014-02-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201320413695.7U Expired - Lifetime CN203455409U (en) | 2013-07-12 | 2013-07-12 | Silicon wafer resistivity measuring device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106405246A (en) * | 2016-08-24 | 2017-02-15 | 杭州电子科技大学 | Ice-core solid body DC conductivity measuring control circuit |
| CN104280616B (en) * | 2013-07-12 | 2017-03-22 | 苏州博昇科技有限公司 | Silicon wafer resistivity measurement device and method |
-
2013
- 2013-07-12 CN CN201320413695.7U patent/CN203455409U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104280616B (en) * | 2013-07-12 | 2017-03-22 | 苏州博昇科技有限公司 | Silicon wafer resistivity measurement device and method |
| CN106405246A (en) * | 2016-08-24 | 2017-02-15 | 杭州电子科技大学 | Ice-core solid body DC conductivity measuring control circuit |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140226 |