CN203434153U - Capacitor assembly/chip-integrated radio frequency chip encapsulation structure - Google Patents
Capacitor assembly/chip-integrated radio frequency chip encapsulation structure Download PDFInfo
- Publication number
- CN203434153U CN203434153U CN201320256075.7U CN201320256075U CN203434153U CN 203434153 U CN203434153 U CN 203434153U CN 201320256075 U CN201320256075 U CN 201320256075U CN 203434153 U CN203434153 U CN 203434153U
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- chip
- radio frequency
- capacitance
- package lead
- lower plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
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- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a capacitor assembly/chip-integrated radio frequency chip encapsulation structure. The capacitor assembly/chip-integrated radio frequency chip encapsulation structure includes a heat conduction pad, namely, a heat dissipation pad, which is used for placing a chip and a capacitor assembly, the chip which is bonded on the heat dissipation pad, electric conduction pads which are arranged at the periphery of the heat conduction pad in a surrounding manner so as to realize electrical connection, encapsulation lead wires which are connected with chip pads and the heat conduction pad, and upper and lower pole plate capacitors which are bonded on the heat conduction pad so as to realize a power source filtering circuit and an input/output impedance matching network. According to the capacitor assembly/chip-integrated radio frequency chip encapsulation structure of the utility model, the area of the heat dissipation pad is fully utilized; off-chip capacitors which are required when the chip works, especially the input/output matching circuit of the radio frequency chip, is directly encapsulated in the encapsulation unit; and therefore, later-stage PCB design can be facilitated, and at the same time, a problem of a difficulty for realizing large-capacitor design on a wafer can be solved, and a PCB layout area can be decreased.
Description
Technical field
The utility model relates to chip encapsulation technology field; A kind of radio frequency chip encapsulating structure that integrates patch capacitor and chip specifically.
Background technology
Traditional chip package as shown in Figure 1, is at heat dissipation bonding pad 1 ' chip placement 2 ', by go between 4 ' with conductive plate 3 ' bonding; On wafer, be difficult to the large electric capacity of realization or the filter capacitor of chip power and can only on pcb board, design, cause pcb board area to increase the miniaturization that is unfavorable for electronic equipment.
Utility model content
The purpose of this utility model is to solve the problem of prior art, for the large electric capacity that is difficult on current wafer realize or the filter capacitor of chip power, can only on pcb board, design, make full use of the area except chip on heat dissipation bonding pad, upper and lower plates capacitance is encapsulated in packaging body, make the simplicity of design of chip on pcb board, area miniaturization.
For reaching above-mentioned purpose, the utility model adopts following technical scheme:
A radio frequency chip encapsulating structure for capacitance component and chip, comprising: thermal land: for chip placement and capacitance component; Chip: bonding is placed on thermal land; Conductive welding disk: realize electric link around the periphery that is arranged on thermal land; Package lead: connect chip bonding pad and conductive welding disk; Upper and lower plates capacitance: be arranged on and realize electric source filter circuit and input and output impedance matching network on thermal land.Described package lead also can be used as inductance, and the large I of inductance is by regulating the length of package lead to realize.
Concrete, described filter circuit comprises upper and lower plates capacitance one and package lead; Upper and lower plates capacitance one top crown is connected to by package lead on the power pad of chip, and this top crown is connected on corresponding conductive welding disk by package lead again simultaneously; Described upper and lower plates capacitance one bottom crown is connected on thermal land and is grounded.
Described input and output impedance matching network comprises T-shaped matching network or the multistage LC coupling phase-shift network that upper and lower plates capacitance and package lead form.
Described T-shaped matching network is comprised of a upper and lower plates capacitance two and two package leads; Upper and lower plates capacitance two top crowns are connected to by package lead on the input pad of chip, and this pole plate is connected on corresponding conductive welding disk by package lead again simultaneously, and upper and lower plates capacitance two bottom crowns are connected on thermal land and are grounded.
Described multistage LC coupling phase-shift network is comprised of more than one upper and lower plates capacitance three and three and above package lead; Upper and lower plates capacitance three top crowns are connected on the input pad of chip by package lead, this pole plate is connected on another electric capacity top crown by another package lead again simultaneously, by package lead, be connected on conductive welding disk again, and the upper and lower all bottom crowns of plates capacitance three are all connected to and on thermal land, are grounded connection.
Adopt technique scheme, upper upper and lower plates capacitance and the chip placed of the utility model thermal land (heat dissipation bonding pad), by lead-in wire (bondwire) bonding, electric capacity and chip are coupled together, bonding wire can be realized the design of radio frequency input and output matching circuit as inductance simultaneously.The utility model makes full use of the area of thermal land, the outer electric capacity of required some sheets during by chip operation, particularly the input and output matching circuit of radio frequency chip is potted directly in unit package, facilitate the pcb board design in later stage, can solve the problem that is difficult to realize large capacitor design on wafer, reduce PCB chip area simultaneously.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide further understanding of the present utility model, forms a part of the present utility model, and schematic description and description of the present utility model is used for explaining the utility model, does not form improper restriction of the present utility model.In the accompanying drawings:
Fig. 1 is the utility model prior art structural representation;
Fig. 2 is the main TV structure schematic diagram of the utility model;
Fig. 3 is the utility model side-looking structural representation;
Fig. 4 is the T-shaped schematic network structure of the utility model;
Fig. 5 is the multistage LC matching network of the utility model structural representation.
Embodiment
In order to make technical problem to be solved in the utility model, technical scheme and beneficial effect clearer, clear, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
As Figure 2-Figure 5, a kind of radio frequency chip encapsulating structure that integrates capacitance component and chip described in the utility model, comprising:
Thermal land 1: for chip placement and capacitance component; Chip 2: bonding is placed on thermal land 1; Conductive welding disk 3: realize electric link around the periphery that is arranged on thermal land 1; Package lead 4: connect chip and conductive welding disk 3; Upper and lower plates capacitance 5: be placed on and realize electric source filter circuit 6 and input and output impedance matching network 7 on thermal land 1.Described package lead 4 can be inductance.
Concrete, described filter circuit 6 comprises upper and lower plates capacitance one 5-1 and package lead 4-1; Upper and lower plates capacitance one 5-1 top crown is connected to by package lead 4-1 on the power pad of chip, and this top crown is connected on corresponding conductive welding disk 3 by package lead 4-2 again simultaneously; Described upper and lower plates capacitance one 5-1 bottom crown is connected on thermal land 1 and is grounded.
Described input and output impedance matching network 7 comprises T-shaped matching network or multistage LC coupling (containing the Π type) phase-shift network that upper and lower plates capacitance and package lead form.Described T-shaped matching network is comprised of upper and lower plates capacitance two 5-2 and two package lead 4-3,4-4; Upper and lower plates capacitance two 5-2 top crowns are connected on the input pad of chip by package lead 4-4, this pole plate is connected on corresponding conductive welding disk 3 by package lead 4-3 again simultaneously, and upper and lower plates capacitance two 5-2 bottom crowns are connected on thermal land 1 and are grounded.
Described multistage LC coupling phase shift (containing Π type) network is comprised of more than one upper and lower plates capacitance three 5-3 and three and above package lead 4-5; Upper and lower plates capacitance three 5-3 top crowns are connected on the input pad of chip by package lead 4-5, this pole plate is connected on another electric capacity top crown by another package lead again simultaneously, by package lead, be connected on conductive welding disk 3 again, and the upper and lower all bottom crowns of plates capacitance three 5-3 are all connected on thermal land 1 and are grounded connection.
Upper upper and lower plates capacitance and the chip placed of the utility model thermal land (heat dissipation bonding pad), couples together electric capacity and chip by lead-in wire (bondwire) bonding, and bonding wire can be realized the design of radio frequency input and output matching circuit as inductance simultaneously.The utility model makes full use of the area of thermal land, the outer electric capacity of required some sheets during by chip operation, particularly the input and output matching circuit of radio frequency chip is potted directly in unit package, facilitate the pcb board design in later stage, can solve the problem that is difficult to realize large capacitor design on wafer, reduce PCB chip area simultaneously.
Above-mentioned explanation illustrates and has described preferred embodiment of the present utility model, as previously mentioned, be to be understood that the utility model is not limited to disclosed form herein, should not regard the eliminating to other embodiment as, and can be used for various other combinations, modification and environment, and can, in utility model contemplated scope described herein, by technology or the knowledge of above-mentioned instruction or association area, change.And the change that those skilled in the art carry out and variation do not depart from spirit and scope of the present utility model, all should be in the protection range of the utility model claims.
Claims (6)
1. a radio frequency chip encapsulating structure that integrates capacitance component and chip, is characterized in that: comprising:
Thermal land (1): for chip placement and capacitance component;
Chip (2): bonding is placed on thermal land (1);
Conductive welding disk (3): realize electric link around the periphery that is arranged on thermal land (1);
Package lead (4): connect chip bonding pad and conductive welding disk (3);
Upper and lower plates capacitance (5): be placed on and realize electric source filter circuit (6) and input and output impedance matching network (7) on thermal land (1).
2. a kind of radio frequency chip encapsulating structure that integrates capacitance component and chip as claimed in claim 1, is characterized in that: described package lead (4) is used as inductance.
3. a kind of radio frequency chip encapsulating structure that integrates capacitance component and chip as claimed in claim 1, is characterized in that: described filter circuit (6) comprises upper and lower plates capacitance one (5-1) and package lead (4-1); Upper and lower plates capacitance one (5-1) top crown is connected on the power pad of chip by package lead (4-1), and this top crown is connected on corresponding conductive welding disk (3) by package lead (4-2) again simultaneously; Described upper and lower plates capacitance one (5-1) bottom crown is connected on thermal land (1) and is grounded.
4. a kind of radio frequency chip encapsulating structure that integrates capacitance component and chip as claimed in claim 1, is characterized in that: described input and output impedance matching network (7) comprises T-shaped matching network or the multistage LC coupling phase-shift network that upper and lower plates capacitance and package lead form.
5. a kind of radio frequency chip encapsulating structure that integrates capacitance component and chip as claimed in claim 4, is characterized in that: described T-shaped matching network is comprised of a upper and lower plates capacitance two (5-2) and two package leads (4-3,4-4); Upper and lower plates capacitance two (5-2) top crown is connected on the input pad of chip by package lead (4-4), this pole plate is connected to corresponding conductive welding disk (3) above by package lead (4-3) again simultaneously, and upper and lower plates capacitance two (5-2) bottom crown is connected on thermal land (1) and is grounded.
6. a kind of radio frequency chip encapsulating structure that integrates capacitance component and chip as claimed in claim 4, is characterized in that: described multistage LC coupling phase-shift network is comprised of more than one upper and lower plates capacitance three (5-3) and three and above package lead (4-5); Upper and lower plates capacitance three (5-3) top crown is connected on the input pad of chip by package lead (4-5), this pole plate is connected on another electric capacity top crown by another package lead again simultaneously, by package lead, be connected to conductive welding disk (3) upper, and the upper and lower all bottom crowns of plates capacitance three (5-3) are all connected on thermal land (1) and are grounded connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320256075.7U CN203434153U (en) | 2013-05-13 | 2013-05-13 | Capacitor assembly/chip-integrated radio frequency chip encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320256075.7U CN203434153U (en) | 2013-05-13 | 2013-05-13 | Capacitor assembly/chip-integrated radio frequency chip encapsulation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203434153U true CN203434153U (en) | 2014-02-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201320256075.7U Expired - Lifetime CN203434153U (en) | 2013-05-13 | 2013-05-13 | Capacitor assembly/chip-integrated radio frequency chip encapsulation structure |
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| Country | Link |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105556663A (en) * | 2014-12-23 | 2016-05-04 | 英特尔公司 | Integrated packaging design with leads for overlapped package product |
| CN111463175A (en) * | 2020-04-26 | 2020-07-28 | 潍坊歌尔微电子有限公司 | Chip structure and sensor |
| WO2022088299A1 (en) * | 2020-10-30 | 2022-05-05 | 苏州远创达科技有限公司 | Radio frequency chip with rc circuit integrated on chip |
-
2013
- 2013-05-13 CN CN201320256075.7U patent/CN203434153U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105556663A (en) * | 2014-12-23 | 2016-05-04 | 英特尔公司 | Integrated packaging design with leads for overlapped package product |
| WO2016101151A1 (en) * | 2014-12-23 | 2016-06-30 | Intel Corporation | Integrated package design with wire leads for package-on-package product |
| US9960104B2 (en) | 2014-12-23 | 2018-05-01 | Intel Corporation | Integrated package design with wire leads for package-on-package product |
| CN111463175A (en) * | 2020-04-26 | 2020-07-28 | 潍坊歌尔微电子有限公司 | Chip structure and sensor |
| WO2022088299A1 (en) * | 2020-10-30 | 2022-05-05 | 苏州远创达科技有限公司 | Radio frequency chip with rc circuit integrated on chip |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 361000 N404 room, Weiye building, pioneer zone, torch hi tech Zone, Huli District, Xiamen, Fujian, Xiamen Patentee after: Xiamen Leixunke Microelectronics Co.,Ltd. Address before: 361000 N404 room, Weiye building, pioneer zone, torch hi tech Zone, Huli District, Xiamen, Fujian, Xiamen Patentee before: XIAMEN CREOTECH ELECTRONIC TECHNOLOGY Co.,Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140212 |