CN203415966U - Overcurrent protection circuit and integrated circuit - Google Patents
Overcurrent protection circuit and integrated circuit Download PDFInfo
- Publication number
- CN203415966U CN203415966U CN201320381816.4U CN201320381816U CN203415966U CN 203415966 U CN203415966 U CN 203415966U CN 201320381816 U CN201320381816 U CN 201320381816U CN 203415966 U CN203415966 U CN 203415966U
- Authority
- CN
- China
- Prior art keywords
- nmos
- pmos
- connects
- source
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The utility model discloses an overcurrent protection circuit and an integrated circuit. An overcurrent sampling circuit performs overcurrent sampling on an output circuit and transmits sampling current to an overcurrent protection loop; and the overcurrent protection loop performs DC level shifting on the sampling current to obtain control current, and performs negative feedback on output current of the output circuit according to the control current. By adopting the scheme provided by the utility model, the control current can be obtained through the DC level shifting, and the negative feedback is carried out on the output current of the output circuit by the control current so that the effect exerted by a field effect transistor on the sampling current triggering negative feedback in the prior art can be avoided, and the overcurrent protection accuracy is improved.
Description
Technical field
The utility model relates to the resist technology of integrated circuit, relates in particular to a kind of current foldback circuit and integrated circuit.
Background technology
In order to prevent that integrated circuit from damaging because output current is excessive, generally all need the output circuit of integrated circuit to carry out overcurrent protection (OCP, Over Current Protection).At present; conventionally adopt output circuit is carried out to overcurrent sampling; by sample rate current, trigger field effect transistor and carry out the output current that degenerative mode is controlled output circuit; in which, triggering field effect transistor, to carry out degenerative sample rate current relevant with the performance of described field effect transistor; but the performance of field effect transistor is easy to be subject to temperature, processing technology etc. to affect; therefore, current mode will affect the accuracy of overcurrent protection greatly.
Utility model content
For solving the problems of the prior art, the utility model provides a kind of current foldback circuit and integrated circuit.
For achieving the above object, the technical solution of the utility model is achieved in that
A kind of current foldback circuit that the utility model provides, comprises output circuit, and described current foldback circuit also comprises:
Output circuit is carried out to overcurrent sampling, and sample rate current is transferred to the overcurrent sample circuit of overcurrent protection loop;
Described sample rate current is carried out to the DC level controlled electric current that is shifted, according to controlling electric current, the output current of output circuit is carried out to degenerative overcurrent protection loop.
The utility model provides again a kind of integrated circuit, and this integrated circuit comprises current foldback circuit, described current foldback circuit comprise output circuit and
Output circuit is carried out to overcurrent sampling, and sample rate current is transferred to the overcurrent sample circuit of overcurrent protection loop;
Described sample rate current is carried out to the DC level controlled electric current that is shifted, according to controlling electric current, the output current of output circuit is carried out to degenerative overcurrent protection loop.
The utility model provides a kind of current foldback circuit and integrated circuit, and overcurrent sample circuit carries out overcurrent sampling to output circuit, and sample rate current is transferred to overcurrent protection loop; Overcurrent protection loop carries out the controlled electric current of DC level displacement (DC Level Shifter) to described sample rate current, according to controlling electric current, the output current of output circuit is carried out to negative feedback; So; can be by the DC level controlled electric current that is shifted; and by controlling electric current, the output current of output circuit is carried out to negative feedback, and avoid the performance of field effect transistor in prior art to carry out the impact of degenerative sample rate current to triggering field effect transistor, improve the accuracy of overcurrent protection.
Accompanying drawing explanation
Fig. 1 is the structural representation of the current foldback circuit of a kind of NMOS for the protection of output circuit in prior art;
The structural representation of the current foldback circuit that Fig. 2 provides for the utility model embodiment;
The first that Fig. 3 provides for the utility model embodiment is for the protection of the principle schematic of the current foldback circuit of the NMOS of output circuit;
The second that Fig. 4 provides for the utility model embodiment is for the protection of the principle schematic of the current foldback circuit of the NMOS of output circuit;
The principle schematic of the current foldback circuit of the PMOS for the protection of output circuit that Fig. 5 provides for the utility model embodiment;
Fig. 6 is the sample rate current I of current foldback circuit shown in Fig. 1
ocpanalogous diagram;
Fig. 7 is the sample rate current I of current foldback circuit shown in Fig. 3
ocpanalogous diagram;
The schematic flow sheet of the over-current protection method that Fig. 8 provides for the utility model embodiment.
Embodiment
The current foldback circuit of a kind of NMOS for the protection of output circuit of current existence, as shown in Figure 1, this current foldback circuit comprises: the output circuit consisting of a PMOS P1 and a NMOS N1, output voltage is V
o, output current is I
o; The overcurrent sample circuit that a NMOS N1 is carried out to overcurrent sampling being formed by the first resistance R 1, the 2nd NMOS N2, the 3rd NMOS N3 and amplifier A1; The overcurrent protection loop being formed by the 2nd PMOS P2, the 4th NMOS N4, the 5th NMOS N5 and the first reference current source C1; Wherein, the operation principle of this protective circuit is: as output current I
owhile there is overcurrent, the sample rate current I of overcurrent sample circuit
ocpincrease, trigger grid-source voltage V of the 2nd PMOS P2
gs1increase, the drain current I1 of the 2nd PMOS P2 increases, and the ducting capacity of the 5th NMOS N5 strengthens, the grid voltage V of a NMOSN1
gateby the 5th NMOS N5, dragged down output current I
oalso corresponding being dragged down.As can be seen from Figure 1, V
gs1=I
ocp* R1, that is to say, I
ocp=V
gs1/ R1, due to field effect transistor--grid-source voltage V of the 2nd PMOSP2
gs1be easy to be subject to the impact of temperature, process corner and occur larger variation, therefore, the sample rate current I of overcurrent sample circuit
ocpalso can correspondingly there is relatively large deviation.
Basic thought of the present utility model is: overcurrent sample circuit carries out overcurrent sampling to output circuit, and sample rate current is transferred to overcurrent protection loop; Overcurrent protection loop carries out the DC level controlled electric current that is shifted to described sample rate current, according to controlling electric current, the output current of output circuit is carried out to negative feedback.
Below by drawings and the specific embodiments, the utility model is described in further detail.
The utility model is realized a kind of current foldback circuit, as shown in Figure 2, comprises output circuit 11, and this current foldback circuit also comprises: overcurrent sample circuit 12, overcurrent protection loop 13; Wherein,
The first that Fig. 3 provides for the utility model is for the protection of the principle schematic of the current foldback circuit of the NMOS of output circuit, and this current foldback circuit comprises: the output circuit 11 consisting of a PMOS P1 and a NMOS N1, output voltage is V
o, output current is I
o; The overcurrent sample circuit 12 that a NMOS N1 is carried out to overcurrent sampling being formed by the first resistance R 1, the 2nd NMOS N2, the 3rd NMOS N3 and amplifier A1; The overcurrent protection loop 13 being formed by the second resistance R 2, the 2nd PMOS P2, the 3rd PMOS P3, the 4th NMOS N4, the 5th NMOS N5 and the first reference current source C1, the second reference current source C2; Wherein,
In output circuit 11, the source electrode of the one PMOS P1 connects feeder ear VCC, the positive input terminal of amplifier A1 in the drain electrode of drain electrode connection the one NMOS N1 of the one PMOS P1 and overcurrent sample circuit 12, the source ground GND of the one NMOS N1, the drain electrode of the 5th NMOS N5 in the grid of the 2nd NMOS N2 and overcurrent protection loop 13 in the grid connection overcurrent sample circuit 12 of a NMOS N1;
In overcurrent sample circuit 12, the source ground GND of the 2nd NMOS N2, the drain electrode of the 2nd NMOS N2 connects the negative input end of amplifier A1 and the source electrode of the 3rd NMOS N3, the output of amplifier A1 connects the grid of the 3rd NMOS N3, the drain electrode of the 3rd NMOS N3 connects the source electrode of the 3rd PMOS P3 in overcurrent protection loop 13, and connects feeder ear VCC by the first resistance R 1;
In overcurrent protection loop 13, the drain electrode of the 3rd PMOS P3 connects the grid of the 2nd PMOS P2 and one end of the second resistance R 2, the grid of the 3rd PMOS P3 connects the other end and the second reference current source C2 of the second resistance R 2, the source electrode of the 2nd PMOS P2 connects feeder ear VCC, the drain electrode of the 2nd PMOS P2 connects the drain and gate of the 4th NMOS N4 and the grid of the 5th NMOS N5, the source ground GND of the 4th NMOS N4, the drain electrode of the 5th NMOS N5 connects the grid of a NMOS N1 in output circuit 11, and connect feeder ear VCC by the first reference current source C1, the source ground GND of the 5th NMOS N5,
Here, the 3rd PMOS P3 and the 2nd PMOS P2 are configured to have identical parameters, i.e. grid-source voltage V of the 2nd PMOS P2
gs1equal grid-source voltage V of the 3rd PMOS P3
gs2;
The operation principle of this protective circuit is: as output current I
owhile there is overcurrent, the sample rate current I of overcurrent sample circuit 12
ocpincrease, drag down the source voltage of the 3rd PMOS P3, the control electric current of the drain electrode output of the 3rd PMOS P3 is corresponding being dragged down also, and the drain current I1 of the 2nd PMOS P2 increases, and the ducting capacity of the 5th NMOS N5 strengthens, the grid voltage V of a NMOS N1
gateby the 5th NMOS N5, dragged down output current I
oalso corresponding being dragged down.As can be seen from Figure 3, the 3rd PMOS P3, the second resistance R 2 and the second reference current source C2 form DC level shift circuit, make to exist following relational expression: I
ocp* R1+V
gs2=I
ref* R2+V
gs1, wherein, I
refthe electric current providing for the second reference current source C2, due to V
gs1=V
gs2so, I
ocp* R1=I
ref* R2, like this, I
ocponly with I
refrelevant, not with V
gs1or V
gs2relevant.
The second that Fig. 4 provides for the utility model is for the protection of the principle schematic of the current foldback circuit of the NMOS of output circuit, and this current foldback circuit comprises: the output circuit 11 consisting of a PMOS P1 and a NMOS N1, output voltage is V
o, output current is I
o; The overcurrent sample circuit 12 that a NMOS N1 is carried out to overcurrent sampling being formed by the first resistance R 1, the 2nd NMOS N2, the 3rd NMOS N3 and amplifier A1; The overcurrent protection loop 13 being formed by the 3rd resistance R 3, the 2nd PMOS P2, the 4th PMOS P4, the 4th NMOS N4, the 5th NMOS N5 and the first reference current source C1, the 3rd reference current source C3, the 4th reference current source C4; Wherein,
In output circuit 11, the source electrode of the one PMOS P1 connects feeder ear VCC, the positive input terminal of amplifier A1 in the drain electrode of drain electrode connection the one NMOS N1 of the one PMOS P1 and overcurrent sample circuit 12, the source ground GND of the one NMOS N1, the grid of the one NMOS N1 is connected with the grid of the 2nd NMOS N2 in overcurrent sample circuit 12, and receives the feedback signal of overcurrent protection loop 13;
In overcurrent sample circuit 12, the source ground GND of the 2nd NMOS N2, the drain electrode of the 2nd NMOS N2 connects the negative input end of amplifier A1 and the source electrode of the 3rd NMOS N3, the output of amplifier A1 connects the grid of the 3rd NMOS N3, the drain electrode of the 3rd NMOS N3 connects the source electrode of the 4th PMOS P4 in overcurrent protection loop 13, and connects feeder ear VCC by the first resistance R 1;
In overcurrent protection loop 13, the source electrode of PMOS P4 connects the drain electrode of the 3rd NMOS N3 in overcurrent sample circuit 12, the drain electrode of the 4th PMOS P4 is connected and is connected to one end and the 3rd reference current source C3 of the 3rd resistance R 3 with grid, the grid of the 2nd PMOS P2 connects the other end and the 4th reference current source C4 of the 3rd resistance R 3, the 3rd reference current source C3 ground connection GND, the 4th reference current source C4 connects feeder ear VCC, the source electrode of the 2nd PMOS P2 connects feeder ear VCC, the drain electrode of the 2nd PMOS P2 connects the drain and gate of the 4th NMOS N4 and the grid of the 5th NMOS N5, the source ground GND of the 4th NMOS N4, the drain electrode of the 5th NMOS N5 connects the grid of a NMOS N1 in output circuit 11, and connect feeder ear VCC by the first reference current source C1, the source ground GND of the 5th NMOS N5,
Here, the 4th PMOS P4 and the 2nd PMOS P2 are configured to have identical parameters, i.e. grid-source voltage V of the 2nd PMOS P2
gs1equal grid-source voltage V of the 4th PMOS P4
gs3;
The operation principle of this protective circuit is: as output current I
owhile there is overcurrent, the sample rate current I of overcurrent sample circuit 12
ocpincrease, drag down the source voltage of the 4th PMOS P4, the control electric current of the drain electrode output of the 4th PMOS P4 is corresponding being dragged down also, and the drain current I1 of the 2nd PMOS P2 increases, and the ducting capacity of the 5th NMOS N5 strengthens, the grid voltage V of a NMOS N1
gateby the 5th MMOS N5, dragged down output current I
oalso corresponding being dragged down.As can be seen from Figure 4, the 4th PMOS P4, the 3rd resistance R 3 and the 3rd reference current source C3 form DC level shift circuit.
Further, in the overcurrent protection electric current shown in Fig. 4, the source electrode of described the 2nd PMOS P2 also connects the 5th reference current source C5 over the ground.
The principle schematic of the current foldback circuit of the PMOS for the protection of output circuit that Fig. 5 provides for the utility model, this current foldback circuit comprises: the output circuit 11 consisting of the 5th PMOS P5 and the 6th NMOS N6, output voltage is V
o, output current is I
o; The overcurrent sample circuit 12 that the 5th PMOS P5 is carried out to overcurrent sampling being formed by the 4th resistance R 4, the 6th PMOS P6, the 7th PMOS P7 and amplifier A2; The overcurrent protection loop 13 being formed by the 5th resistance R 5, the 7th NMOS N7, the 8th NMOS N8, the 8th PMOS P8, the 9th PMOS P9 and the 6th reference current source C6, the 7th reference current source C7; Wherein,
In output circuit 11, the source electrode of the 5th PMOS P5 connects feeder ear VCC, the grid of the 5th PMOS P5 is connected with the grid of the 6th PMOS P6 in overcurrent sample circuit 12, and be connected with the drain electrode of the 9th PMOS P9 in overcurrent protection loop 13, the positive input terminal of amplifier A2 in the drain electrode of drain electrode connection the 6th NMOS N6 of the 5th PMOS P5 and overcurrent sample circuit 12, the source ground GND of the 6th NMOS N6;
In overcurrent sample circuit 12, the source electrode of the 6th PMOS P6 meets feeder ear VCC, the drain electrode of the 6th PMOS P6 connects the negative input end of amplifier A2 and the source electrode of the 7th PMOS P7, the output of amplifier A2 connects the grid of the 7th PMOS P7, the drain electrode of the 7th PMOS P7 connects the source electrode of the 7th NMOS N7 in overcurrent protection loop 13, and by the 4th resistance R 4 ground connection GND;
In overcurrent protection loop 13, the drain electrode of the 7th NMOS N7 connects one end of the 5th resistance R 5 and the grid of the 8th NMOS N8, the grid of the 7th NMOS N7 connects the other end and the 6th reference current source C6 of the 5th resistance R 5, the 6th reference current source C6 connects feeder ear VCC, the source ground GND of the 8th NMOS N8, the drain electrode of the 8th NMOS N8 connects the drain and gate of the 8th PMOS P8 and the grid of the 9th PMOS P9, the source electrode of the 8th PMOS P8 connects feeder ear VCC, the drain electrode of the 9th PMOS P9 connects the grid of the 5th PMOS P5 in output circuit 11, and by the 7th reference current source C7 ground connection GND, the source electrode of the 9th PMOS P9 connects feeder ear VCC,
Here, the 7th NMOS N7 and the 8th NMOS N8 are configured to have identical parameters, i.e. grid-source voltage V of the 7th NMOS N7
gs4equal grid-source voltage V of the 8th NMOS N8
gs5;
The operation principle of this protective circuit is: as output current I
owhile there is overcurrent, the sample rate current I of overcurrent sample circuit 12
ocpincrease, draw high the source voltage of the 7th NMOS N7, the control electric current of the drain electrode output of the 7th NMOS N7 is dragged down, and the source current I1 of the 8th NMOS N8 reduces, and the ducting capacity of the 9th PMOS P9 strengthens, the grid voltage V of the 5th PMOS P5
gateby the 9th PMOS P9, drawn high output current I
odragged down.As can be seen from Figure 5, the 7th NMOS N7, the 5th resistance R 5 and the 6th reference current source C6 form DC level shift circuit.
Fig. 6 is the sample rate current I of current foldback circuit shown in Fig. 1
ocpanalogous diagram, wherein, each curve is under different temperatures and/or the 2nd PMOS P2 has in the situation at different process angle, sample rate current I
ocpthe curve changing with feeder ear VCC, can find out sample rate current I
ocpexcursion be probably 400mA～700mA.
Fig. 7 is the sample rate current I of current foldback circuit shown in Fig. 3
ocpanalogous diagram, wherein, each curve is under different temperatures and/or the 2nd PMOS P2, the 3rd PMOS P3 have in the situation at different process angle, sample rate current I
ocpthe curve changing with feeder ear VCC, can find out, now, and sample rate current I
ocpexcursion be probably 345mA～385mA, improved to a great extent the accuracy of overcurrent protection.
Based on above-mentioned current foldback circuit, the utility model also provides a kind of over-current protection method, and as shown in Figure 8, the method comprises:
Step 101: overcurrent sample circuit carries out overcurrent sampling to output circuit;
Step 102: overcurrent protection loop carries out the DC level controlled electric current that is shifted to described sample rate current;
Step 103: overcurrent protection loop carries out negative feedback according to controlling electric current to the output current of output circuit.
Based on above-mentioned current foldback circuit, the utility model also provides a kind of integrated circuit, and this integrated circuit comprises above-mentioned current foldback circuit, comprises output circuit 11, overcurrent sample circuit 12, overcurrent protection loop 13; Wherein,
The first that Fig. 3 provides for the utility model is for the protection of the principle schematic of the current foldback circuit of the NMOS of output circuit, and this current foldback circuit comprises: the output circuit 11 consisting of a PMOS P1 and a NMOS N1, output voltage is V
o, output current is I
o; The overcurrent sample circuit 12 that a NMOS N1 is carried out to overcurrent sampling being formed by the first resistance R 1, the 2nd NMOS N2, the 3rd NMOS N3 and amplifier A1; The overcurrent protection loop 13 being formed by the second resistance R 2, the 2nd PMOS P2, the 3rd PMOS P3, the 4th NMOS N4, the 5th NMOS N5 and the first reference current source C1, the second reference current source C2; Wherein,
In output circuit 11, the source electrode of the one PMOS P1 connects feeder ear VCC, the positive input terminal of amplifier A1 in the drain electrode of drain electrode connection the one NMOS N1 of the one PMOS P1 and overcurrent sample circuit 12, the source ground GND of the one NMOS N1, the drain electrode of the 5th NMOS N5 in the grid of the 2nd NMOS N2 and overcurrent protection loop 13 in the grid connection overcurrent sample circuit 12 of a NMOS N1;
In overcurrent sample circuit 12, the source ground GND of the 2nd NMOS N2, the drain electrode of the 2nd NMOS N2 connects the negative input end of amplifier A1 and the source electrode of the 3rd NMOS N3, the output of amplifier A1 connects the grid of the 3rd NMOS N3, the drain electrode of the 3rd NMOS N3 connects the source electrode of the 3rd PMOS P3 in overcurrent protection loop 13, and connects feeder ear VCC by the first resistance R 1;
In overcurrent protection loop 13, the drain electrode of the 3rd PMOS P3 connects the grid of the 2nd PMOS P2 and one end of the second resistance R 2, the grid of the 3rd PMOS P3 connects the other end and the second reference current source C2 of the second resistance R 2, the source electrode of the 2nd PMOS P2 connects feeder ear VCC, the drain electrode of the 2nd PMOS P2 connects the drain and gate of the 4th NMOS N4 and the grid of the 5th NMOS N5, the source ground GND of the 4th NMOS N4, the drain electrode of the 5th NMOS N5 connects the grid of a NMOS N1 in output circuit 11, and connect feeder ear VCC by the first reference current source C1, the source ground GND of the 5th NMOS N5,
Here, the 3rd PMOS P3 and the 2nd PMOS P2 are configured to have identical parameters, i.e. grid-source voltage V of the 2nd PMOS P2
gs1equal grid-source voltage V of the 3rd PMOS P3
gs2;
The operation principle of this protective circuit is: as output current I
owhile there is overcurrent, the sample rate current I of overcurrent sample circuit 12
ocpincrease, drag down the source voltage of the 3rd PMOS P3, the control electric current of the drain electrode output of the 3rd PMOS P3 is corresponding being dragged down also, and the drain current I1 of the 2nd PMOS P2 increases, and the ducting capacity of the 5th NMOS N5 strengthens, the grid voltage V of a NMOS N1
gateby the 5th NMOS N5, dragged down output current I
oalso corresponding being dragged down.As can be seen from Figure 3, the 3rd PMOS P3, the second resistance R 2 and the second reference current source C2 form DC level shift circuit, make to exist following relational expression: I
ocp* R1+V
gs2=I
ref* R2+V
gs1, wherein, I
refthe electric current providing for the second reference current source C2, due to V
gs1=V
gs2so, I
ocp* R1=I
ref* R2, like this, I
ocponly with I
refrelevant, not with V
gs1or V
gs2relevant.
The second that Fig. 4 provides for the utility model is for the protection of the principle schematic of the current foldback circuit of the NMOS of output circuit, and this current foldback circuit comprises: the output circuit 11 consisting of a PMOS P1 and a NMOS N1, output voltage is V
o, output current is I
o; The overcurrent sample circuit 12 that a NMOS N1 is carried out to overcurrent sampling being formed by the first resistance R 1, the 2nd NMOS N2, the 3rd NMOS N3 and amplifier A1; The overcurrent protection loop 13 being formed by the 3rd resistance R 3, the 2nd PMOS P2, the 4th PMOS P4, the 4th NMOS N4, the 5th NMOS N5 and the first reference current source C1, the 3rd reference current source C3, the 4th reference current source C4; Wherein,
In output circuit 11, the source electrode of the one PMOS P1 connects feeder ear VCC, the positive input terminal of amplifier A1 in the drain electrode of drain electrode connection the one NMOS N1 of the one PMOS P1 and overcurrent sample circuit 12, the source ground GND of the one NMOS N1, the grid of the one NMOS N1 is connected with the grid of the 2nd NMOS N2 in overcurrent sample circuit 12, and receives the feedback signal of overcurrent protection loop 13;
In overcurrent sample circuit 12, the source ground GND of the 2nd NMOS N2, the drain electrode of the 2nd NMOS N2 connects the negative input end of amplifier A1 and the source electrode of the 3rd NMOS N3, the output of amplifier A1 connects the grid of the 3rd NMOS N3, the drain electrode of the 3rd NMOS N3 connects the source electrode of the 4th PMOS P4 in overcurrent protection loop 13, and connects feeder ear VCC by the first resistance R 1;
In overcurrent protection loop 13, the source electrode of PMOS P4 connects the drain electrode of the 3rd NMOS N3 in overcurrent sample circuit 12, the drain electrode of the 4th PMOS P4 is connected and is connected to one end and the 3rd reference current source C3 of the 3rd resistance R 3 with grid, the grid of the 2nd PMOS P2 connects the other end and the 4th reference current source C4 of the 3rd resistance R 3, the 3rd reference current source C3 ground connection GND, the 4th reference current source C4 connects feeder ear VCC, the source electrode of the 2nd PMOS P2 connects feeder ear VCC, the drain electrode of the 2nd PMOS P2 connects the drain and gate of the 4th NMOS N4 and the grid of the 5th NMOS N5, the source ground GND of the 4th NMOS N4, the drain electrode of the 5th NMOS N5 connects the grid of a NMOS N1 in output circuit 11, and connect feeder ear VCC by the first reference current source C1, the source ground GND of the 5th NMOS N5,
Here, the 4th PMOS P4 and the 2nd PMOS P2 are configured to have identical parameters, i.e. grid-source voltage V of the 2nd PMOS P2
gs1equal grid-source voltage V of the 4th PMOS P4
gs3;
The operation principle of this protective circuit is: as output current I
owhile there is overcurrent, the sample rate current I of overcurrent sample circuit 12
ocpincrease, drag down the source voltage of the 4th PMOS P4, the control electric current of the drain electrode output of the 4th PMOS P4 is corresponding being dragged down also, and the drain current I1 of the 2nd PMOS P2 increases, and the ducting capacity of the 5th NMOS N5 strengthens, the grid voltage V of a NMOS N1
gateby the 5th NMOS N5, dragged down output current I
oalso corresponding being dragged down.As can be seen from Figure 4, the 4th PMOS P4, the 3rd resistance R 3 and the 3rd reference current source C3 form DC level shift circuit.
Further, in the overcurrent protection electric current shown in Fig. 4, the source electrode of described the 2nd PMOS P2 also connects the 5th reference current source C5 over the ground.
The principle schematic of the current foldback circuit of the PMOS for the protection of output circuit that Fig. 5 provides for the utility model, this current foldback circuit comprises: the output circuit 11 consisting of the 5th PMOS P5 and the 6th NMOS N6, output voltage is V
o, output current is I
o; The overcurrent sample circuit 12 that the 5th PMOS P5 is carried out to overcurrent sampling being formed by the 4th resistance R 4, the 6th PMOS P6, the 7th PMOS P7 and amplifier A2; The overcurrent protection loop 13 being formed by the 5th resistance R 5, the 7th NMOS N7, the 8th NMOS N8, the 8th PMOS P8, the 9th PMOS P9 and the 6th reference current source C6, the 7th reference current source C7; Wherein,
In output circuit 11, the source electrode of the 5th PMOS P5 connects feeder ear VCC, the grid of the 5th PMOS P5 is connected with the grid of the 6th PMOS P6 in overcurrent sample circuit 12, and be connected with the drain electrode of the 9th PMOS P9 in overcurrent protection loop 13, the positive input terminal of amplifier A2 in the drain electrode of drain electrode connection the 6th NMOS N6 of the 5th PMOS P5 and overcurrent sample circuit 12, the source ground GND of the 6th NMOS N6;
In overcurrent sample circuit 12, the source electrode of the 6th PMOS P6 meets feeder ear VCC, the drain electrode of the 6th PMOS P6 connects the negative input end of amplifier A2 and the source electrode of the 7th PMOS P7, the output of amplifier A2 connects the grid of the 7th PMOS P7, the drain electrode of the 7th PMOS P7 connects the source electrode of the 7th NMOS N7 in overcurrent protection loop 13, and by the 4th resistance R 4 ground connection GND;
In overcurrent protection loop 13, the drain electrode of the 7th NMOS N7 connects one end of the 5th resistance R 5 and the grid of the 8th NMOS N8, the grid of the 7th NMOS N7 connects the other end and the 6th reference current source C6 of the 5th resistance R 5, the 6th reference current source C6 connects feeder ear VCC, the source ground GND of the 8th NMOS N8, the drain electrode of the 8th NMOS N8 connects the drain and gate of the 8th PMOS P8 and the grid of the 9th PMOS P9, the source electrode of the 8th PMOS P8 connects feeder ear VCC, the drain electrode of the 9th PMOS P9 connects the grid of the 5th PMOS P5 in output circuit 11, and by the 7th reference current source C7 ground connection GND, the source electrode of the 9th PMOS P9 connects feeder ear VCC,
Here, the 7th NMOS N7 and the 8th NMOS N8 are configured to have identical parameters, i.e. grid-source voltage V of the 7th NMOS N7
gs4equal grid-source voltage V of the 8th NMOS N8
gs5;
The operation principle of this protective circuit is: as output current I
owhile there is overcurrent, the sample rate current I of overcurrent sample circuit 12
ocpincrease, draw high the source voltage of the 7th NMOS N7, the control electric current of the drain electrode output of the 7th NMOS N7 is dragged down, and the source current I1 of the 8th NMOS N8 reduces, and the ducting capacity of the 9th PMOS P9 strengthens, the grid voltage V of the 5th PMOS P5
gateby the 9th PMOS P9, drawn high output current I
odragged down.As can be seen from Figure 5, the 7th NMOS N7, the 5th resistance R 5 and the 6th reference current source C6 form DC level shift circuit.
The above, be only preferred embodiment of the present utility model, is not intended to limit protection range of the present utility model.
Claims (14)
1. a current foldback circuit, comprises output circuit, it is characterized in that, described current foldback circuit also comprises:
Output circuit is carried out to overcurrent sampling, and sample rate current is transferred to the overcurrent sample circuit of overcurrent protection loop;
Described sample rate current is carried out to the DC level controlled electric current that is shifted, according to controlling electric current, the output current of output circuit is carried out to degenerative overcurrent protection loop.
2. current foldback circuit according to claim 1, is characterized in that, described output circuit comprises: a PMOS and a NMOS;
Described overcurrent sample circuit comprises: the first resistance, the 2nd NMOS, the 3rd NMOS and amplifier;
Described overcurrent protection loop comprises: the second resistance, the 2nd PMOS, the 3rd PMOS, the 4th NMOS, the 5th NMOS and the first reference current source, the second reference current source.
3. current foldback circuit according to claim 2, is characterized in that,
In described output circuit, the source electrode of the one PMOS connects feeder ear, the positive input terminal of amplifier in the drain electrode of drain electrode connection the one NMOS of the one PMOS and overcurrent sample circuit, the source ground of the one NMOS, the drain electrode of the 5th NMOS in the grid of the 2nd NMOS and overcurrent protection loop in the grid connection overcurrent sample circuit of a NMOS;
In described overcurrent sample circuit, the source ground of the 2nd NMOS, the drain electrode of the 2nd NMOS connects the negative input end of amplifier and the source electrode of the 3rd NMOS, the output of amplifier connects the grid of the 3rd NMOS, the drain electrode of the 3rd NMOS connects the source electrode of the 3rd PMOS in overcurrent protection loop, and connects feeder ear by the first resistance;
In described overcurrent protection loop; the drain electrode of the 3rd PMOS connects the grid of the 2nd PMOS and one end of the second resistance; the grid of the 3rd PMOS connects the other end and second reference current source of the second resistance; the source electrode of the 2nd PMOS connects feeder ear; the drain electrode of the 2nd PMOS connects the drain and gate of the 4th NMOS and the grid of the 5th NMOS; the source ground of the 4th NMOS; the drain electrode of the 5th NMOS connects the grid of a NMOS in output circuit; and connect feeder ear, the source ground of the 5th NMOS by the first reference current source.
4. current foldback circuit according to claim 1, is characterized in that, described output circuit comprises: a PMOS and a NMOS;
Described overcurrent sample circuit comprises: the first resistance, the 2nd NMOS, the 3rd NMOS and amplifier;
Described overcurrent protection loop comprises: the 3rd resistance, the 2nd PMOS, the 4th PMOS, the 4th NMOS, the 5th NMOS and the first reference current source, the 3rd reference current source, the 4th reference current source.
5. current foldback circuit according to claim 4, it is characterized in that, in described overcurrent protection loop, the source electrode of PMOS connects the drain electrode of the 3rd NMOS in overcurrent sample circuit, the drain electrode of the 4th PMOS is connected and is connected to one end and the 3rd reference current source of the 3rd resistance with grid, the grid of the 2nd PMOS connects the other end and the 4th reference current source of the 3rd resistance, the 3rd reference current source ground connection, the 4th reference current source connects feeder ear, the source electrode of the 2nd PMOS connects feeder ear, the drain electrode of the 2nd PMOS connects the drain and gate of the 4th NMOS and the grid of the 5th NMOS, the source ground of the 4th NMOS, the drain electrode of the 5th NMOS connects output circuit, and connect feeder ear by the first reference current source, the source ground of the 5th NMOS.
6. current foldback circuit according to claim 1, is characterized in that, described output circuit comprises: the 5th PMOS and the 6th NMOS;
Described overcurrent sample circuit comprises: the 4th resistance, the 6th PMOS, the 7th PMOS and amplifier;
Described overcurrent protection loop comprises: the 5th resistance, the 7th NMOS, the 8th NMOS, the 8th PMOS, the 9th PMOS and the 6th reference current source, the 7th reference current source.
7. current foldback circuit according to claim 6, is characterized in that,
In described output circuit, the source electrode of the 5th PMOS connects feeder ear, the grid of the 5th PMOS is connected with the grid of the 6th PMOS in overcurrent sample circuit, and be connected with the drain electrode of the 9th PMOS in overcurrent protection loop, the positive input terminal of amplifier in the drain electrode of drain electrode connection the 6th NMOS of the 5th PMOS and overcurrent sample circuit, the source ground of the 6th NMOS;
In described overcurrent sample circuit, the source electrode of the 6th PMOS connects feeder ear, the drain electrode of the 6th PMOS connects the negative input end of amplifier and the source electrode of the 7th PMOS, the output of amplifier connects the grid of the 7th PMOS, the drain electrode of the 7th PMOS connects the source electrode of the 7th NMOS in overcurrent protection loop, and by the 4th grounding through resistance;
In described overcurrent protection loop; the drain electrode of the 7th NMOS connects one end of the 5th resistance and the grid of the 8th NMOS; the grid of the 7th NMOS connects the other end and the 6th reference current source of the 5th resistance; the 6th reference current source connects feeder ear; the source ground of the 8th NMOS; the drain electrode of the 8th NMOS connects the drain and gate of the 8th PMOS and the grid of the 9th PMOS; the source electrode of the 8th PMOS connects feeder ear; the drain electrode of the 9th PMOS connects the grid of the 5th PMOS in output circuit; and by the 7th reference current source ground connection, the source electrode of the 9th PMOS connects feeder ear.
8. an integrated circuit, is characterized in that, this integrated circuit comprises current foldback circuit, described current foldback circuit comprise output circuit and
Output circuit is carried out to overcurrent sampling, and sample rate current is transferred to the overcurrent sample circuit of overcurrent protection loop;
Described sample rate current is carried out to the DC level controlled electric current that is shifted, according to controlling electric current, the output current of output circuit is carried out to degenerative overcurrent protection loop.
9. integrated circuit according to claim 8, is characterized in that, described output circuit comprises: a PMOS and a NMOS;
Described overcurrent sample circuit comprises: the first resistance, the 2nd NMOS, the 3rd NMOS and amplifier;
Described overcurrent protection loop comprises: the second resistance, the 2nd PMOS, the 3rd PMOS, the 4th NMOS, the 5th NMOS and the first reference current source, the second reference current source.
10. integrated circuit according to claim 9, is characterized in that,
In described output circuit, the source electrode of the one PMOS connects feeder ear, the positive input terminal of amplifier in the drain electrode of drain electrode connection the one NMOS of the one PMOS and overcurrent sample circuit, the source ground of the one NMOS, the drain electrode of the 5th NMOS in the grid of the 2nd NMOS and overcurrent protection loop in the grid connection overcurrent sample circuit of a NMOS;
In described overcurrent sample circuit, the source ground of the 2nd NMOS, the drain electrode of the 2nd NMOS connects the negative input end of amplifier and the source electrode of the 3rd NMOS, the output of amplifier connects the grid of the 3rd NMOS, the drain electrode of the 3rd NMOS connects the source electrode of the 3rd PMOS in overcurrent protection loop, and connects feeder ear by the first resistance;
In described overcurrent protection loop; the drain electrode of the 3rd PMOS connects the grid of the 2nd PMOS and one end of the second resistance; the grid of the 3rd PMOS connects the other end and second reference current source of the second resistance; the source electrode of the 2nd PMOS connects feeder ear; the drain electrode of the 2nd PMOS connects the drain and gate of the 4th NMOS and the grid of the 5th NMOS; the source ground of the 4th NMOS; the drain electrode of the 5th NMOS connects the grid of a NMOS in output circuit; and connect feeder ear, the source ground of the 5th NMOS by the first reference current source.
11. integrated circuits according to claim 8, is characterized in that, described output circuit comprises: a PMOS and a NMOS;
Described overcurrent sample circuit comprises: the first resistance, the 2nd NMOS, the 3rd NMOS and amplifier;
Described overcurrent protection loop comprises: the 3rd resistance, the 2nd PMOS, the 4th PMOS, the 4th NMOS, the 5th NMOS and the first reference current source, the 3rd reference current source, the 4th reference current source.
12. integrated circuits according to claim 11, it is characterized in that, in described overcurrent protection loop, the source electrode of PMOS connects the drain electrode of the 3rd NMOS in overcurrent sample circuit, the drain electrode of the 4th PMOS is connected and is connected to one end and the 3rd reference current source of the 3rd resistance with grid, the grid of the 2nd PMOS connects the other end and the 4th reference current source of the 3rd resistance, the 3rd reference current source ground connection, the 4th reference current source connects feeder ear, the source electrode of the 2nd PMOS connects feeder ear, the drain electrode of the 2nd PMOS connects the drain and gate of the 4th NMOS and the grid of the 5th NMOS, the source ground of the 4th NMOS, the drain electrode of the 5th NMOS connects output circuit, and connect feeder ear by the first reference current source, the source ground of the 5th NMOS.
13. integrated circuits according to claim 8, is characterized in that, described output circuit comprises: the 5th PMOS and the 6th NMOS;
Described overcurrent sample circuit comprises: the 4th resistance, the 6th PMOS, the 7th PMOS and amplifier;
Described overcurrent protection loop comprises: the 5th resistance, the 7th NMOS, the 8th NMOS, the 8th PMOS, the 9th PMOS and the 6th reference current source, the 7th reference current source.
14. integrated circuits according to claim 13, is characterized in that,
In described output circuit, the source electrode of the 5th PMOS connects feeder ear, the grid of the 5th PMOS is connected with the grid of the 6th PMOS in overcurrent sample circuit, and be connected with the drain electrode of the 9th PMOS in overcurrent protection loop, the positive input terminal of amplifier in the drain electrode of drain electrode connection the 6th NMOS of the 5th PMOS and overcurrent sample circuit, the source ground of the 6th NMOS;
In described overcurrent sample circuit, the source electrode of the 6th PMOS connects feeder ear, the drain electrode of the 6th PMOS connects the negative input end of amplifier and the source electrode of the 7th PMOS, the output of amplifier connects the grid of the 7th PMOS, the drain electrode of the 7th PMOS connects the source electrode of the 7th NMOS in overcurrent protection loop, and by the 4th grounding through resistance;
In described overcurrent protection loop; the drain electrode of the 7th NMOS connects one end of the 5th resistance and the grid of the 8th NMOS; the grid of the 7th NMOS connects the other end and the 6th reference current source of the 5th resistance; the 6th reference current source connects feeder ear; the source ground of the 8th NMOS; the drain electrode of the 8th NMOS connects the drain and gate of the 8th PMOS and the grid of the 9th PMOS; the source electrode of the 8th PMOS connects feeder ear; the drain electrode of the 9th PMOS connects the grid of the 5th PMOS in output circuit; and by the 7th reference current source ground connection, the source electrode of the 9th PMOS connects feeder ear.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320381816.4U CN203415966U (en) | 2013-06-24 | 2013-06-24 | Overcurrent protection circuit and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320381816.4U CN203415966U (en) | 2013-06-24 | 2013-06-24 | Overcurrent protection circuit and integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203415966U true CN203415966U (en) | 2014-01-29 |
Family
ID=49978825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320381816.4U Expired - Fee Related CN203415966U (en) | 2013-06-24 | 2013-06-24 | Overcurrent protection circuit and integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203415966U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242278A (en) * | 2013-06-24 | 2014-12-24 | 快捷半导体(苏州)有限公司 | Overcurrent protection method and circuit and integrated circuit |
| CN104638896A (en) * | 2015-02-13 | 2015-05-20 | 矽恩微电子(厦门)有限公司 | Current clamping circuit based on BCD process |
-
2013
- 2013-06-24 CN CN201320381816.4U patent/CN203415966U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242278A (en) * | 2013-06-24 | 2014-12-24 | 快捷半导体(苏州)有限公司 | Overcurrent protection method and circuit and integrated circuit |
| CN104638896A (en) * | 2015-02-13 | 2015-05-20 | 矽恩微电子(厦门)有限公司 | Current clamping circuit based on BCD process |
| CN104638896B (en) * | 2015-02-13 | 2017-06-27 | 矽恩微电子(厦门)有限公司 | Current-clamp circuitry based on BCD techniques |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103575964B (en) | A kind of over-current detection circuit of power switch pipe and method | |
| CN105446404B (en) | Low differential voltage linear voltage stabilizer circuit, chip and electronic equipment | |
| CN202794314U (en) | Over-current detection circuit of power switching tube | |
| CN207069897U (en) | Start-up circuit and inverse-excitation type switch power-supply | |
| CN102364851A (en) | Circuit converting high-voltage power supply into low-voltage power supply for enabling zero switching current of chip | |
| CN105403753A (en) | Auxiliary sampling circuit of primary inductance peak current of switching power supply | |
| CN104393760B (en) | The positive negative output low voltage difference with short-circuit protection function adjusts circuit | |
| CN203415966U (en) | Overcurrent protection circuit and integrated circuit | |
| CN104242278A (en) | Overcurrent protection method and circuit and integrated circuit | |
| CN203339958U (en) | Peak current detection-based line voltage compensation circuit | |
| CN202978247U (en) | Overcurrent protection circuit | |
| CN101153880A (en) | Negative voltage detector | |
| CN101763134B (en) | Parallel voltage stabilizing circuit | |
| CN105807831A (en) | Linear voltage regulator and linear voltage stabilizing system preventing overshoot | |
| CN104242277A (en) | Device for carrying out current-limiting protection on load or output | |
| CN103592991B (en) | Circuit protected by Power Limitation type for ambipolar linear voltage regulator | |
| CN203405751U (en) | Novel voltage stabilizer circuit structure | |
| CN202331254U (en) | Current-voltage conversion circuit with over-current protection circuit module | |
| CN105375892B (en) | A kind of energy-efficient current amplifier | |
| CN110445377B (en) | Conduction time generating circuit with zero static power consumption | |
| CN102447466B (en) | IO (Input/Output) circuit for accurate pull-down current | |
| CN104300952A (en) | Self-adaptive drive circuit for environment-friendly switching mode power supply chip | |
| CN102158213B (en) | DC solid-state relay | |
| CN203800836U (en) | CS short circuit protection circuit for switch power supply | |
| CN203813431U (en) | Current limiting protection circuit based on MOS tube grid voltage control |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140129 Termination date: 20150624 |
|
| EXPY | Termination of patent right or utility model |