CN203414760U

CN203414760U - Data acquisition system

Info

Publication number: CN203414760U
Application number: CN201320384996.1U
Authority: CN
Inventors: 张丽萍
Original assignee: SHANGHAI TD TELECOM TECHNOLOGY DEVELOPMENT Co Ltd
Current assignee: SHANGHAI TD TELECOM TECHNOLOGY DEVELOPMENT Co Ltd
Priority date: 2013-06-28
Filing date: 2013-06-28
Publication date: 2014-01-29
Anticipated expiration: 2023-06-28

Abstract

The utility model provides a data acquisition system. The data acquisition system comprises an FPGA chip, and an external clock module, a downloading configuration circuit and an A/D conversion module which are respectively in coupling connection with the FPGA chip. The registered trademark of the FPGA chip is Stratix IIFPGA, the A/D conversion module adopts an ADuC824, the external clock module adopts a clock chip MPC92432, and the downloading configuration circuit adopts a serial configuration device series EPCS16. The utility model discloses the FPGA-based high-speed data acquisition system which performs analog-to-digital conversion on signals by using an AD device, performs ADC logic control by using the FPGA to design an internal module, and realizes a data buffering function.

Description

Data acquisition system (DAS)

Technical field

The utility model relates to a kind of data acquisition system (DAS), refers in particular to a kind of data acquisition system (DAS) based on FPGA.

Background technology

In the every profession and trade of commercial production and scientific and technical research, usually need various data to gather, as the collection of the information such as liquid level, temperature, pressure, frequency.In some fields such as image processing, transient signal detection, software radios, require especially the data acquisition technology of high-speed, high precision, high real-time.

The task of data acquisition system (DAS), processes and converts to by the simulating signal of pick-up transducers output the digital signal of calculating function identification exactly, by computing machine, is calculated accordingly and is processed to meet different needs, draws required data.The quality of data acquisition system (DAS) performance is to be decided by its precision and speed.Guaranteeing, under the prerequisite of precision, should to use high as far as possible sample rate, could meet like this Real-time Collection, processing in real time and control in real time the requirement to speed.

In traditional data acquisition system (DAS), the control of A/D and the unloading of data are all to complete by CPU or MCU.In this manner, the result of A/D conversion is read in, and then this process in the storer outside sheet that dumps at least needs 4 machine cycles.Even for the single-chip microcomputer of ARM core, use the crystal oscillator of 33MHz, its highest unloading data speed also only reaches 8Mbyte/s.In high-speed data acquistion system, this mode takies too many cpu resource on the one hand, also can not meet in addition the rate request of high speed acquisition far away.

Utility model content

The purpose of this utility model is to provide a kind of data acquisition system (DAS) that overcomes above-mentioned technical matters.

For solving the problems of the technologies described above, the utility model data acquisition system (DAS), comprises fpga chip and the external clock module, download configuration circuit and the A/D modular converter that are of coupled connections with described fpga chip respectively.

Preferably, described fpga chip adopts

Preferably, described A/D modular converter adopts ADuC824.

Preferably, described external clock module adopts clock chip MPC92432.

Preferably, described download configuration circuit adopts series arrangement device series EPCS16.

The utility model data acquisition system (DAS) has realized a kind of high-speed data acquistion system based on FPGA, and this system utilizes AD device to carry out analog to digital conversion to signal, utilizes FPGA design internal module to carry out the logic control of ADC and realize data buffer storage function.

Accompanying drawing explanation

Fig. 1 is the utility model data acquisition system (DAS) block diagram.

Embodiment

Below in conjunction with accompanying drawing, the utility model data acquisition system (DAS) is described in further detail.

As shown in Figure 1, the utility model data acquisition system (DAS), comprises fpga chip and the external clock module, download configuration circuit and the A/D modular converter that are of coupled connections with fpga chip respectively.Fpga chip adopts

a/D modular converter adopts ADuC824.External clock module adopts clock chip MPC92432.Download configuration circuit adopts series arrangement device series EPCS16.

1, fpga chip

Adopt

obtain higher performance and better signal integrity.No matter be in individual devices, to carry out ASIC prototyping, or towards batch production, can both from use StratixIIFPGA, benefit, comprise High Performance DSP module and on-chip memory, High Speed I/O pin and external memory interface, low-cost high-density logic is transplanted approach.StratixIIFPGA adopts the low k insulating process of the 90nm technology of TSMC to produce, and equivalent logic unit (LE), up to 180K, in-line memory reaches 9Mbits.StratixII not only has high performance and density, also for device general power, is optimized.The redundancy of Altera uniqueness has improved output greatly, has reduced device cost.

2, A/D modular converter

Adopt the new high-performance monolithic ADuC824 releasing of AD company, it is integrated high-resolution A/D converter in inside, is one of single-chip microcomputer that in current sheet, resource is the abundantest.It is integrated in one the affluent resources such as 8051 kernels, 24+16 sigma-delta A/D of two-way, 12 D/A, FLASH, WDT, μ P supervisory circuit, temperature sensor, SPI and I2C bus interface, and volume is little, low in energy consumption, be suitable for very much the fields such as all kinds of intelligent instruments, intelligent sensor, transmitter and portable instrument.

Flash/EE data-carrier store, 256 byte ram in slice in Flash/EE program storage, 640 chunks in ADuC824 high resolving power, 8k chunk, there are PLL, 3 16 bit timings/counters in 32kHz external crystal-controlled oscillation and sheet; Include 12 interrupt sources, temperature sensor in 2 priority, sheet; 12 Voltage-output DAC; Two excitation constant current sources; Time-interval counter; 2 lines (I2C can be compatible) and SPI serial i/O; House dog watchdog timer (WDT); Power supply monitor (PSM)

3, external clock module

The high performance clock synthetic source that the utility model adopts clock chip MPC92432 ，Ta Shi Freescale company to produce, inner PLL produces high frequency output signal on the basis of low frequency reference signal.

The MPC92432 high frequency compositor of Freescale is an I2C programmable clock, and it can be produced by single clock chip the clock frequency of 21.25～1360MHz, thereby gives developer enough dirigibilities.The limiting frequency performance of cost economy is provided in the situation that keeping low-power consumption.The manufacturing process of MPC92432 is Germanium carbon (SiGe:C) technology of Freescale, to reach splendid cost performance and low-power consumption.

4, download configuration circuit

Select the series arrangement device series EPCS16 of ALTERA company.FPGA downloads code by JTAG and moves in slice, thin piece, and code leaves in RAM, and power-off post code disappear.Therefore, FPGA needs nonvolatile memory to be used for depositing code, after powering on, code is read then to move to FPGA from configuring chip at every turn.The config memory EPCS16 that selects the AS pattern of ALTERA company series arrangement device series matching, cost compare is low, and is easy to configuration, is the configuration device of least cost in FPGA (Field Programmable Gate Array) industrial circle.The advanced features such as small outline integrated circuit (SOIC) encapsulation that are included in system programmable (ISP), flash memory access interface, saving veneer space that EPCS16 has, make series arrangement device become CycloneII and the perfection of CycloneFPGA series of products under the applied environment of large capacity and Price Sensitive supplements.The serial series arrangement device EPCS16 of Altera also provides the solution of a kind of low cost, miniaturization for StratixII family device.

Simulating signal is first sent into FPGA after simulating signal being converted into digital signal by analog to digital converter, FPGA writes data FIFO storage chip again, FPGA sends after read command FIFO, after FPGA can read data from FIFO, deliver to reading interface, follow-up MCU can obtain gathered data.

Below the preferred embodiment of the utility model having been created illustrates, but the utility model is not limited to embodiment, those of ordinary skill in the art also can make all modification being equal to or replacement under the prerequisite without prejudice to the utility model creative spirit, and the modification that these are equal to or replacement are all included in the application's scope.

Claims

1. data acquisition system (DAS), is characterized in that, comprises fpga chip and the external clock module, download configuration circuit and the A/D modular converter that are of coupled connections with described fpga chip respectively.

2. data acquisition system (DAS) according to claim 1, is characterized in that, described fpga chip adopts

3. data acquisition system (DAS) according to claim 1, is characterized in that, described A/D modular converter adopts ADuC824.

4. data acquisition system (DAS) according to claim 1, is characterized in that, described external clock module adopts clock chip MPC92432.

5. data acquisition system (DAS) according to claim 1, is characterized in that, described download configuration circuit adopts series arrangement device series EPCS16.