CN203386746U - Punch-through type transient voltage suppressor - Google Patents
Punch-through type transient voltage suppressor Download PDFInfo
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- CN203386746U CN203386746U CN201320412260.0U CN201320412260U CN203386746U CN 203386746 U CN203386746 U CN 203386746U CN 201320412260 U CN201320412260 U CN 201320412260U CN 203386746 U CN203386746 U CN 203386746U
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- Prior art keywords
- punch
- transient voltage
- voltage suppressor
- substrate
- injection region
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Abstract
The utility model discloses a punch-through type transient voltage suppressor. The punch-through type transient voltage suppressor comprises a P substrate. The upper surface of the P substrate is provided with a layer of oxide layer, wherein the oxide layer is divided into an anode region and a cathode region from the middle portion. The upper surface of the P substrate is provided with an N well having a second conduction type in the anode region, wherein a first N+ active injection region having the second conduction type is arranged in the N well. The upper surface of the P substrate is provided with a P well having a first conduction type in the cathode region, wherein a second N+ active injection region having the second conduction type is arranged in the P well. An anode metal connecting piece is arranged on the first N+ active injection region. A cathode metal connecting piece is arranged on the second N+ active injection region. The punch-through type transient voltage suppressor of the utility model has an appropriate trigger voltage and good forward and reverse clamping capacity, can be used to effectively protect forward and reverse electrostatic pulses, has advantages of good ESD protection effect, small consumed chip area, low cost, easy implementation, and good application prospects.
Description
Technical field
The utility model relates to a kind of punch Transient Voltage Suppressor, belongs to the outer integrated circuit electrostatic defending technical field of sheet.
Background technology
Along with the high speed development of electronics industry, fashional consumption electronics and portable product are more and more.And these electronic products often carry a lot of interfaces, need with other electronic equipment communication, the useful life that seriously is related to whole electronic equipment for the reliability design relation of these interfaces, ESD(Electrostatic Discharge wherein, static discharge) problem is the vital problem to these interface reliability designs.
Current, along with electronic device tends to miniaturization day by day, high density and multifunction, be easy to be subject to the impact of static discharge, we know, static is at every moment ubiquitous, in the sixties, along with the appearance to the highstrung MOS device of static, electrostatic discharge problem also arises at the historic moment, to the seventies electrostatic discharge problem more and more come seriously, 80 ~ nineties, along with the density of integrated circuit is increasing, the thickness of its silicon dioxide film of one side more and more thinner (micron changes to nanometer), cause the ability to bear of integrated circuit static more and more lower, therefore, electrostatic breakdown has become the stealthy killer of electronics industry, caused people's extensive concern.
At present, the solution for the ESD protection question of integrated circuit has following two kinds usually:
(1) in the I/O(Input/ of IC interior Output, I/O) a mouthful electrostatic discharge protection component of interior making;
(2) at the PCB(Printed of integrated circuit Circuit Board, printed circuit board (PCB)) go up and place the reliability that Transient Voltage Suppressor increases integrated circuit;
Due to the area constraints that is subject to the IC interior chip, increase electrostatic discharge protection component at IC interior extremely inconvenient, and protective capacities is also very limited, so, the practicality of solution one is little, therefore, in order to increase the antistatic capacity of integrated circuit, placing Transient Voltage Suppressor on the pcb board of integrated circuit is very important solution, but, the voltage clamping ability of current Transient Voltage Suppressor on the market is not high, forward and back clamping ability differ larger, protection forward that can not be fully effective and the electrostatic pulse of negative sense, the ESD protection effect is not good, and production technology is special, expensive, be difficult to meet the demand of current ten hundreds of electronic product.
The utility model content
The technical problem that the utility model solves is that to overcome the voltage clamping ability of existing Transient Voltage Suppressor on the market not high, forward and back clamping ability differ larger, protection forward that can not be fully effective and the electrostatic pulse of negative sense, the ESD protection effect is not good, and production technology is special, expensive problem.
In order to solve the problems of the technologies described above, the technical scheme that the utility model adopts is:
A kind of punch Transient Voltage Suppressor, comprise the P substrate, it is characterized in that:
Described P substrate top surface is provided with layer of oxide layer, and described oxide layer is divided into anode region and cathode zone from middle part;
Described P substrate top surface is positioned at anode region and is provided with a N trap with second conduction type, is provided with an active injection region of N+ with second conduction type in described N trap;
Described P substrate top surface is positioned at cathode zone and is provided with a P trap with first conduction type, is provided with the 2nd an active injection region of N+ with second conduction type in described P trap;
A described active injection region of N+ is provided with the anode metal brace that is connected to the device anode;
Described the 2nd active injection region of N+ is provided with the cathodic metal brace that is connected to device cathodes.
The aforesaid punch Transient Voltage Suppressor of wearing, it is characterized in that: the doping content of described P substrate is 1 * 10
15~ 1 * 10
16atom/cm
3.
Aforesaid punch Transient Voltage Suppressor is characterized in that: the distance between the 2nd active injection region of N+ of described P trap and the section that sets within it is between 0.5 μ m ~ 1.5 μ m.
The aforesaid punch Transient Voltage Suppressor of wearing is characterized in that: the thickness of described oxide layer is 0.8 μ m ~ 1.2 μ m, and the degree of depth that oxide layer is embedded into the P substrate interior is 0.1 μ m ~ 0.3 μ m.
The aforesaid punch Transient Voltage Suppressor of wearing is characterized in that: the doping content of described N trap is 7 * 10
18~ 1 * 10
19atom/cm
3between.
The aforesaid punch Transient Voltage Suppressor of wearing, it is characterized in that: the doping content of described P trap is 9 * 10
17~ 5 * 10
19atom/cm
3between.
Aforesaid punch Transient Voltage Suppressor is characterized in that: a described active injection region of N+ is identical with the doping content of the 2nd active injection region of N+, all 9 * 10
19~ 1 * 10
21atom/cm
3between.
Preferably, by the parallel connection of two or more punch Transient Voltage Suppressor, be about to each punch Transient Voltage Suppressor anode metal brace and be connected and each punch Transient Voltage Suppressor cathodic metal brace is connected.
The beneficial effects of the utility model are: punch Transient Voltage Suppressor of the present utility model, there is suitable trigger voltage, and great forward and back clamping ability, can effectively protect the electrostatic pulse of forward and negative sense, the ESD protection effect is good, and manufacture method is simple, the consumption chip area is little, with low cost, easily realize, have a good application prospect.
The accompanying drawing explanation
Fig. 1 is the structural representation of punch Transient Voltage Suppressor of the present utility model.
Fig. 2 is the equivalent circuit diagram of punch Transient Voltage Suppressor of the present utility model.
Fig. 3 is the schematic diagram of the manufacture first step of punch Transient Voltage Suppressor of the present utility model.
Fig. 4 is the schematic diagram of the manufacture second step of punch Transient Voltage Suppressor of the present utility model.
Fig. 5 is the schematic diagram of manufacture the 3rd step of punch Transient Voltage Suppressor of the present utility model.
Fig. 6 is the schematic diagram of manufacture the 4th step of punch Transient Voltage Suppressor of the present utility model.
Fig. 7 is the current lead-through performance diagram of punch Transient Voltage Suppressor of the present utility model.
Fig. 8 is the equivalent circuit diagram of a plurality of punch Transient Voltage Suppressors of parallel connection of the present utility model.
Fig. 9 is the current lead-through performance diagram of 12 punch Transient Voltage Suppressors in parallel of the present utility model.
Embodiment
Below in conjunction with Figure of description, the utility model is further described.
As shown in Figure 1, a kind of punch Transient Voltage Suppressor, comprise P substrate 01, and the doping content of P substrate 01 is 1 * 10
15~ 1 * 10
16atom/cm
3between, described P substrate 01 upper surface is provided with layer of oxide layer 02, and oxide layer 02 is divided into anode region and cathode zone from middle part, and the thickness of oxide layer 02 is 0.8 μ m ~ 1.2 μ m, and the degree of depth that oxide layer 02 is embedded into P substrate 01 inside is 0.1 μ m ~ 0.3 μ m;
Described P substrate 01 upper surface is positioned at anode region and is provided with a N trap 03 with second conduction type, and the doping content of N trap 03 is 7 * 10
18~ 1 * 10
19atom/cm
3between, be provided with an active injection region 05 of N+ with second conduction type in described N trap 03;
Described P substrate 01 upper surface is positioned at cathode zone and is provided with a P trap 04 with first conduction type, and the doping content of P trap 04 is 9 * 10
17~ 5 * 10
19atom/cm
3between, be provided with the 2nd an active injection region 06 of N+ with second conduction type in described P trap 04;
A described active injection region 05 of N+ is identical with the doping content of the 2nd active injection region 06 of N+, all 9 * 10
19~ 1 * 10
21atom/cm
3between.
A described active injection region 05 of N+ is provided with the anode metal brace 07 that is connected to the device anode;
Described the 2nd active injection region 06 of N+ is provided with the cathodic metal brace 08 that is connected to device cathodes.
As shown in Figure 2, the equivalent circuit diagram of punch Transient Voltage Suppressor of the present utility model, its operation principle is as follows,
When ESD(static occurs for the anode metal brace 07 of punch Transient Voltage Suppressor of the present utility model) during pulse, because an active injection region 05 of N+ and N trap 03 have the second identical conduction type, they are equal to wire and connect, on the PN junction that make the voltage produced by esd pulse mainly the drop to N trap 03 with second conduction type and the P substrate 01 with first conduction type forms, and it is partially anti-that it is occurred, because the doping content of P substrate 01 is low, its preferred value is 1 * 10
15~ 1 * 10
16atom/cm
3between concentration, so this P substrate 01 is very easy to exhaust, make before PN junction punctures, this depletion layer just extends and has in the P trap 04 of the first conduction type, very near due to the distance design of the 2nd active injection region 06 of N+ in the edge of P trap 04 and P trap 04 again, its preferred value is between 0.5 μ m ~ 1.5 μ m, so P trap 04 is also depleted before PN junction punctures, before puncturing, PN junction just make the active injection region 06 of N trap 03 and the 2nd N+ that horizontal break-through occurs, laterally the punch through voltage value is generally between 3V ~ 5.5V, break-through occurs after, along with constantly rising fast of electric current, device is triggered fully, produce back stagnant phenomenon, the trigger voltage scope is 5V ~ 7V,
When ESD(static occurs for the cathodic metal brace 08 of punch Transient Voltage Suppressor of the present utility model) during pulse, the voltage produced by esd pulse mainly drops on the PN junction that the P trap 04 with first conduction type and the 2nd active injection region 06 of N+ with second conduction type form, it is occurred partially anti-, similar to the forward conduction mechanism of this Transient Voltage Suppressor, very near due to the distance design of the 2nd active injection region 06 of N+ in the edge of P trap 04 and P trap 04, and the doping content of P substrate 01 is low, so P trap 04 and P substrate 01 are all depleted before PN junction punctures, horizontal break-through occurs in the 2nd active injection region 06 of N+ and N trap 03, because an active injection region 05 of N+ and N trap 03 have the second identical conduction type, being equal to wire on electricity connects, laterally punch through also is equal to an active injection region 05 of N+ and the 2nd N+ horizontal break-through in active injection region 06, laterally the punch through voltage value is generally 3V ~ 4.5V, break-through occurs after, along with constantly rising fast of electric current, device is triggered fully, produce back stagnant phenomenon, the scope of trigger voltage is 5V ~ 6.5V.
By the above-mentioned course of work, as shown in Figure 7, be punch Transient Voltage Suppressor of the present utility model, measured current lead-through performance curve.
As shown in Fig. 3-Fig. 6, be the manufacturing process of punch Transient Voltage Suppressor of the present utility model,
(1) oxide layer 02 of making at the upper surface of P substrate 01, and divide anode region and the cathode zone of stipulating out device, as shown in Figure 3;
(2) anode region on P substrate 01 is manufactured with a N trap 03 with second conduction type, as shown in Figure 4;
(3) cathode zone on P substrate 01 is manufactured with a P trap 04 with first conduction type, as shown in Figure 5;
(4) have an active injection region 05 of N+ of the second conduction type in the interior making one of the N trap 03 with first conduction type, having the P trap of the first conduction type, (4 interior making one have the 2nd active injection region 06 of N+ of the second conduction type, as shown in Figure 6;
Make the anode metal brace 07 that is connected to the device anode on an active injection region 05 of N+, make the cathodic metal brace 08 that is connected to device cathodes, the punch Transient Voltage Suppressor completed as shown in Figure 1 on the 2nd active injection region 06 of N+.
In actual applications, a punch Transient Voltage Suppressor often is not enough to the ESD protection for high reliability, two or more punch Transient Voltage Suppressors are connected in parallel, carry out the current lead-through ability of enhance device, specific practice is: each punch Transient Voltage Suppressor anode metal brace 07 is connected and each punch Transient Voltage Suppressor cathodic metal brace 08 is connected, as shown in Figure 8, wherein number in parallel is arbitrarily to equivalent circuit diagram.
In the present embodiment, concrete device number in parallel is 12, the punch Transient Voltage Suppressor of 12 parallel connections, the ESD protective capacities is multiplied, be embodied in ESD current lead-through ability and be multiplied, the horizontal punch through voltage value of the punch Transient Voltage Suppressor of described 12 parallel connections is generally 3V ~ 4.5V; The scope of trigger voltage is 5V ~ 6.5V, and measured current lead-through performance curve as shown in Figure 9, contrasts and Fig. 7, and the current lead-through ability obviously strengthens.
Above demonstration and described basic principle of the present utility model, principal character and advantage.The technical staff of the industry should understand; the utility model is not restricted to the described embodiments; that in above-described embodiment and specification, describes just illustrates principle of the present utility model; under the prerequisite that does not break away from the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall in claimed the utility model scope.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (9)
1. a punch Transient Voltage Suppressor, comprise P substrate (01), it is characterized in that:
Described P substrate (01) upper surface is provided with layer of oxide layer (02), and described oxide layer (02) is divided into anode region and cathode zone from middle part;
Described P substrate (01) upper surface is positioned at anode region and is provided with a N trap (03) with second conduction type, is provided with an active injection region of N+ (05) with second conduction type in described N trap (03);
Described P substrate (01) upper surface is positioned at cathode zone and is provided with a P trap (04) with first conduction type, is provided with the 2nd an active injection region of N+ (06) with second conduction type in described P trap (04);
A described active injection region of N+ (05) is provided with the anode metal brace (07) that is connected to the device anode;
Described the 2nd active injection region of N+ (06) is provided with the cathodic metal brace (08) that is connected to device cathodes.
2. punch Transient Voltage Suppressor according to claim 1, it is characterized in that: the doping content of described P substrate (01) is 1 * 10
15~ 1 * 10
16atom/cm
3.
3. punch Transient Voltage Suppressor according to claim 1 is characterized in that: the distance between the 2nd active injection region of N+ (06) of described P trap (04) and the section that sets within it is between 0.5 μ m ~ 1.5 μ m.
4. punch Transient Voltage Suppressor according to claim 1, it is characterized in that: the thickness of described oxide layer (02) is 0.8 μ m ~ 1.2 μ m, and oxide layer (02) to be embedded into the inner degree of depth of P substrate (01) be 0.1 μ m ~ 0.3 μ m.
5. punch Transient Voltage Suppressor according to claim 1, it is characterized in that: the doping content of described N trap (03) is 7 * 10
18~ 1 * 10
19atom/cm
3between.
6. punch Transient Voltage Suppressor according to claim 1, it is characterized in that: the doping content of described P trap (04) is 9 * 10
17~ 5 * 10
19atom/cm
3between.
7. punch Transient Voltage Suppressor according to claim 1, it is characterized in that: a described active injection region of N+ (05) is identical with the doping content of the 2nd active injection region of N+ (06), all 9 * 10
19~ 1 * 10
21atom/cm
3between.
8. according to the described punch Transient Voltage Suppressor of any one in claim 1-7, it is characterized in that: by the parallel connection of two or more punch Transient Voltage Suppressor.
9. punch Transient Voltage Suppressor according to claim 8, it is characterized in that: the parallel connection of two or more punch Transient Voltage Suppressor is each punch Transient Voltage Suppressor anode metal brace (07) is connected and each punch Transient Voltage Suppressor cathodic metal brace (08) is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320412260.0U CN203386746U (en) | 2013-07-11 | 2013-07-11 | Punch-through type transient voltage suppressor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320412260.0U CN203386746U (en) | 2013-07-11 | 2013-07-11 | Punch-through type transient voltage suppressor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203386746U true CN203386746U (en) | 2014-01-08 |
Family
ID=49875201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320412260.0U Expired - Fee Related CN203386746U (en) | 2013-07-11 | 2013-07-11 | Punch-through type transient voltage suppressor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203386746U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103354229A (en) * | 2013-07-11 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | Breaking-through transient voltage inhibitor |
-
2013
- 2013-07-11 CN CN201320412260.0U patent/CN203386746U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103354229A (en) * | 2013-07-11 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | Breaking-through transient voltage inhibitor |
| CN103354229B (en) * | 2013-07-11 | 2016-04-27 | 江苏艾伦摩尔微电子科技有限公司 | A kind of Breaking-through transient voltage inhibitor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140108 Termination date: 20150711 |
|
| EXPY | Termination of patent right or utility model |