CN203386743U - 一种带有螺旋电感的封装基板 - Google Patents

一种带有螺旋电感的封装基板 Download PDF

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CN203386743U
CN203386743U CN201320256007.0U CN201320256007U CN203386743U CN 203386743 U CN203386743 U CN 203386743U CN 201320256007 U CN201320256007 U CN 201320256007U CN 203386743 U CN203386743 U CN 203386743U
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electric capacity
conductive layer
wire
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杨国山
陈溅冰
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Xiamen Leixunke Microelectronics Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/4809Loop shape
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    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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Abstract

本实用新型公开了一种带有螺旋电感的封装基板, 包括一个介质层以及第一、第二两个导电层,第一、第二两个导电层分别设置于介质层的两面,第一导电层上设置有由螺旋导电线构成的螺旋电感、芯片焊接导电区、SMD焊接导电区,第一导电层和第二导电层设置有过孔连接,所述的螺旋电感包括导线一及导线二,导线二旋绕形成螺旋部,导线一的首端形成螺旋电感的第一端,导线一末端与导线二的首端通过一根或多根键合线连接,导线二的末端形成螺旋电感第二端,仅需要一个介质层和两个导电层,就可以实现微带螺旋电感的制作,并满足封装基板的布线功能和与集成电路器件与外部的电气连接,有效降低封装基板成本。

Description

一种带有螺旋电感的封装基板
技术领域
本实用新型涉及设计集成电路封装领域,尤其涉及一种带有螺旋电感的封装基板。
背景技术
随着应用小型化的需求越来越高,集成电路器件的小型化要求也越来越高。封装基板可以采用多层线路布线,具有高密度互联等优点,现已被广泛应用于芯片封装,如BGA(Ball Grid Array)以及LGA(Land Grid Array)等。在射频应用领域中,电感经常用于阻抗匹配或者射频扼流,通过在封装基板上采用矩形或圆形的螺旋微带线制作电感,可以减少基板的占用面积,从而减少封装尺寸。然而,现有方法制作的微带螺旋电感,至少需要两个导电层,以满足电感与外部电路的连接。封装基板既需要满足集成电路器件的内部线路走线,又必须提供与器件外部进行电气互联的导电线,因此,封装基板必须具有至少两个导电层。如果在两层导电层的封装基板上制作微带螺旋电感,无法满足应用的要求。为了制作微带螺旋电感,必须增加一个导电层和一个介质层,提高了封装成本。具体以一个实施例如图1-图3所示,包括第一导电层A,第二导电层B,第三导电层C以及两个介质层D、E,其螺旋电感包括导线1F、导线2G、第一端、第二端。导线2第一端和导线1被导线2的螺旋部隔断,无法在第一导电层实现电气连接。为了实现导线1和导线2的连接,导线1和导线2第一端必须经由过孔和第三导电层的内层导线连接,由此增加了一个导电层和一个介质层,增加了封装基板的成本。
实用新型内容
本实用新型的目的在于解决现有技术的问题,提供一种带有螺旋电感的封装基板,其采用单个介质层的封装基板制作螺旋电感,降低封装成本。
为达成上述目的,本实用新型采用如下技术方案:
一种带有螺旋电感的封装基板, 包括一个介质层以及第一、第二两个导电层,第一、第二两个导电层分别设置于介质层的两面,第一导电层上设置有由螺旋导电线构成的螺旋电感、芯片焊接导电区、SMD焊接导电区,第一导电层和第二导电层设置有过孔连接。
所述的螺旋电感包括导线一及导线二,导线二旋绕形成螺旋部,导线一的首端形成螺旋电感的第一端,导线一末端与导线二的首端通过一根或多根键合线连接,导线二的末端形成螺旋电感第二端。
封装基板上设置有输出阻抗匹配电路,包括键合线、SMD电容一、SMD电容二、SMD电容三、SMD电容四、微带线;键合线的第一端连接芯片焊盘,键合线的第二端连接SMD电容一、二 ,SMD电容一、二的另一端通过过孔到第二导电层,键合线的第二端还连接一段微带线,微带线的另一端分别连接SMD电容三和SMD电容四的第一端,SMD电容三的第二端通过过孔连接到第二导电层的接地金属,SMD电容四的第二端通过过孔连接到第二导电层上的引脚。
所述的芯片焊接导电区设置有多个金属化过孔,金属化过孔连接第一导电层和第二导电层。
采用上述技术方案,本实用新型仅需要一个介质层和两个导电层,就可以实现微带螺旋电感的制作,并满足封装基板的布线功能和与集成电路器件与外部的电气连接,有效降低封装基板成本。
附图说明
此处所说明的附图用来提供对本实用新型的进一步理解,构成本实用新型的一部分,本实用新型的示意性实施例及其说明用于解释本实用新型,并不构成对本实用新型的不当限定。在附图中:
图1为现有技术结构示意图一;
图2为现有技术结构示意图二;
图3为现有技术结构示意图三;
图4为本实用新型 结构示意图一;
图5为本实用新型 结构示意图二;
图6为本实用新型 结构示意图三;
图7为本实用新型 螺旋电感结构示意图一;
图8为本实用新型 螺旋电感结构示意图二;
图9为本实用新型 输出阻抗匹配电路等效电路图。
具体实施方式
为了使本实用新型所要解决的技术问题、技术方案及有益效果更加清楚、明白,以下结合附图和实施例,对本实用新型进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本实用新型,并不用于限定本实用新型。
如图4-图9所示,本实用新型所述的一种带有螺旋电感的封装基板,包括:一个介质层1以及第一、第二两个导电层2、3,第一、第二两个导电层2、3分别设置于介质层1的两面,第一导电层上设置有由螺旋导电线构成的螺旋电感21、芯片焊接导电区22、SMD焊接导电区23,第一导电层和第二导电层设置有过孔4连接。
如图4-6,集成电路器件使用的封装基板,具有第一第二两个导电层2、3和一个介质层1,第一第二导电层间设置有过孔4,用于实现第一第二两个导电层的电气连接。第一导电层上设置有线路,通过键合线5或其他连接方式与芯片6连接。第一导电层上还可以焊接SMD无源器件7。第二导电层设置引脚8,用于集成电路与其他电路的电气连接。
如图7、图8,所述的螺旋电感21包括导线一211及导线二212,导线二212旋绕形成螺旋部,导线一211的首端形成螺旋电感21的第一端,导线一211末端与导线二212的首端通过一根或多根键合线5连接,导线二212的末端形成螺旋电感第二端。
如图5、图9,封装基板上设置有输出阻抗匹配电路,包括键合线51、SMD电容一711、SMD电容二712、SMD电容三713、SMD电容四714、微带线52;键合线51的第一端连接芯片焊盘,键合线51的第二端连接SMD电容一711、SMD电容一712,SMD电容一711、SMD电容二712的另一端通过过孔到第二导电层,键合线51的第二端还连接一段微带线52,微带线52的另一端分别连接SMD电容三713和SMD电容四714的第一端,SMD电容三713的第二端通过过孔4连接到第二导电层的接地金属9,SMD电容四714的第二端通过过孔4连接到第二导电层上的引脚8。
所述的芯片焊接导电区22设置有多个金属化过孔41,金属化过孔41连接第一导电层和第二导电层。本实用新型用键合线5将导线一和导线二连接,仅需要一个介质层和第一第二两个导电层,有效节约成本。
上述说明示出并描述了本实用新型的优选实施例,如前所述,应当理解本实用新型并非局限于本文所披露的形式,不应看作是对其他实施例的排除,而可用于各种其他组合、修改和环境,并能够在本文所述实用新型构想范围内,通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本实用新型的精神和范围,则都应在本实用新型所附权利要求的保护范围内。

Claims (4)

1.一种带有螺旋电感的封装基板, 其特征在于:包括:
一个介质层(1)以及第一、第二两个导电层(2)、(3),第一、第二两个导电层(2)、(3)分别设置于介质层(1)的两面,第一导电层上设置有由螺旋导电线构成的螺旋电感(21)、芯片焊接导电区(22)、SMD焊接导电区(23),第一导电层和第二导电层设置有过孔(4)连接。
2.如权利要求1所述的一种带有螺旋电感的封装基板, 其特征在于:所述的螺旋电感(21)包括导线一(211)及导线二(212),导线二(212)旋绕形成螺旋部,导线一(211)的首端形成螺旋电感(21)的第一端,导线一(211)末端与导线二(212)的首端通过一根或多根键合线(5)连接,导线二(212)的末端形成螺旋电感第二端。
3.如权利要求1所述的一种带有螺旋电感的封装基板,其特征在于:封装基板上设置有输出阻抗匹配电路,包括键合线(51)、SMD电容一(711)、SMD电容二(712)、SMD电容三(713)、SMD电容四(714)、微带线(52);键合线(51)的第一端连接芯片焊盘,键合线(51)的第二端连接SMD电容一(711)、SMD电容一(712),SMD电容一(711)、SMD电容二(712)的另一端通过过孔到第二导电层,键合线(51)的第二端还连接一段微带线(52),微带线(52)的另一端分别连接SMD电容三(713)和SMD电容四(714)的第一端,SMD电容三(713)的第二端通过过孔(4)连接到第二导电层的接地金属(9),SMD电容四(714)的第二端通过过孔(4)连接到第二导电层上的引脚(8)。
4.如权利要求1所述的一种带有螺旋电感的封装基板,其特征在于:所述的芯片焊接导电区(22)设置有多个金属化过孔(41),金属化过孔(41)连接第一导电层和第二导电层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114695339A (zh) * 2020-12-25 2022-07-01 京东方科技集团股份有限公司 集成有无源器件的基板及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114695339A (zh) * 2020-12-25 2022-07-01 京东方科技集团股份有限公司 集成有无源器件的基板及其制备方法

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Address after: 361000 N404 room, Weiye building, pioneer zone, torch hi tech Zone, Huli District, Xiamen, Fujian, Xiamen

Patentee after: Xiamen Leixunke Microelectronics Co.,Ltd.

Address before: 361000 N404 room, Weiye building, pioneer zone, torch hi tech Zone, Huli District, Xiamen, Fujian, Xiamen

Patentee before: XIAMEN CREOTECH ELECTRONIC TECHNOLOGY Co.,Ltd.

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Granted publication date: 20140108