CN203233401U - PCI-based IRIG-B decoding card - Google Patents
PCI-based IRIG-B decoding card Download PDFInfo
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- CN203233401U CN203233401U CN 201320258681 CN201320258681U CN203233401U CN 203233401 U CN203233401 U CN 203233401U CN 201320258681 CN201320258681 CN 201320258681 CN 201320258681 U CN201320258681 U CN 201320258681U CN 203233401 U CN203233401 U CN 203233401U
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- sign indicating
- indicating number
- number decoding
- pci
- decoding unit
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Abstract
The utility model discloses a PCI-based IRIG-B decoding card which comprises a PCI card body, a direct-current B code decoding unit, and/or a direct-current difference B code decoding unit, and/or an alternating current B code decoding unit, wherein the last three units are disposed on the PCI card body. The PCI-based IRIG-B decoding card also comprises a time information processing unit, a second signal time-delay processing unit, and a millisecond counter, which are all disposed on the PCI card body. According to the utility model, accurate second pulses can be obtained by the second signal time-delay processing unit. The accurate second pulses are read by a computer via a PCI bus and capable of making the time accuracy of a whole computer system be improved greatly, which facilitates the cooperative processing of the system and meets expected requirements.
Description
Technical field
The utility model relates to a kind of decoding card, relates in particular to a kind of IRIG B sign indicating number decoding card based on PCI.
Background technology
PCI is the abbreviation of Peripheral Component Interconnect (being the Peripheral Component Interconnect standard), and it is the most widely used interface in the present PC, all has this slot on nearly all mainboard product.IRIG B then is serial timing code (being Inter Range Instrumentation Group), has six kinds of forms.
In the prior art, computer is by having the IRIG B sign indicating number decoding card acquisition time information of PCI slot interface.But, because the temporal information precision of obtaining not high (can only reach a millisecond magnitude) often can't accomplish the end in view.
The utility model content
The utility model provides a kind of IRIG B sign indicating number decoding card based on PCI at the drawback of prior art.
IRIG B sign indicating number decoding card based on PCI described in the utility model, be used for the general B coded signal that timing equipment sends is decoded, and the system time when being read to obtain by pci bus by computer, comprise the pci card body, also comprise the DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or the alternating-current B sign indicating number decoding unit that are arranged on the pci card body;
And be arranged at temporal information processing unit on the pci card body, second signal lag processing unit and millisecond counter;
Wherein, the input of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit connects timing equipment respectively and receives the general B coded signal that timing equipment is exported;
The output of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit is the connect hours information process unit respectively, and exports the temporal information that calculates to the temporal information processing unit; Described temporal information processing unit then gathers the temporal information that receives the back and reads by pci bus for computer;
The output of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit also connects a second signal lag processing unit respectively, and to information second that second, the output of signal lag processing unit calculated; The signal lag processing unit carried out exporting millisecond counter to behind the compensation of delay to information second that receives in described second;
The input of described millisecond counter is connected with a second signal lag processing unit, and carries out zero clearing and enabling counting according to information second that receives; Described computer then reads the count value of described millisecond counter as the millisecond value of reaction event information.
In the IRIG B sign indicating number decoding card based on PCI described in the utility model, described DC B sign indicating number decoding unit comprises signal input interface, egress buffer circuit and the B sign indicating number decoding single-chip microcomputer that is linked in sequence.
In the IRIG B sign indicating number decoding card based on PCI described in the utility model, described direct current difference B sign indicating number decoding unit comprises signal input interface, signal receiving circuit and the B sign indicating number decoding single-chip microcomputer that is linked in sequence.
In the IRIG B sign indicating number decoding card based on PCI described in the utility model, described alternating-current B sign indicating number decoding unit comprises that the signal input interface, automatic gain amplifier, the B sign indicating number that are linked in sequence go back primary circuit and B sign indicating number decoding single-chip microcomputer.
In the IRIG B sign indicating number decoding card based on PCI described in the utility model, the signal lag processing unit comprised delay compensating chain and the constant temperature high stability crystal oscillator that is arranged on the pci card body in described second, the signal output access delay compensating circuit of described constant temperature high stability crystal oscillator.
In the IRIG B sign indicating number decoding card based on PCI described in the utility model, by a second signal lag processing unit is set, thereby can obtain accurate pulse per second (PPS), this accurate pulse per second (PPS) is read by pci bus by computer, just make that also the time precision of whole computer system improves greatly, make things convenient for the associated treatment of system, satisfied the requirement of expection.
Description of drawings
Fig. 1 is the structure principle chart that blocks based on the IRIG B sign indicating number decoding of PCI described in the utility model.
Embodiment
Below in conjunction with accompanying drawing the utility model is described in further detail, can implements according to this with reference to the specification literal to make those skilled in the art.
As shown in Figure 1, IRIG B sign indicating number decoding card based on PCI described in the utility model, be used for the general B coded signal that timing equipment sends is decoded, and the system time when being read to obtain by pci bus by computer, this IRIG B sign indicating number decoding card comprises the pci card body, also comprises the DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or the alternating-current B sign indicating number decoding unit that are arranged on the pci card body.Above-mentioned DC B sign indicating number decoding unit, direct current difference B sign indicating number decoding unit and alternating-current B sign indicating number decoding unit can arrange according to actual needs, both can arrange simultaneously, also can only arrange one of them or wherein two.
IRIG B sign indicating number decoding card based on PCI described in the utility model also comprises temporal information processing unit, second signal lag processing unit and the millisecond counter that is arranged on the pci card body.
Wherein, the input of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit connects timing equipment respectively and receives the general B coded signal that timing equipment is exported;
The output of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit is the connect hours information process unit respectively, and exports the temporal information that calculates to the temporal information processing unit; Described temporal information processing unit then gathers the temporal information that receives the back and reads by pci bus for computer;
The output of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit also connects a second signal lag processing unit respectively, and to information second that second, the output of signal lag processing unit calculated; The signal lag processing unit carried out exporting millisecond counter to behind the compensation of delay to information second that receives in described second;
The input of described millisecond counter is connected with a second signal lag processing unit, and carries out zero clearing and enabling counting according to information second that receives; Described computer then reads the count value of described millisecond counter as the millisecond value of reaction event information.
Particularly, as shown in Figure 1, described DC B sign indicating number decoding unit comprises signal input interface, egress buffer circuit and the B sign indicating number decoding single-chip microcomputer that is linked in sequence.The general B coded signal of described timing equipment output is delivered to the egress buffer circuit after inserting through signal input interface, further calculates temporal information and second information by B sign indicating number decoding single-chip microcomputer again, and the form of described temporal information be " day: time: branch: second ".
Described direct current difference B sign indicating number decoding unit comprises signal input interface, signal receiving circuit and the B sign indicating number decoding single-chip microcomputer that is linked in sequence.The general B coded signal of described timing equipment output is delivered to signal receiving circuit after inserting through signal input interface, further calculates temporal information and second information by B sign indicating number decoding single-chip microcomputer again, and the form of described temporal information be " day: time: branch: second ".
Described alternating-current B sign indicating number decoding unit comprises that the signal input interface, automatic gain amplifier, the B sign indicating number that are linked in sequence go back primary circuit and B sign indicating number decoding single-chip microcomputer.The general B coded signal of described timing equipment output is delivered to the B sign indicating number again and is gone back primary circuit after inserting through signal input interface after automatic gain amplifier amplifies the square-wave signal that becomes 1000 hertz; Described B sign indicating number is gone back the square-wave signal that primary circuit sends here automatic gain amplifier with 1000 hertz frequency and is carried out analog-to-digital conversion, thereby restore the DC B coded signal, further calculate temporal information and second information by B sign indicating number decoding single-chip microcomputer again, the form of described temporal information be " day: time: branch: second ".
Described temporal information processing unit gathers the temporal information that above-mentioned DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit calculate, make it to become a temporal information, read by pci bus for computer.
Calculating second information for aforementioned DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit, is to handle by compensation of delay to obtain more accurate pulse per second (PPS) in the utility model.Particularly, as shown in Figure 1, the signal lag processing unit comprised delay compensating chain and the constant temperature high stability crystal oscillator that is arranged on the pci card body in described second, the signal output access delay compensating circuit of described constant temperature high stability crystal oscillator.After the above-mentioned second information via delay process, for DC B sign indicating number and direct current difference B sign indicating number signal second, pulse precision can reach ± 100 nanoseconds, and for alternating-current B sign indicating number signal second, pulse precision can reach ± 5 microseconds.Start millisecond counter in the time of described pulse signal zero clearing millisecond counter, this count value is latched in the buffer under the effect of PCI control signal, reads for pci bus.And computer program reads the millisecond counter value as the millisecond value of obtaining event information by pci bus acquisition time information the time, and the time precision of whole system has just reached ± 10 microseconds like this.
The utility model is by arranging second signal lag processing unit and a millisecond counter, make B sign indicating number temporal information precision that computer obtains by current approximately ± 1 millisecond bring up to ± 10 microseconds, the B sign indicating number that has improved computer greatly obtains precision, makes things convenient for the associated treatment of system.
Although embodiment of the present utility model is open as above, but it is not restricted to listed utilization in specification and the execution mode, it can be applied to the various fields of the present utility model that are fit to fully, for those skilled in the art, can easily realize other modification, therefore do not deviating under the universal that claim and equivalency range limit, the utility model is not limited to specific details and illustrates here and the legend of describing.
Claims (5)
1. the IRIG B sign indicating number decoding based on PCI blocks, be used for the general B coded signal that timing equipment sends is decoded, and the system time when being read to obtain by pci bus by computer, comprise the pci card body, it is characterized in that, also comprise the DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or the alternating-current B sign indicating number decoding unit that are arranged on the pci card body;
And be arranged at temporal information processing unit on the pci card body, second signal lag processing unit and millisecond counter;
Wherein, the input of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit connects timing equipment respectively and receives the general B coded signal that timing equipment is exported;
The output of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit is the connect hours information process unit respectively, and exports the temporal information that calculates to the temporal information processing unit; Described temporal information processing unit then gathers the temporal information that receives the back and reads by pci bus for computer;
The output of described DC B sign indicating number decoding unit and/or direct current difference B sign indicating number decoding unit and/or alternating-current B sign indicating number decoding unit also connects a second signal lag processing unit respectively, and to information second that second, the output of signal lag processing unit calculated; The signal lag processing unit carried out exporting millisecond counter to behind the compensation of delay to information second that receives in described second;
The input of described millisecond counter is connected with a second signal lag processing unit, and carries out zero clearing and enabling counting according to information second that receives; Described computer then reads the count value of described millisecond counter as the millisecond value of reaction event information.
2. the IRIG B sign indicating number decoding card based on PCI as claimed in claim 1 is characterized in that, described DC B sign indicating number decoding unit comprises signal input interface, egress buffer circuit and the B sign indicating number decoding single-chip microcomputer that is linked in sequence.
3. the IRIG B sign indicating number decoding card based on PCI as claimed in claim 1 is characterized in that, described direct current difference B sign indicating number decoding unit comprises signal input interface, signal receiving circuit and the B sign indicating number decoding single-chip microcomputer that is linked in sequence.
4. the IRIG B sign indicating number decoding card based on PCI as claimed in claim 1 is characterized in that, described alternating-current B sign indicating number decoding unit comprises that the signal input interface, automatic gain amplifier, the B sign indicating number that are linked in sequence go back primary circuit and B sign indicating number decoding single-chip microcomputer.
5. the IRIG B sign indicating number decoding based on PCI as claimed in claim 1 blocks, it is characterized in that, the signal lag processing unit comprised delay compensating chain and the constant temperature high stability crystal oscillator that is arranged on the pci card body in described second, the signal output access delay compensating circuit of described constant temperature high stability crystal oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320258681 CN203233401U (en) | 2013-05-14 | 2013-05-14 | PCI-based IRIG-B decoding card |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320258681 CN203233401U (en) | 2013-05-14 | 2013-05-14 | PCI-based IRIG-B decoding card |
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| CN203233401U true CN203233401U (en) | 2013-10-09 |
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| CN 201320258681 Expired - Fee Related CN203233401U (en) | 2013-05-14 | 2013-05-14 | PCI-based IRIG-B decoding card |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708169A (en) * | 2016-12-31 | 2017-05-24 | 中国舰船研究设计中心 | Multicomputer system time synchronization method based on VPX framework and device |
| CN111913523A (en) * | 2020-06-19 | 2020-11-10 | 国网河南省电力公司焦作供电公司 | Double-buffer IRIG-B code generation method |
-
2013
- 2013-05-14 CN CN 201320258681 patent/CN203233401U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708169A (en) * | 2016-12-31 | 2017-05-24 | 中国舰船研究设计中心 | Multicomputer system time synchronization method based on VPX framework and device |
| CN111913523A (en) * | 2020-06-19 | 2020-11-10 | 国网河南省电力公司焦作供电公司 | Double-buffer IRIG-B code generation method |
| CN111913523B (en) * | 2020-06-19 | 2024-05-07 | 国网河南省电力公司焦作供电公司 | Dual-buffer IRIG-B code generation method |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131009 Termination date: 20160514 |