CN203217600U - Base band control chip and ultrahigh frequency radio frequency read-write apparatus - Google Patents
Base band control chip and ultrahigh frequency radio frequency read-write apparatus Download PDFInfo
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- CN203217600U CN203217600U CN 201320225712 CN201320225712U CN203217600U CN 203217600 U CN203217600 U CN 203217600U CN 201320225712 CN201320225712 CN 201320225712 CN 201320225712 U CN201320225712 U CN 201320225712U CN 203217600 U CN203217600 U CN 203217600U
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Abstract
The utility model discloses a base band control chip and an ultrahigh frequency radio frequency read-write apparatus. The base band control chip comprises a microprocessor, a reset and clock control unit, a storage apparatus control unit, a timer, an external interruption control unit, an AD conversion unit, a DA conversion unit, an ISO18000-6B protocol processing unit, a bus control unit, a bus conversion unit, a high-speed communication interface, a low-speed communication interface, a debugging interface and an on-chip bus. The ISO18000-6B protocol processing unit is used for processing an electronic label of the ISO18000-6B protocol standard. According to the utility model, the ultrahigh frequency radio frequency identification device (UHF RFID) read-write apparatus with the advantages of high integrated level, low power consumption, high versatility, low cost, and high performance can be realized conveniently.
Description
Technical field
The utility model relates to the base band signal process technical field, relates in particular to a kind of base band control chip and super high frequency radio frequency read-write equipment.
Background technology
Along with the fast development of integrated circuit with the electronic tag size reduces and the reduction of cost, the application of REID has obtained develop rapidly.The read-write scope of radio frequency read-write equipment depends primarily on frequency of operation, read-write equipment emissive power, label susceptibility and data transmission rate etc.For the near field radio frequency read-write equipment, because its short reading/writing distance and lower data transmission rate is subjected to certain restriction, and the super high frequency radio frequency read-write equipment has the advantage of longer reading/writing distance and higher data transfer rate.
Passive type ultrahigh frequency identification UHF RFID device general work is in 860-928MHz (there is different standards in all parts of the world district) frequency range.Adopt the backscattered modulation pattern, work in the far-field radiation district, have reading/writing distance far away (can reach 3-10 rice), non-visual, characteristics such as read or write speed is fast, label is passive, make it be widely used in fields such as warehouse logistics, parking lot management, asset management, valuables be antitheft.Passive type super high frequency radio frequency identification RFID device is made of read-write equipment, electronic tag and background application device, and wherein read-write equipment and electronic tag are the keys of whole device.Electronic tag internal passive and adopt the power supply of passive far end radio frequency, internal resource is limited, can't finish complicated signal to handle, and therefore, the design performance of read-write equipment is the key point of whole device performance in the RFID device.
The ultrahigh frequency read-write equipment structurally is made of two parts, and a part is radio-frequency module and baseband module, and as shown in Figure 1, wherein radio-frequency module mainly is to be made of quadrature transmitter, receiver, mainly finishes the modulation of high-frequency signal, sends and receives.Baseband module mainly is made of digital signal processing unit and protocol processing unit two parts, digital signal processing unit mainly is responsible for following sampling, the filtering to baseband signal and is produced the required baseband signal of different modulating mode, and protocol processing unit mainly is responsible for the coding/decoding, generation check code of the data of sending out or data are carried out verification, data are carried out framing or unpacked and to the control of radio-frequency head etc.The effect of radio-frequency module comprises specifically: the modulate emission signal produces baseband signal with baseband module and moves tremendously high frequency, and is sent to electronic tag by antenna; The emission high-frequency signal, the active electron label, and provide energy for electronic tag; Receive also demodulation from the signal of electronic tag, and carry out simple filtering.The main task of base band control module comprises: communicates with application apparatus software, and the action command that sends of actuating unit software; The signal that receives is carried out synchronously, carry out the filtering moulding to sending signal; According to the agreement regulation data that receive are handled; The communication process of control and label; Realize the anti-collision algorithm of many labels; Radio-frequency module is controlled.In order to make the integrated master of super high frequency radio frequency read-write equipment higher, described base band control device also can comprise the application program unit of curing, sees Fig. 2 for details.It is big that present existing ultrahigh frequency RFID read-write equipment exists the read-write equipment volume, is not suitable for miniaturized application, cost height, peripheral circuit complexity, problem such as performance is limited, and power consumption is big.
The utility model content
In view of this, the utility model provides a kind of base band control chip and super high frequency radio frequency read-write equipment, solves the technical matters that above background technology is partly mentioned.
A kind of base band control chip, comprise microprocessor, reset and clock control cell, memory storage control module, timer, external interrupt control module, AD converting unit, DA converting unit, ISO18000-6B protocol processing unit, bus control unit, bus conversion unit, high-speed communication interface, low-speed communication interface, debugging interface and bus on chip that described ISO18000-6B protocol processing unit is for the treatment of the electronic tag of ISO18000-6B consensus standard;
Described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, described high speed system bus AHB is connected by bridge with low speed peripheral bus APB, and each described high speed system bus AHB and each described low speed peripheral bus APB are equipped with address decoder and bus arbiter;
Described microprocessor, described debugging interface, described memory storage control module, described high-speed communication interface, ISO18000-6B protocol processing unit, bus control unit and described bus conversion unit are connected with described high speed system bus AHB respectively;
Described timer, described external interrupt control module and described low-speed communication interface are connected with described low speed peripheral bus APB respectively;
Described AD converting unit is connected with described ISO18000-6B protocol processing unit respectively with described DA converting unit, and described resetting is connected with described microprocessor with clock control cell;
Described ISO18000-6B protocol processing unit comprises the ahb bus interface, random access memory ram, control register, the down-sampling subelement, variable bandwidth filter, phase bit recovery subelement, matched filter, sampling judgement subelement, the FMO subelement of decoding, the first CRC check subelement, string and conversion subelement, receive the state of a control machine, and string conversion subelement, send the state of a control machine, the second CRC check subelement, the Manchester's cde subelement, power convergent-divergent subelement, hilbert filter, the predistortion subelement, lag line, frequency hopping control subelement and up-sampling subelement; Described FM0 decoding subelement is used for signal is carried out the FMO decoding, and described Manchester's cde subelement is used for signal is carried out Manchester's cde.
Further, described base band control chip comprises ten DAC output channels of two-way and one tunnel eight DAC output channel, and each passage is respectively applied to I passage and Q passage baseband digital signal in ten DAC output channels of described two-way; Described one tunnel eight DAC output channel is used for providing power amplifier control information.
Further, described base band control chip comprises ten ADC input channels of two-way, is respectively applied to the baseband digital signal of I passage and Q passage.
Further, described base band control chip comprises one group of GPIO mouth, is used to radio frequency chip to send control information and/or is used for the feedback information of received RF chip.
Further, described high-speed communication interface comprises USB2.0 interface and jtag interface.
Further, described low-speed communication interface comprises UART interface, SPI interface and IIC interface.
Further, described timer comprises two sixteen bit timer conter timers and real-time clock.
According to same design of the present utility model, the utility model also provides a super high frequency radio frequency read-write equipment, comprises aforesaid base band control chip.
The utility model purpose is the deficiency at existing RFID technology, and the low-power consumption miniaturization UHF RFID read-write equipment base band signal processing chip of a kind of miniaturization, high integration, high adaptive faculty, support ISO18000-6B agreement that antijamming capability is strong is provided.
Description of drawings
Fig. 1 is the basic structure block diagram of a kind of read-write equipment in the prior art;
Fig. 2 is the basic structure block diagram of a kind of read-write equipment in the prior art;
Fig. 3 is chip of the present utility model mechanism block diagram;
Fig. 4 is the application apparatus structured flowchart of chips incorporate radio-frequency front-end of the present utility model;
Fig. 5 is the inner structure block diagram of protocol processing unit.
Embodiment
Further specify the technical solution of the utility model below in conjunction with accompanying drawing and by embodiment.Specific embodiment described herein only is used for explanation the utility model, but not to restriction of the present utility model.
It is chip structure block diagram of the present utility model.As shown in Figure 3, the described base band control chip of present embodiment comprises microprocessor, resets and clock control cell, memory storage control module, timer, external interrupt control module, AD converting unit, DA converting unit, ISO18000-6B protocol processing unit, bus control unit, bus conversion unit, high-speed communication interface, low-speed communication interface, debugging interface and bus on chip, and described ISO18000-6B protocol processing unit is for the treatment of the electronic tag of ISO18000-6B consensus standard.
Wherein, described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, described high speed system bus AHB is connected by bridge with low speed peripheral bus APB, and each described high speed system bus AHB and each described low speed peripheral bus APB are equipped with address decoder and bus arbiter.
Described microprocessor, described debugging interface, described memory storage control module, described high-speed communication interface, ISO18000-6B protocol processing unit, bus control unit and described bus conversion unit are connected with described high speed system bus AHB respectively.
Described timer, described external interrupt control module and described low-speed communication interface are connected with described low speed peripheral bus APB respectively.
Described AD converting unit is connected with described ISO18000-6B protocol processing unit respectively with described DA converting unit, and described resetting is connected with described microprocessor with clock control cell.
The described base band control chip of present embodiment can be the base band control chip, SOC (System on Chip) is system level chip, be that functional units such as peripheral hardware, communication interface, A/D and D/A conversion in the needed microprocessor of system, the sheet are integrated on a slice chip, the SOC (system on a chip) that forms has characteristics such as high integration, cost are low, good reliability, low-power consumption.
In the present embodiment, microprocessor adopts the CPU core of 32 SPARC frameworks, and for example based on the kernel of leon3, this CPU core can be finished functions such as coordination, configuration and status monitoring to whole each component units of base band control chip by instruction.Utilize software to realize functions such as anti-collision algorithm, protocol stack control at this CPU nuclear, also can be at this kernel operation various common embedded OSs, for example Linux or Windows etc.Described microprocessor has the low power consumption control function, various modes such as support power down, standby, work, wake up, and can independently control each interface.The mode that the implementation of low-power consumption adopts the dynamic clock Control of Voltage to be combined with gated clock.
Two buses of having followed the AMBA2.0 protocol configuration in the base band control base band control chip.
Described debugging interface comprises JTAG debugging interface and serial debugging interface, supports on-line debugging and program to download.
Described memory interface disposes PROM, SRAM, SDRAM, DDR2 and FLASH interface.
Described DA converting unit comprises ten DAC output channels of two-way, is respectively applied to the needed I passage of quadrature modulator and Q passage baseband digital signal; One tunnel eight DAC output channel is used for providing power amplifier control information; Described DA converting unit AD converting unit comprises ten ADC input channels of two-way, is respectively applied to import I passage after the quadrature demodulation and the baseband digital signal of Q passage.
Described chip also comprises one group of special I/O mouth, is used for providing to the extra control information of base band control base band control chip or chip and/or is used for the feedback information of received RF chip.
High-speed communication interface disposes USB2.0, Ethernet interface, GPIO interface, is convenient to expand new equipment.USB2.0 comprises two kinds of interfaces of principal and subordinate.
The low-speed communication interface configuration has UART interface, SPI interface, IIC interface and two groups 32 s' GPIO mouth.
Timer comprises two sixteen bit timer conter timers and real-time clock, can be used as WatchDog Timer, or the PWN output function.
Fig. 4 is the structured flowchart of the described protocol processing unit of present embodiment.Described ISO18000-6B protocol processing unit is supported the ISO18000-6B agreement.ISO18000-6B is one of at present the most frequently used read-write equipment communication protocol, is that use is more extensive at present, the read-write equipment puppy parc that stability is best.
In the present embodiment, described ISO18000-6B protocol processing unit comprises the ahb bus interface, random access memory ram, control register, the down-sampling subelement, variable bandwidth filter, phase bit recovery subelement, matched filter, sampling judgement subelement, the FMO subelement of decoding, the first CRC check subelement, string and conversion subelement, receive the state of a control machine, and string conversion subelement, send the state of a control machine, the second CRC check subelement, the Manchester's cde subelement, power convergent-divergent subelement, hilbert filter, the predistortion subelement, lag line, frequency hopping control subelement and up-sampling subelement; Described FM0 decoding subelement is used for signal is carried out the FMO decoding, and described Manchester's cde subelement is used for signal is carried out Manchester's cde.
Described predistortion subelement is only worked under the situation that adopts the SSB-ASK modulation.
Microprocessor unit: the CPU core (based on leon3) of 32 SPARC frameworks that the base band control chip is built-in, utilize software to realize functions such as anti-collision algorithm, protocol stack control at this CPU nuclear.Also can be at the various common embedded OSs of this kernel operation.
Bus on chip: two buses of having followed the AMBA2.0 standard configuration in the base band control chip are respectively high speed system bus AHB and low speed peripheral bus APB.Microprocessor unit, storer control, protocol processing unit, debug interface unit and communication interface USB at a high speed etc. hang on the high-speed bus.And low-speed communication interface SPI, UART, IIC etc. are to hang on the low speed peripheral bus.Link together by bus bridge between high-speed bus and the low speed bus, every bus has independent address decoder and bus arbiter.
Memory interface: the base band control chip can be expanded multiple memory devices, comprises EPROM, DDR2, SRAM, DRAM, FLASH etc.
DAC output channel: comprise 2 tunnel 10 DAC output channels, be respectively applied to the needed I passage of quadrature modulator and Q passage baseband digital signal; One tunnel 8 DAC output channel is used for providing power amplifier control information.
ADC input channel: comprise that 2 tunnel 10 ADC passages are used for I passage after the input quadrature demodulation and the baseband digital signal of Q passage.
ISO18000-6B protocol processing unit: comprise two 16 times of down-sampling subelements, two 1248 times of variable down-sampling subelements, a variable bandwidth filter, a digital phase place recovery unit, a matched filter, a power detector, a sampling judgement subelement, a FM0 decoding subelement, two CRC-16 syndrome unit, go here and there and modular converter for one, one receives state of a control machine module, a parallel serial conversion module, a PIE coding subelement, a power Zoom module, a hilbert filter, a predistortion subelement, a frequency hopping control module, one group of lag line.The Manchester coding, FM0 decoding, CRC check, RSSI that can finish baseband signal by this unit detects, receives clock information recoverys of signal, the predistortion that transmits, produces frame synchronization sequence, the state control of requirement etc. carries on an agreement, the control information of protocol stack and anti-collision algorithm operate on the microprocessing unit with the form of software, and this mode makes chip have stronger upgrading ability.
High-speed communication interface: SOC has disposed USB2.0, Ethernet interface, DDR2 interface, memory interface, is convenient to expand new equipment.USB2.0 comprises two kinds of interfaces of principal and subordinate.
The low-speed communication interface: the base band control chip has disposed UART interface, SPI interface, IIC interface module and two groups of 32 GPIO mouths.
Timer: the base band control chip is built-in two sixteen bit timers, can be used as WatchDog Timer, or the PWN output function.
The low-power consumption module: various modes such as this base band control chip supports power down, standby, work, wake up, and can independently control each interface module.The implementation of low-power consumption adopts the dynamic clock voltage control mode.
Chip has also disposed UART, JTAG debugging interface, supports on-line debugging and program to download.
The super high frequency radio frequency read-write equipment structured flowchart that utilizes the utility model to make up is illustrated in fig. 3 shown below, as seen from Figure 3, the chip of present embodiment has directly been exported the necessary I passage of orthogonal modulation and Q passage baseband signal, and (this signal is to handle via the ISO18000-6B protocol processing unit, through the signal after coding, filtering moulding, the processing of modulation three phases), be used for the P channel digital signal that the power amplifier gain is adjusted, this three road signal has passed through built-in DA converter, the actual simulating signal that is output as when externally exporting.I, Q two paths of signals are sent into antenna through circulator after orthogonal modulation, amplification and filtering, constitute transmission channel, and concrete emission process has a little difference according to different radio-frequency front-ends.For receiving cable, this chip configuration input I passage and Q channel interface, be used for to receive through quadrature demodulation and through LNA and wave filter, the input chip, chip internal is built-in with 10 AD converter, and concrete receiving course has a little difference according to the difference of radio-frequency front-end.
Support the protocol processing unit functional structure of ISO18000-6B as shown in Figure 5, comprised two 16 times of down-sampling subelements, two 1248 times of variable down-sampling subelements, a variable bandwidth filter, a digital phase place recovery unit, a matched filter, a power detector, a sampling judgement subelement, a FM0 decoding subelement, a miller decoding subelement, two CRC-16 syndrome unit, a CRC-5 syndrome unit, go here and there and modular converter for one, one receives state of a control machine module, a parallel serial conversion module, a PIE coding subelement, a power Zoom module, a hilbert filter, a predistortion subelement, a frequency hopping control module, one group of lag line.The course of work of this ISO18000-6B protocol processing unit is as follows:
(1) process of transmitting: after main frame or input equipment are sent to leon3 with control information, leon3 writes required transmission data among the RAM in corresponding address space in the protocol processing unit according to the requirement of protocol stack, then control register is arranged, with required control information (as data length, the form of synchronous head, the CRC check mode, send data rate etc.) write in the control register, at last with the transmission enable bit set in the control register, module enters transmission flow, the state of a control machine is according to the information in the control register, data are read from RAM, through also sending into the CRC check subelement after the string conversion, the CRC check subelement produces the corresponding check sign indicating number, and with the packing of data and check code (be about to check code be added on former data after), serial input Manchester coding subelement, Manchester coding subelement carries out Manchester coding back and adds corresponding frame head data according to the information in the control register, makes data form corresponding frame format.Then the data after the framing are sent into the raised cosine filter filtering moulding of roll-offing, after carry out the power convergent-divergent, send into modulation module.According to the information in the control register, select corresponding modulation system, if the DSB-ASK modulation system is then sent into the delayed line of the data after the filtering moulding DAC output of I path, the data after the filtering moulding are sent into the DAC output of Q channel after predistortion.If the SSB-ASK modulation system is then sent into the delayed line of the data after the filtering moulding DAC output of I path, the data after the filtering moulding are sent into the DAC output of Q channel after hilbert filter filtering.
(2) receiving course: through the I of quadrature receiver output, the Q two paths of signals, at first be converted to digital signal through built-in AD converter after sending into chip, because AD is over-sampling a/d C, so digital signal needs the down-sampling through 16 times, the back according to the different choice 1 of receiving velocity 248 times down-sampling (receiving velocity is determined by the order in the agreement, the speed that this means the label return data is determined by read write line, so label return data speed is known for read write line is seen), after the data process variable bandwidth filter filtering of the down-sampling second time, send into digital CDR module and carry out the recovery of data clock information, the clock information that recovers to come out is sent into sampling judgement subelement, data message through matched filtering is sampled, data after the sampling are sent into corresponding decoding subelement (FM0) decoding, decoded data are through after the CRC check, after sending into string and modular converter, under the control that receives the state of a control machine, write the RAM in corresponding address space, and the set of accepting state position is represented to accept data finish.After leon3 detects the zone bit set, corresponding RAM data are read, require to handle accordingly according to protocol stack.
The technical scheme that present embodiment provides, support required various base band signal process functions, agreement control function, codec functions, radio frequency control function, predistortion function, synchronizing function, modulation function and the processor of UHF rfid interrogator of ISO18000-6B agreement to integrate, and can realize support to custom protocol by the mode of revising software.Microprocessor (realizing based on the 32bit SPARC framework CPU leon3 that increases income) is arranged in the chip, can Embedded Operating System (linux, uc-os etc.), but the capacity of extended memory, the protocol processing unit of integrated support ISO18000-6B, this unit is embedded in the bus as an AHB slave module, and chip also provides open software interface, is used for realizing functions such as anticollision, agreement control, database, middleware.Can be applied to various UHF RFID application scenario easily.
The above only is preferred embodiment of the present utility model, and is in order to limit the utility model, not all within spirit of the present utility model and principle, any modification of doing, is equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (8)
1. base band control chip, comprise microprocessor, reset and clock control cell, memory storage control module, timer, external interrupt control module, AD converting unit, DA converting unit, ISO18000-6B protocol processing unit, bus control unit, bus conversion unit, high-speed communication interface, low-speed communication interface, debugging interface and bus on chip, described ISO18000-6B protocol processing unit is characterized in that for the treatment of the electronic tag of ISO18000-6B consensus standard:
Described bus on chip comprises high speed system bus AHB and low speed peripheral bus APB, described high speed system bus AHB is connected by bridge with low speed peripheral bus APB, and each described high speed system bus AHB and each described low speed peripheral bus APB are equipped with address decoder and bus arbiter;
Described microprocessor, described debugging interface, described memory storage control module, described high-speed communication interface, ISO18000-6B protocol processing unit, bus control unit and described bus conversion unit are connected with described high speed system bus AHB respectively;
Described timer, described external interrupt control module and described low-speed communication interface are connected with described low speed peripheral bus APB respectively;
Described AD converting unit is connected with described ISO18000-6B protocol processing unit respectively with described DA converting unit, and described resetting is connected with described microprocessor with clock control cell;
Described ISO18000-6B protocol processing unit comprises the ahb bus interface, random access memory ram, control register, the down-sampling subelement, variable bandwidth filter, phase bit recovery subelement, matched filter, sampling judgement subelement, the FMO subelement of decoding, the first CRC check subelement, string and conversion subelement, receive the state of a control machine, and string conversion subelement, send the state of a control machine, the second CRC check subelement, the Manchester's cde subelement, power convergent-divergent subelement, hilbert filter, the predistortion subelement, lag line, frequency hopping control subelement and up-sampling subelement; Described FM0 decoding subelement is used for signal is carried out the FMO decoding, and described Manchester's cde subelement is used for signal is carried out Manchester's cde.
2. base band control chip as claimed in claim 1, it is characterized in that, described base band control chip comprises ten DAC output channels of two-way and one tunnel eight DAC output channel, and each passage is respectively applied to I passage and Q passage baseband digital signal in ten DAC output channels of described two-way; Described one tunnel eight DAC output channel is used for providing power amplifier control information.
3. base band control chip as claimed in claim 2 is characterized in that, described base band control chip comprises ten ADC input channels of two-way, is respectively applied to the baseband digital signal of I passage and Q passage.
4. base band control chip as claimed in claim 2 is characterized in that, described base band control chip comprises one group of GPIO mouth, is used to radio frequency chip to send control information and/or is used for the feedback information of received RF chip.
5. base band control chip as claimed in claim 4 is characterized in that, described high-speed communication interface comprises USB2.0 interface and jtag interface.
6. base band control chip as claimed in claim 5 is characterized in that, described low-speed communication interface comprises UART interface, SPI interface and IIC interface.
7. base band control chip as claimed in claim 6 is characterized in that, described timer comprises two sixteen bit timer conter timers and real-time clock.
8. a super high frequency radio frequency read-write equipment is characterized in that, described read write line comprises as the described base band control chip of one of claim 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103353944A (en) * | 2013-04-27 | 2013-10-16 | 无锡昶达信息技术有限公司 | Baseband control chip and ultrahigh-frequency radio frequency read-write device |
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| CN103353944A (en) * | 2013-04-27 | 2013-10-16 | 无锡昶达信息技术有限公司 | Baseband control chip and ultrahigh-frequency radio frequency read-write device |
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Effective date of registration: 20171031 Address after: West Street, Qingyang District of Chengdu City, Sichuan province 610000 84 1 unit 1 Building 6 floor, No. 628 Patentee after: CHENGDU HONGFU RADIO TECHNOLOGY Co.,Ltd. Address before: 214135 Jiangsu New District of Wuxi City Branch Park University Science Park China sensor network Qingyuan Road No. 20 building B room 406 career Patentee before: WUXI CHANG DA INFORMATION TECHNOLOGY Co.,Ltd. |
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