CN203191481U

CN203191481U - Ageing test system for inverter

Info

Publication number: CN203191481U
Application number: CN 201320180285
Authority: CN
Inventors: 张普光; 王一鸣; 许颇
Original assignee: NINGBO GINLONG TECHNOLOGIES Co Ltd
Current assignee: Ginlong Technologies Co Ltd
Priority date: 2013-04-11
Filing date: 2013-04-11
Publication date: 2013-09-11
Anticipated expiration: 2023-04-11

Abstract

The utility model relates to an ageing test system for an inverter, which is used for performing a functional test on a subsystem comprising an embedded chip. The ageing test system comprises the embedded subsystem and a test platform, wherein the embedded subsystem comprises the embedded chip, as well as an IO (input-output) port interface circuit and an AD (analogue-digital) port interface circuit which are connected with the embedded chip; the test platform provided with a filter circuit and written with a firmware program is accessed via an IO output port and an AD input and lead-out port, and used for testing whether the IO port and the interface circuit of each path, and the AD port and the interface circuit of each path are normal; and after the judgement on each path is concluded, whether the circuit of each path is in a normal state is judged by displaying the external LED (light-emitting diode) of the embedded chip or serial communication item by item, and the record is printed. The ageing test system disclosed by the utility model is capable of very conveniently and effectively testing whether the outward input and output ports, welding and peripheral circuits of chips in the embedded subsystems which are produced in batches are normal, thus increasing the production efficiency, and ensuring the test quality.

Description

The inverter aging testing system

Technical field

The utility model relates to a kind of inverter aging testing system, relates in particular to comprising the system that embedded chip and peripheral circuit subsystem carry out functional test.

Background technology

Embedded system more and more is applied to industry and various fields in life, and a lot of complicated a little any embedded systems all are made up of several parts.Be exactly the embedded system of a protection embedded chip as solar grid-connected inverter or wind-force combining inverter, it generally can be made up of embedded core control subsystem circuit, external voltage current detection circuit, inverter circuit and filtering circuit unit.Embedded core control subsystem is finished the control function of total system, receives the various analog and digital signals of outside input and sends correct control output signal through calculating.In large-scale production run, each unit of embedded system must could finally be assembled together through reliable functional test, and carries out final test.Embedded core control subsystem more should be carried out full test as the brain of entire product system, guarantees the reliability of itself and external circuit.If one has the embedded key control unit of function problem directly to be assembled to entire product system and final test, might cause very much collapse and the permanent damage in other unit of total system.

How embedded core control subsystem circuit is carried out Validity Test, and in high volume production process, guarantee high efficiency.Present conventional application testing method has the ICT(online circuit to detect), the AOI(automated optical inspection) etc., but these all are peripheral circuit to be carried out physical fault detect, and can not directly detect the function of embedded chip itself and whole unit.

The utility model content

In view of this, the purpose of this utility model is to provide a kind of inverter aging testing system, comprise the self-testing system to the subsystem Validity Test of embedded chip and peripheral circuit, be used for being implemented in the functional test that product is produced embedded core subsystem in enormous quantities.

The utility model purpose is achieved through the following technical solutions: a kind of inverter aging testing system, be used for the subsystem that comprises embedded chip is carried out functional test, comprise embedded subsystem and test platform, described embedded subsystem comprises embedded chip, the IO mouth interface circuit that is connected with described embedded chip and AD mouth interface circuit, insert a test platform that has filtering circuit and embedded firmware agent by IO output and AD input outlet, whether be used for each road IO mouth of test and interface circuit and Ge Lu AD mouth and interface circuit normal, each road judge finish after, by the external LED lamp of described embedded chip or serial communication being shown one by one each road circuit whether normal condition and print record.

By a test platform is inserted in the core cell outside that comprises embedded chip, write a specific embedded firmware agent, can realize the self-test of embedded subsystem own, content measurement comprises whether embedded chip IO port welding is correct, whether IO mouth output circuit is correct, whether the output interface terminal is correct, whether AD mouth sample circuit is correct, whether the welding of embedded chip AD port is correct etc.

On the such scheme basis, described embedded subsystem and external interface have the output of one road IO mouth at least, and all external IO mouths all are set at output; And has the input of one road AD mouth at least.

The utility model can very conveniently test out effectively production in enormous quantities embedded subsystem chips itself external input and output port whether normal, whether welding normal, whether peripheral circuit normal.Can enhance productivity effectively, and guarantee the production test quality.

Below in conjunction with drawings and Examples the utility model is further described.

Description of drawings

Fig. 1 is the utility model embedded system test schematic diagram;

Fig. 2 is filtering circuit 1 commonly used in the embedded system test platform of 70 parts among Fig. 1;

Fig. 3 is filtering circuit 2 72 commonly used in the embedded system test platform of 70 parts among Fig. 1;

Fig. 4 is the numeral input of filtering circuit, the oscillogram of simulation output;

The number in the figure explanation:

100---embedded subsystem;

30---embedded chip; 40---IO mouth interface circuit;

50---AD mouth interface circuit;

60---IO output and AD input outlet;

200---test platform;

70---filtering circuit; 71---filtering circuit one; 72---filtering circuit two.

Embodiment

As shown in Figure 1, a kind of inverter aging testing system of the utility model, be used for the subsystem that comprises embedded chip is carried out functional test, comprise embedded subsystem 100 and test platform 200, described embedded subsystem 100 comprises embedded chip 30, the IO mouth interface circuit 40 that is connected with described embedded chip and AD mouth interface circuit 50, insert a test platform 200 that has filtering circuit 70 and embedded firmware agent by IO output and AD input outlet 60, whether be used for each road IO mouth of test and interface circuit and Ge Lu AD mouth and interface circuit normal, each road judge finish after, by described embedded chip 30 external LED lamps or serial communication being shown one by one each road circuit whether normal condition and print record.

On the such scheme basis, described embedded subsystem and 100 external interfaces have the output of one road IO mouth at least, and all external IO mouths all are set at output; And has the input of one road AD mouth at least.

The utility model can carry out Validity Test to the subsystem that comprises embedded chip and peripheral circuit.Can realize whether input/output port to embedded chip 30 itself normal, whether welding normal, the peripheral circuit Validity Test that carries out such as normal whether.

Principle of work of the present utility model is: at first, embedded chip 30 selects to enter fixing test procedure, its all external IO mouths all are set at output, and send pwm signal according to certain pulse width, are sent to IO output and AD input outlet 60 through IO mouth interface circuit.The supplied with digital signal waveform of concrete output waveform such as Fig. 4.The pwm signal of IO mouth is sent in the filtering circuit 70 of test platform 200 then, and digital signal is carried out filtering.Filtering circuit is shown in Fig. 2 filtering circuit 1 and Fig. 3 filtering circuit 2 72.Circuit is exported simulating signal as shown in Figure 4 after the filtering.At last, simulating signal is sent in the tested embedded subsystem 100 by IO output and AD input outlet 60, is sent to the AD interface pin of embedded chip 30 through AD mouth interface circuit 50.Embedded chip 30 controls than the voltage that can configure respective channel AD sampling what are according to accounting for of the every road IO mouth pwm pulse width that sends like this, whether set bound in firmware program after, it is normal to judge this road IO mouth and interface circuit and this road AD mouth and interface circuit.Each road is judged can be by showing each road circuit whether normal condition and print record one by one after finishing to embedded chip 30 external LED lamps or serial communication.

In sum, the utility model can very conveniently test out effectively production in enormous quantities embedded subsystem chips itself external input and output port whether normal, whether welding normal, whether peripheral circuit normal.Native system can be enhanced productivity effectively, and guarantees the production test quality.

Above embodiment only is used for the explanation the technical solution of the utility model but not to the restriction of the utility model protection domain; although with reference to preferred embodiment the utility model has been done detailed description; those of ordinary skill in the art is to be understood that; can make amendment or be equal to replacement the technical solution of the utility model, and not break away from essence and the scope of technical solutions of the utility model.

Claims

1. inverter aging testing system, be used for the subsystem that comprises embedded chip is carried out functional test, it is characterized in that: comprise embedded subsystem (100) and test platform (200), described embedded subsystem comprises embedded chip (30), the IO mouth interface circuit (40) that is connected with described embedded chip (30) and AD mouth interface circuit (50), insert a test platform (200) that has filtering circuit (70) by IO output and AD input outlet (60), the external LED lamp of described embedded chip (30) or serial communication show each road circuit whether normal condition and print record one by one.

2. inverter aging testing system according to claim 1 is characterized in that: described embedded subsystem and external interface have the output of one road IO mouth at least, and all external IO mouths all are set at output; And has the input of one road AD mouth at least.