CN102901905B - Parallel bus testing method - Google Patents
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- CN102901905B CN102901905B CN201210451366.1A CN201210451366A CN102901905B CN 102901905 B CN102901905 B CN 102901905B CN 201210451366 A CN201210451366 A CN 201210451366A CN 102901905 B CN102901905 B CN 102901905B
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Abstract
The invention discloses a parallel bus testing device which comprises a controller, a data acquisition card and a signal distributor, wherein the controller is connected with the data acquisition card; the data acquisition card is connected with the signal port of the signal distributor; the first test port and the second test port of the signal distributor are respectively connected with the input end and the output end of a bus back board; the controller comprises an application module, a recording module and a determining module, wherein the application module is used for applying high-level signals to a selected input pin in a signal port through the data acquisition card and setting all input pins except the selected input pin into a high-resistance state; the recording module is used for acquiring the level states of all output pins of the signal port, which are acquired by the data acquisition card; and the determining module is used for determining a first circuit state of a bus corresponding to the selected pin and a second circuit state between the corresponding bus and any other bus according to the level states of all the output pins. The invention also discloses a parallel bus testing method.
Description
Technical field
The present invention relates to bus test technical field, particularly relate to a kind of parallel bus proving installation and method.
Background technology
Parallel bus is the passage transmitting data between parallel interface and computer equipment, parallel bus generally comprises address bus, data bus and control bus three class, generally, parallel bus can be with multiple controller or control module, and these controllers or control module are all independently, they are interknited by parallel bus.Parallel bus form is physically generally one piece of backboard, multiple controller or control module can be linked together by this backboard, forms a parallel bus system.Due to this backboard containing parallel bus, usually this backboard is claimed to be " bus backplane ".
Parallel bus in bus backplane is the connection bridge of each control assembly in system, most important in systems in which.If occur such as in the process generating, process described bus backplane: rosin joint is opened a way or dripped the faults such as weldering short circuit and do not check out in testing, once flow into onsite application, gently then produce data errors, system works is abnormal; Heavy then produce short circuit, the accident such as damage control system or system is on fire.So the bus backplane newly processed can must be come into operation by off test.But, general one piece of bus backplane has 40 to 80 lines, every root line there is the electric connecting point on 8 ~ 16 connectors, the electric connecting point of more than 300 is had like this with regard to one, need to test the electric connecting point in bus backplane, in order to determine that open fault has appearred in which root bus, and there is short trouble between which root bus, thus further faulty line has been repaired.
On a production line, some producers are the methods using manual test, namely manually utilize multimeter to carry out break-make measurement to every two electric connecting points, but this method workload is huge, efficiency is extremely low and contain the subjective factor of people, often occurs omitting test or test by mistake.And some producers utilize LED to carry out test bus, namely a LED is added at the two ends of a bus, to bus voltage, if LED is bright, cable leads to, otherwise then obstructed, obviously, this equipment needs a large amount of LED and not directly perceived, the more important thing is, when between bus, occur short circuit, just cannot test in this way.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of parallel bus proving installation and method, with realize can accurately, object that is quick, comprehensively whole circuits of test bus backboard.
For achieving the above object, the invention provides a kind of parallel bus proving installation, described device comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, first test port of described signal distributor and the second test port are connected with the input end of bus backplane and output terminal respectively, all current-limiting resistance is in series with between every bar connecting line of described signal port and described first test port, all pull down resistor is in series with between every bar connecting line of described signal port and described second test port and ground wire, described controller comprises:
Applying module, for applying the selected input pin of high level signal in described signal port through described data collecting card, and other all input pin except described selected input pin being all set to high-impedance state;
Logging modle, for obtaining the level state of all output pins of the described signal port that described data collecting card collects;
Determination module, for determining the corresponding first line state of bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
Preferably, in said apparatus, described determination module comprises:
Detecting unit, for detecting the level state of described all output pins;
First normal condition determining unit, when being high level for detecting the level state of output pin corresponding to the described selected input pin that obtains at described detecting unit, determines that the line status of the corresponding bus of described selected input pin is normal;
Second normal condition determining unit, for detect other all output pin except the output pin corresponding except described selected input pin that obtain at described detecting unit level state in there is low level time, determine that level state be the line status of the bus that low level output pin is corresponding is normal;
Open-circuit condition determining unit, when being low level for detecting the level state of output pin corresponding to the described selected input pin that obtains at described detecting unit, determines that the line status of the corresponding bus of described selected input pin is open circuit;
Short-circuit condition determining unit, for detect other all output pin except the output pin corresponding except described selected input pin that obtain at described detecting unit level state in there is high level time, determine that level state be the bus that the output pin of high level is corresponding is short circuit with the line status between the corresponding bus of described selected input pin.
Preferably, in said apparatus, determine the corresponding first line state of bus of each selected input pin and the second line status between described corresponding bus and other bus successively according to pin numbering.
Preferably, said apparatus also comprises: using the input end of described bus backplane as output terminal, and using the output terminal of described bus backplane as input end, determine the corresponding first line state of bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of output pins all in described signal port.
Preferably, in said apparatus, the connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
Present invention also offers a kind of parallel bus method of testing, described method is applied to parallel bus proving installation, described proving installation comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, first test port of described signal distributor and the second test port are connected with the input end of bus backplane and output terminal respectively, all current-limiting resistance is in series with between every bar connecting line of described signal port and described first test port, all pull down resistor is in series with between every bar connecting line of described signal port and described second test port and ground wire, described controller realizes the test to parallel bus according to following steps:
Apply the selected input pin of high level signal in described signal port through described data collecting card, and other all input pin except described selected input pin is all set to high-impedance state;
Obtain the level state of all output pins of the described signal port that described data collecting card collects;
The corresponding first line state of bus of described selected pin and the second line status between described corresponding bus and other bus is determined according to the level state of described all output pins.
Preferably, in the above-mentioned methods, the described level state according to described all output pins determines that the corresponding first line state of bus of described selected pin and the second line status between described corresponding bus and other bus comprise:
Detect the level state of described all output pins;
If the level state of the output pin that described selected input pin is corresponding is high level, then determine that the line status of the corresponding bus of described selected input pin is normal;
If there is low level in the level state of other all output pin beyond the output pin that described selected input pin is corresponding, then determine that level state be the line status of the bus that low level output pin is corresponding is normal;
If the level state of the output pin that described selected input pin is corresponding is low level, then determine that the line status of the corresponding bus of described selected input pin is open circuit;
If there is high level in the level state of other all output pin beyond the output pin that described selected input pin is corresponding, then determine that level state be the bus that the output pin of high level is corresponding is short circuit with the line status between the corresponding bus of described selected input pin.
Preferably, in the above-mentioned methods, the corresponding first line state of bus of each selected input pin and the second line status between described corresponding bus and other bus is determined successively according to pin numbering.
Preferably, said method also comprises: using the input end of described bus backplane as output terminal, and using the output terminal of described bus backplane as input end, determine the corresponding first line state of bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of output pins all in described signal port.
Preferably, in the above-mentioned methods, the connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
Visible, parallel bus proving installation of the present invention and method, by described high level signal to be put on a selected input pin of signal distributor signal port through data collecting card, and other all input pin except described selected input pin is all set to high-impedance state; Obtain the level state of all output pins of the described signal port that described data collecting card collects; Finally determine whether the corresponding bus of selected pin has occurred open circuit according to the level state of described all output pins, and whether there is short circuit between the corresponding bus of this selected pin and other bus, thus the line status that can obtain between the line status of each bus in bus backplane itself and bus, the present invention accurately, fast, comprehensively can test the situation of parallel bus open circuit, short circuit, and can realize the test of any one bus backplane.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of parallel bus proving installation of the present invention;
Fig. 2 is signal distributor internal circuit diagram of the present invention;
Fig. 3 is the structural representation of determining unit in parallel bus proving installation of the present invention;
Fig. 4 is line fault pattern diagram of the present invention;
Fig. 5 is pin status of the present invention and line status table;
Fig. 6 is the schematic flow sheet of parallel bus method of testing of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The line status of bus comprises normally, short circuit, these three kinds of situations of opening a way, short-circuit condition comprises two line short circuits or multi-thread short circuit; Open-circuit condition comprises single line open circuit or multi-thread open circuit.The present invention can not only judge that bus backplane occurs short circuit and can locate which root bus concrete producing short circuit, can also judge that bus backplane occurs open circuit and can locate which root bus concrete producing open circuit, this has very large directive significance to reprocessing after test.
The present invention is adopted to test parallel bus, controller (can be computing machine or industrial control computer) control data capture card is mainly utilized to send an electric signal to a certain of bus one end, then monitor the state of all buses at the other end and record all quantity of states, to obtain first group of Monitoring Data; In like manner, then send an electric signal to another root of bus one end, then monitor the state of all buses at the other end and record all quantity of states, to obtain second group of Monitoring Data; The like, all buses are all tested once, has how many buses just how much can be organized data, just can obtain the line status of whole bus backplane finally by these data of computer program analysis.
Shown in Figure 1, Fig. 1 is the structural representation of parallel bus proving installation provided by the invention, described device comprises: controller 1, data collecting card 2, signal distributor 3, described controller 1 is connected with described data collecting card 2, described data collecting card 2 is connected with the signal port XP3 of described signal distributor 3, first test port XP1 of described signal distributor 3 and the second test port XP2 are connected with the input end of bus backplane 4 and output terminal respectively, all current-limiting resistance is in series with between every bar connecting line of described signal port XP3 and described first test port XP1, all pull down resistor is in series with between every bar connecting line of described signal port XP3 and described second test port XP2 and ground wire, described controller 1 comprises:
Applying module 11, for applying the selected input pin of high level signal in described signal port through described data collecting card, and other all input pin except described selected input pin being all set to high-impedance state;
Logging modle 12, for obtaining the level state of all output pins of the described signal port XP3 that described data collecting card 2 collects.
Determination module 13, for determining the corresponding first line state of bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
Wherein, described first line state is normal or open circuit, and described second line status is normal or short circuit.
For the ease of understanding, first specifically introduce the inner structure of signal distributor 3 below.Signal distributor internal circuit diagram shown in Figure 2, has identical connected mode based on every root bus, for convenience of explanation, only gives two bus connections in this circuit diagram.This signal distributor internal circuit comprises two electron-like components and parts:
1), connector plug (XP1 ~ XP3)
XP1 with XP2 is the plug for being connected bus backplane, plug can be inserted on two sockets corresponding in bus backplane during test, if for the bus of 40 cores (address bus 16, data bus 16, control bus 8), need choose the plug that XP1 and XP2 is 40 cores, and plug model is supporting with the socket in bus backplane to be measured; XP3 is the plug for connection data capture card, its model needs and the socket of data collecting card mates, wherein, XP3 plug is divided into input pin part (as XP3:1) and output pin part (as XP3:101), and the number of pins of every part is all identical with the bus number in bus backplane.
2), resistance
If still for the bus of 40 cores, need in circuit to connect current-limiting resistance R1 ~ R40, its effect prevents bus short circuit and impacts data collecting card; And pull down resistor R101 ~ R140 need be connected, its effect prevents bus from opening a way and bus signals is played pendulum.
When needing to test, first plug XP1 and XP2 is inserted on two sockets of bus backplane respectively.Bus between such XP1:1 (No. 1 pin of plug XP1), XP2:1 (No. 1 pin of plug XP2) and pin XP1:1 and XP2:1 has just linked together, and in like manner, other pin and bus have also linked together.During test, first test No. 1 pin, high level is set to by plug XP3:1 (No. 1 pin of plug XP3), other pin (XP3:2 ~ XP3:40) is set to high-impedance state, and keep, gather the state of all output pins (XP3:101 ~ XP3:140) afterwards again, state is divided into: high level or low level.In like manner, the test process of No. 2 pins and other all pin is with No. 1 pin.
In addition, in the parallel bus proving installation shown in Fig. 1, data collecting card is the capture card with digital I/O mouth, the interface of it and controller is numerous, data collecting card is connected with controller by the form of pci interface or ISA interface or USB interface or Ethernet interface, when testing bus, controller transmits control signal the I/O mouth of driving data capture card, wherein, I/O mouth output state has: high level (1), low level (0), high resistant (∞); I/O mouth input state has: high level (1), low level (0).
The structural representation of determining unit in parallel bus proving installation shown in Figure 3, described determination module 13 comprises:
Detecting unit 131, for detecting the level state of described all output pins;
First normal condition determining unit 132, when level state for the output pin (as XP3:101) detecting described selected input pin (as the XP3:1) correspondence obtained at described detecting unit 131 is high level, determine that the line status of the corresponding bus of described selected input pin (as XP3:1) (No. 1 bus) is normal;
Second normal condition determining unit 133, for detect other all output pin except the output pin (as XP3:101) corresponding except described selected input pin (as XP3:1) that obtain at described detecting unit 131 level state in there is low level time, determine that level state be the line status of the bus (No. 2 buses) of low level output pin (as XP3:102) correspondence is normal;
Open-circuit condition determining unit 134, when level state for the output pin (as XP3:101) detecting described selected input pin (as the XP3:1) correspondence obtained at described detecting unit 131 is low level, determine that the line status of the corresponding bus (No. 1 bus) of described selected input pin is open circuit;
Short-circuit condition determining unit 135, for detect other all output pin except the output pin (as XP3:101) corresponding except described selected input pin (as XP3:1) that obtain at described detecting unit 131 level state in there is high level time, determine level state be output pin (as the XP3:102) correspondence of high level bus (No. 2 buses) with as described in line status between bus (No. 1 bus) corresponding to selected input pin be short circuit.
In addition, input pin can be chosen successively and using the described pin chosen as described selected input pin, to determine the corresponding first line state of bus of each selected input pin and second line status between described corresponding bus and other bus successively according to pin numbering.
In addition, said apparatus also comprises: the connectivity port exchanging bus backplane, by the input end of described bus backplane as output terminal, and using the output terminal of described bus backplane as input end, retest according to the method described above, finally determine the corresponding first line state of bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of output pins all in described signal port.
Content for a more clear understanding of the present invention, illustrate below, line fault pattern diagram shown in Parameter Map 4, three kinds of fault modes are given in this figure, choose two buses in bus backplane, bus between definition port one and port one 01 is No. 1 bus, same, bus between definition port 2 and port one 02 is No. 2 buses, at the signal port input pin XP3:1 applying high level signal that No. 1 bus is corresponding, and signal port input pin XP3:2 corresponding for No. 2 buses is placed in high-impedance state, below just following three kinds of fault modes be described:
See first kind fault mode, using port one and 2 as input end, during using port one 01 and 102 as output terminal, when No. 1 bus near input end 1 place occur open circuit (open circuit point 1) and No. 1 bus and No. 2 bus short circuits, the equal output low level signal of output pin of output terminal 101 and output terminal 102 correspondence, now only can judge No. 1 bus open circuit, but but can not judge whether occurred short circuit between No. 1 bus and No. 2 buses.Take to test in the other direction, by port one 01 and 102 as input end, simultaneously using port one and 2 as output terminal, now, output terminal 1 corresponding output pin output low level signal but the corresponding output pin of output terminal 2 exports high level signal, now not only can judge No. 1 bus open circuit, No. 1 bus and No. 2 bus short circuits (namely there is open circuit point 1) can also be judged.
See Equations of The Second Kind fault mode, using port one and 2 as input end, during using port one 01 and 102 as output terminal, when No. 1 bus near output terminal 101 place occur open circuit (open circuit point 2) and No. 1 bus and No. 2 bus short circuits, output terminal 101 corresponding output pin output low level signal but the corresponding output pin of output terminal 102 exports high level signal, now can judge No. 1 bus open circuit and No. 1 bus and No. 2 bus short circuits (namely there is open circuit point 2).Take to test in the other direction, just can not judge whether occurred short circuit between No. 1 bus and No. 2 buses.
See the 3rd class fault mode, using port one and 2 as input end, during using port one 01 and 102 as output terminal, when No. 1 bus near input end 1 place occur open circuit (open circuit point 1), near output terminal 101 place occur open circuit (open circuit point 2) and No. 1 bus and No. 2 bus short circuits, output terminal 101 and output terminal 102 all output low level signals, now only can judge No. 1 bus open circuit; If but after taking above-mentioned opposite direction to test, as port one and 2 also equal output low level signal of output terminal, be to judge short-circuit condition between No. 1 bus and No. 2 buses all the time in this case.
Certainly, but the present invention includes and be not limited only to above-mentioned three class fault modes, the fault mode of other derivative class is content of the present invention.
Based on above-mentioned fault mode, method of the present invention can be adopted to carry out first round test to the every bar bus in bus backplane successively, can judge to learn in all circuits, open circuit has appearred in which circuit by said method, but but all may not judge the short trouble (such as the 3rd class fault mode) between circuit, therefore, the first round test after can to obtain to faulty line repair, and then carry out second according to method provided by the invention, third round is tested, in order to get rid of one by one line fault, all trouble spots can be repaired the most at last.
Pin status shown in Figure 5 and line status table, for convenience of description, only provide the test result of No. 1 pin herein, analyze the situation of 3 buses, equally, No. 2, test, also similar results can be collected when No. 3 pins and other any pin, same analysis can be done, all test result is obtained by with form or other mode for every root bus, finally, comprehensive all test results can judge whole bus backplane, finally show which bar circuit occurs occurring short circuit between which circuit of open circuit, to carry out fault according to this result to reprocess, above-mentioned test is repeated again after reprocessing, repair all trouble spots the most at last.
Parallel bus proving installation of the present invention, by described high level signal to be put on a selected input pin of signal distributor signal port through data collecting card, and is all set to high-impedance state by other all input pin except described selected input pin; Obtain the level state of all output pins of the described signal port that described data collecting card collects; Finally determine whether the corresponding bus of selected pin has occurred open circuit according to the level state of described all output pins, and whether there is short circuit between the corresponding bus of this selected pin and other bus, thus the line status that can obtain between the line status of each bus in bus backplane itself and bus, the present invention accurately, fast, comprehensively can test the situation of parallel bus open circuit, short circuit, and can realize the test of any one bus backplane.
Shown in Figure 6, Fig. 6 is the schematic flow sheet of a kind of parallel bus method of testing provided by the invention, described method is applied to parallel bus proving installation, described proving installation comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, first test port of described signal distributor and the second test port are connected with the input end of bus backplane and output terminal respectively, all current-limiting resistance is in series with between every bar connecting line of described signal port and described first test port, all pull down resistor is in series with between every bar connecting line of described signal port and described second test port and ground wire, described controller realizes the test to parallel bus according to following steps:
Step 601: apply the selected input pin of high level signal in described signal port through described data collecting card, and other all input pin except described selected input pin is all set to high-impedance state;
Step 602: the level state obtaining all output pins of the described signal port that described data collecting card collects;
Step 603: determine the corresponding first line state of bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
Wherein, described first line state is normal or open circuit, and described second line status is normal or short circuit.
Realize step 103 in accordance with the following methods: first, detect the level state of described all output pins; If the level state of the output pin that described selected input pin is corresponding is high level, then determine that the line status of the corresponding bus of described selected input pin is normal; If there is low level in the level state of other all output pin beyond the output pin that described selected input pin is corresponding, then determine that level state be the line status of the bus that low level output pin is corresponding is normal; If the level state of the output pin that described selected input pin is corresponding is low level, then determine that the line status of the corresponding bus of described selected input pin is open circuit; If there is high level in the level state of other all output pin beyond the output pin that described selected input pin is corresponding, then determine that level state be the bus that the output pin of high level is corresponding is short circuit with the line status between the corresponding bus of described selected input pin.
In addition, the corresponding first line state of bus of each selected input pin and the second line status between described corresponding bus and other bus is determined successively according to pin numbering.
In addition, said method also comprises: using the input end of described bus backplane as output terminal, and using the output terminal of described bus backplane as input end, determine the corresponding first line state of bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of output pins all in described signal port.
Connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
Parallel bus method of testing of the present invention, by described high level signal to be put on a selected input pin of signal distributor signal port through data collecting card, and is all set to high-impedance state by other all input pin except described selected input pin; Obtain the level state of all output pins of the described signal port that described data collecting card collects; Finally determine whether the corresponding bus of selected pin has occurred open circuit according to the level state of described all output pins, and whether there is short circuit between the corresponding bus of this selected pin and other bus, thus the line status that can obtain between the line status of each bus in bus backplane itself and bus, the present invention accurately, fast, comprehensively can test the situation of parallel bus open circuit, short circuit, and can realize the test of any one bus backplane.
Also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (4)
1. a parallel bus method of testing, it is characterized in that, described method is applied to parallel bus proving installation, described proving installation comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, first test port of described signal distributor and the second test port are connected with the input end of bus backplane and output terminal respectively, all current-limiting resistance is in series with between every bar connecting line of described signal port and described first test port, all pull down resistor is in series with between every bar connecting line of described signal port and described second test port and ground wire, described controller realizes the test to parallel bus according to following steps:
Apply the selected input pin of high level signal in described signal port through described data collecting card, and other all input pin except described selected input pin is all set to high-impedance state;
Obtain the level state of all output pins of the described signal port that described data collecting card collects;
The corresponding first line state of bus of selected pin and the second line status between described corresponding bus and other bus is determined according to the level state of described all output pins;
Using the input end of described bus backplane as output terminal, and using the output terminal of described bus backplane as input end, determine the corresponding first line state of bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of output pins all in described signal port.
2. method according to claim 1, is characterized in that, the described level state according to described all output pins determines that the corresponding first line state of bus of selected pin and the second line status between described corresponding bus and other bus comprise:
Detect the level state of described all output pins;
If the level state of the output pin that described selected input pin is corresponding is high level, then determine that the line status of the corresponding bus of described selected input pin is normal;
If there is low level in the level state of other all output pin beyond the output pin that described selected input pin is corresponding, then determine that level state be the line status of the bus that low level output pin is corresponding is normal;
If the level state of the output pin that described selected input pin is corresponding is low level, then determine that the line status of the corresponding bus of described selected input pin is open circuit;
If there is high level in the level state of other all output pin beyond the output pin that described selected input pin is corresponding, then determine that level state be the bus that the output pin of high level is corresponding is short circuit with the line status between the corresponding bus of described selected input pin.
3. the method according to any one of claim 1 to 2, is characterized in that, determines the corresponding first line state of bus of each selected input pin and the second line status between described corresponding bus and other bus successively according to pin numbering.
4. method according to claim 3, is characterized in that, the connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
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| CN104038758A (en) * | 2014-06-25 | 2014-09-10 | 深圳市九洲电器有限公司 | HDMI (high-definition multimedia interface) port detecting device and method |
| CN104297619B (en) * | 2014-10-13 | 2017-01-18 | 上海移为通信技术股份有限公司 | Testing device for chip input and output pin |
| CN105866610B (en) * | 2016-04-15 | 2019-11-22 | 中国海洋石油集团有限公司 | Connect the detection device and detection method of bus |
| CN105911459A (en) * | 2016-07-05 | 2016-08-31 | 江苏奥雷光电有限公司 | Method for detecting TO tube insert direction |
| CN107229589B (en) * | 2017-06-21 | 2024-03-12 | 上海景格信息科技有限公司 | TTL communication bus sub-module expansion circuit |
| CN108681497B (en) * | 2018-05-22 | 2022-01-25 | 天津市英贝特航天科技有限公司 | CPCI bus testing device and method |
| CN111948579A (en) * | 2019-04-29 | 2020-11-17 | 深圳市优必选科技有限公司 | Detection method and detection system for terminal connecting wire |
| CN110601801B (en) * | 2019-08-23 | 2021-11-05 | 深圳震有科技股份有限公司 | TDM backplane bus test method, test device and storage medium |
| CN111044879A (en) * | 2019-12-20 | 2020-04-21 | 苏州浪潮智能科技有限公司 | Method and system for quickly positioning fault position of physical interface of main board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201247297Y (en) * | 2008-05-28 | 2009-05-27 | 株洲南车时代电气股份有限公司 | Test device for multi-core cable connecting line |
| CN101458289A (en) * | 2007-12-13 | 2009-06-17 | 鸿富锦精密工业（深圳）有限公司 | Motherboard line detection device |
| CN101666843A (en) * | 2008-09-02 | 2010-03-10 | 杨信明 | Wireless sensing device and system of earthing mechanism for workstation operating personnel |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100487468C (en) * | 2006-06-07 | 2009-05-13 | 华为技术有限公司 | Rear-panel testing system |
| US7884616B2 (en) * | 2008-08-08 | 2011-02-08 | Robert Bosch Gmbh | Automatic multicable electrical continuity tester |
| FR2943435B1 (en) * | 2009-03-17 | 2012-01-27 | Thales Sa | INTEGRATED TEST METHODS OF A LINE. |
| CN101995516A (en) * | 2010-03-31 | 2011-03-30 | 中国商用飞机有限责任公司 | Method for testing integrity of wiring harness |
| KR101016770B1 (en) * | 2010-06-18 | 2011-02-25 | (주)케이디티 | A modular system for integrating sensors and meters using the parallel data bus |
| CN102156237B (en) * | 2011-03-08 | 2014-10-29 | 江苏大学 | Method for detecting automotive harnesses |
-
2012
- 2012-11-12 CN CN201210451366.1A patent/CN102901905B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101458289A (en) * | 2007-12-13 | 2009-06-17 | 鸿富锦精密工业（深圳）有限公司 | Motherboard line detection device |
| CN201247297Y (en) * | 2008-05-28 | 2009-05-27 | 株洲南车时代电气股份有限公司 | Test device for multi-core cable connecting line |
| CN101666843A (en) * | 2008-09-02 | 2010-03-10 | 杨信明 | Wireless sensing device and system of earthing mechanism for workstation operating personnel |
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