CN203165902U - High-efficiency high-withstand voltage Schottky chip - Google Patents
High-efficiency high-withstand voltage Schottky chip Download PDFInfo
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- CN203165902U CN203165902U CN 201220732275 CN201220732275U CN203165902U CN 203165902 U CN203165902 U CN 203165902U CN 201220732275 CN201220732275 CN 201220732275 CN 201220732275 U CN201220732275 U CN 201220732275U CN 203165902 U CN203165902 U CN 203165902U
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- groove
- withstand voltage
- schottky
- grooves
- schottky chip
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Abstract
The utility model relates to a high-efficiency high-withstand voltage Schottky chip and belongs to the semiconductor device manufacturing technical field. The high-efficiency high-withstand voltage Schottky chip includes a top metal layer (1), a Schottky interface (5) below the top metal layer (1), polycrystalline silicon (2) abutting against the lower surface of the Schottky interface (5), first grooves (3) at the peripheries of the polycrystalline silicon, an N-type epitaxial layer (N-EPI) (6) and an N-type substrate (7) at a lower portion. The high-efficiency high-withstand voltage Schottky chip is characterized in that second grooves (4) are arranged between adjacent first grooves (3); and the thickness of the bottoms of the first grooves (3) is greater than the thickness of the side portions of the first grooves (3). Compared with the prior art, the high-efficiency high-withstand voltage Schottky chip has the following advantages that: power-on efficiency of the Schottky chip can be improved; forward voltage drop can be decreased; original backward voltage requirements can be satisfied; and forward voltage drop (VF) can be decreased when forward current is conducted.
Description
Technical field
A kind of high efficiency, high withstand voltage Schottky chip belong to the semiconductor device processing technology field.Be specifically related to a kind of novel efficient Schottky diode Schottky.
Background technology
Tradition N passage Schottky chip schottky interface below is polysilicon, the periphery ditching groove of polysilicon, because have only the consistency of thickness of a kind of groove and groove silica, as shown in Figure 2, the local electric power that takes place easily at the channel bottom bent angle punctures, this kind Schottky chip is oppositely withstand voltage lower, and schottky interface is little by the electric current area, and energising efficient is low.
Summary of the invention
The technical problems to be solved in the utility model is: overcome the deficiencies in the prior art, a kind of energising efficient that can improve the Schottky chip is provided, reduce forward voltage drop, and improve oppositely withstand voltage a kind of high efficiency, high withstand voltage Schottky chip.
The technical scheme that its technical problem that solves the utility model adopts is: this a kind of high efficiency, high withstand voltage Schottky chip, the schottky interface, the polysilicon near the schottky interface below, first groove of polysilicon periphery, N-type epitaxial loayer N-EPI and the N-type substrate of bottom that comprise metal layer at top, metal layer at top below, it is characterized in that: set up second groove between two adjacent first grooves, the bottom thickness of first groove is greater than limit portion thickness.
Described second groove is a plurality of, arranges one between per two first grooves.
The degree of depth of described second groove is lower than the degree of depth of first groove.
The bottom thickness of described first groove is 2-5 times of limit portion thickness.
Compared with prior art, the beneficial effect of high efficiency of the present utility model, high withstand voltage Schottky chip is:
1, in the middle of two first grooves of existing Schottky chip, increases by second groove, schottky interface is increased under the Schottky chip area that equates, the ability of forward conduction electric current is strengthened, the pressure drop VF value when reducing the forward energising, thus promote the efficient 15-30% that forward is switched on.Depth ratio first groove of second groove is shallow in addition, and the vague and general function of the MOS of first groove can be protected the schottky interface of second groove during reverse voltage, thereby reduces the loss of reverse leakage current;
2, the silicon oxide layer of first channel bottom is thicker, thickeies 2-3 doubly than the silicon oxide layer of limit portion groove, prevents that effectively the place of the first channel bottom bent angle from the electric power puncture taking place, and product is oppositely withstand voltage can to improve 15-30%.And the pressure drop VF in the time of can keeping original reverse voltage requirement to reduce the conduct positive electric current.
Description of drawings
Fig. 1 is high efficiency, high withstand voltage Schottky chip structure schematic diagram.
Fig. 2 is prior art Schottky chip structure schematic diagram.
Wherein: 1, metal layer at top 2, polysilicon 3, first groove 4, second groove 5, schottky interface 6, N-type epitaxial loayer N-EPI 7, N-type substrate.
Embodiment
Be described further below in conjunction with 1 pair of the utility model high efficiency of accompanying drawing, high withstand voltage Schottky chip.
This a kind of high efficiency, high withstand voltage Schottky chip are by metal layer at top 1, polysilicon 2, first groove 3, second groove 4, schottky interface 5, N-type epitaxial loayer N-EPI 6 and N-type substrate N
+Substrate 7 forms.Be followed successively by from the bottom up: N-type substrate N
+Substrate 7, N-type epitaxial loayer N-EPI 6, first groove 3, polysilicon 2, second groove 4, schottky interface 5 and metal layer at top 1.
Polysilicon 2 abut against schottky interface 5 the below, dig out first groove 3, between two adjacent first grooves 3, dig out the bottom thickness of second groove, 4, the first grooves 3 greater than limit portion thickness in both sides and the bottom of polysilicon.
Described second groove 4 is square groove, and is a plurality of, arranges one between per two first grooves 3.
The degree of depth of described second groove 4 is lower than the degree of depth of first groove 3.
The bottom thickness of described first groove 3 is 2-5 times of limit portion thickness.
Be 2 times of limit portion ditch slot thickness as undercut thickness, product is oppositely withstand voltage can to improve 15%;
Undercut thickness is 3 times of limit portion ditch slot thickness, and product is oppositely withstand voltage can to improve 20%;
Undercut thickness is 5 times of limit portion ditch slot thickness, and product is oppositely withstand voltage can to improve 30%.
In prior art Schottky crystal grain is made, in the middle of two first grooves 3 that polysilicon 2 peripheries are dug, dig second groove 4 again, the surface of second groove 4 forms extra schottky interface, just the shape of schottky interface is made plane and groove shape separately, therefore schottky interface 5 is increased in the Schottky chip area that equates, the ability of forward conduction electric current is strengthened, the pressure drop VF value when reducing the forward energising, thus promote the efficient 15-30% that forward is switched on.Depth ratio first groove 3 of second groove 4 is shallow in addition, and the vague and general function of the MOS of first groove 3 can be protected the schottky interface of second groove 4 during reverse voltage, thereby reduces the loss of reverse leakage current.
This high efficiency, high withstand voltage Schottky chip make the thickening of Schottky chip silicon oxide layer bottom electric field be discongested at reverse voltage, so oppositely withstand voltagely can improve 15-30%.And can keep original reverse voltage requirement, thereby the pressure drop VF when but the doping content that improves the N-EPI extension reduces the conduct positive electric current, thus the efficient of forward conduction promoted.Solved the local low problem of reverse voltage that causes that punctures easily of Schottky chip first groove 3 bottom bent angles.
The above, it only is preferred embodiment of the present utility model, be not to be the restriction of the utility model being made other form, any those skilled in the art may utilize the technology contents of above-mentioned announcement to be changed or be modified as the equivalent embodiment of equivalent variations.But every technical solutions of the utility model content that do not break away to any simple modification, equivalent variations and remodeling that above embodiment does, still belongs to the protection range of technical solutions of the utility model according to technical spirit of the present utility model.
Claims (4)
1. a high efficiency, high withstand voltage Schottky chip, the schottky interface (5), the polysilicon (2) near schottky interface (5) below, first groove (3) of polysilicon periphery, the N-type epitaxial loayer N-EPI(6 of bottom that comprise metal layer at top (1), metal layer at top (1) below) and N-type substrate (7), it is characterized in that: set up second groove (4) between two adjacent first grooves (3), the bottom thickness of first groove (3) is greater than limit portion thickness.
2. a kind of high efficiency according to claim 1, high withstand voltage Schottky chip is characterized in that: described second groove (4) arranges one for a plurality of between per two first grooves (3).
3. a kind of high efficiency according to claim 1 and 2, high withstand voltage Schottky chip, it is characterized in that: the degree of depth of described second groove (4) is lower than the degree of depth of first groove (3).
4. a kind of high efficiency according to claim 3, high withstand voltage Schottky chip is characterized in that: the bottom thickness of described first groove (3) be limit portion thickness 2-5 doubly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220732275 CN203165902U (en) | 2012-12-27 | 2012-12-27 | High-efficiency high-withstand voltage Schottky chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220732275 CN203165902U (en) | 2012-12-27 | 2012-12-27 | High-efficiency high-withstand voltage Schottky chip |
Publications (1)
| Publication Number | Publication Date |
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| CN203165902U true CN203165902U (en) | 2013-08-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220732275 Expired - Fee Related CN203165902U (en) | 2012-12-27 | 2012-12-27 | High-efficiency high-withstand voltage Schottky chip |
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| Country | Link |
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| CN (1) | CN203165902U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022090A (en) * | 2012-12-27 | 2013-04-03 | 淄博美林电子有限公司 | High-efficiency high-voltage-resistant Schottky chip |
| CN107046065A (en) * | 2017-04-06 | 2017-08-15 | 淄博汉林半导体有限公司 | The vertical field-effect diode and manufacture method of a kind of built-in schottky interface |
-
2012
- 2012-12-27 CN CN 201220732275 patent/CN203165902U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022090A (en) * | 2012-12-27 | 2013-04-03 | 淄博美林电子有限公司 | High-efficiency high-voltage-resistant Schottky chip |
| CN107046065A (en) * | 2017-04-06 | 2017-08-15 | 淄博汉林半导体有限公司 | The vertical field-effect diode and manufacture method of a kind of built-in schottky interface |
| CN107046065B (en) * | 2017-04-06 | 2023-12-01 | 淄博汉林半导体有限公司 | Manufacturing method of vertical field effect diode with built-in Schottky interface |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130828 Termination date: 20161227 |
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| CF01 | Termination of patent right due to non-payment of annual fee |