CN203118940U - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN203118940U CN203118940U CN 201220713058 CN201220713058U CN203118940U CN 203118940 U CN203118940 U CN 203118940U CN 201220713058 CN201220713058 CN 201220713058 CN 201220713058 U CN201220713058 U CN 201220713058U CN 203118940 U CN203118940 U CN 203118940U
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- Prior art keywords
- lower metal
- layer
- those
- projection lower
- semiconductor structure
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- Expired - Lifetime
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000010410 layer Substances 0.000 claims abstract description 121
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 239000011241 protective layer Substances 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims description 65
- 239000011248 coating agent Substances 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000000203 mixture Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 8
- CPFNXHQBAHTVKB-UHFFFAOYSA-N [Ti].[Cu].[W] Chemical compound [Ti].[Cu].[W] CPFNXHQBAHTVKB-UHFFFAOYSA-N 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 claims description 7
- -1 polyparaphenylene Polymers 0.000 claims description 6
- 229920000265 Polyparaphenylene Polymers 0.000 claims description 4
- 150000003851 azoles Chemical class 0.000 claims description 4
- 125000005605 benzo group Chemical group 0.000 claims description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 4
- 150000003376 silicon Chemical class 0.000 abstract description 4
- 238000005253 cladding Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 150000001398 aluminium Chemical class 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 125000001140 1,4-phenylene group Chemical group [H]C1=C([H])C([*:2])=C([H])C([H])=C1[*:1] 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model relates to a semiconductor structure, it contains silicon substrate, a plurality of first lug lower metal layer, a plurality of first buffer layers, supporting layer and a plurality of connection portion, this silicon substrate has a plurality of connection pads and protective layer, these a little first lug lower metal layer covers this protective layer and these a little connection pads, each this first lug lower metal layer has first rampart, each this first buffer layer is formed on each this first lug lower metal layer respectively, each this first buffer layer has the joint portion, embedding portion and second rampart, this supporting layer is formed at this protective layer, on these a little first lug lower metal layer and these a little first buffer layers, each this first rampart of this supporting layer cladding, each this second rampart and each this embedding portion, each this connection portion covers each this joint portion.
Description
Technical field
The utility model relates to a kind of semiconductor structure, particularly relates to a kind of semiconductor structure of strengthening structural strength.
Background technology
As shown in Figure 1; existing known semiconductor structure 200 includes silicon substrate 210, projection lower metal layer 220 and soldered ball 230; this silicon substrate 210 has aluminium pad 211 and protective layer 212, and this projection lower metal layer 220 electrically connects this aluminium pad 211 and this soldered ball 230 is formed on this projection lower metal layer 220.When this semiconductor structure 200 carries out the thrust test, because this soldered ball 230, this projection lower metal layer 220 are different with the material of this aluminium pad 211, therefore can there be tangible combination interface and forms structural strength most fragile part, cause this projection lower metal layer 220 to peel off even damage this aluminium pad 211 by this aluminium pad 211 easily and make these semiconductor structure 200 yields descend.
Because the defective that above-mentioned conventional semiconductor structure exists, the inventor is based on being engaged in practical experience and the professional knowledge that this type of product design manufacturing is enriched for many years, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of semiconductor structure of new structure, can improve general conventional semiconductor structure, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the utility model that has practical value finally.
Summary of the invention
The purpose of this utility model is, overcomes the defective that the conventional semiconductor structure exists, and a kind of novel semiconductor structure is provided, and technical problem to be solved is to strengthen its structural strength, thereby is suitable for practicality more.
The purpose of this utility model and to solve its technical problem be to adopt following technical scheme to realize.According to the semiconductor structure that the utility model proposes, it comprises at least: silicon substrate, it has surface, a plurality of connection pad and protective layer, those connection pads are formed on this surface, this protective layer is formed on this surface and covers those connection pads, this protective layer has a plurality of first openings, and respectively this first opening appears respectively this connection pad respectively; A plurality of first projection lower metal layers, it covers this protective layer and those connection pads, and respectively this first projection lower metal layer has first ring wall; A plurality of first resilient coatings, it is formed at respectively this first projection lower metal layer respectively, and respectively this first resilient coating has junction surface, embedding portion and second ring wall; Supporting layer, it is formed on this protective layer, those first projection lower metal layers and those first resilient coatings, this supporting layer have a plurality of second openings and respectively this second opening appear respectively this junction surface of this first resilient coating respectively, this supporting layer coats this first ring wall of this first projection lower metal layer respectively, respectively this second ring wall and this embedding portion of this first resilient coating; And a plurality of junctions, it is formed at respectively this second opening respectively and covers respectively this junction surface of this first resilient coating.
The purpose of this utility model and solve its technical problem and can also be further achieved by the following technical measures.
Aforesaid semiconductor structure, wherein respectively this junction includes the second projection lower metal layer, second resilient coating and solder layer, respectively this second projection lower metal layer is formed at respectively in this second opening, and cover respectively this junction surface of this first resilient coating, respectively this second resilient coating covers respectively this second projection lower metal layer, and respectively this solder layer covers respectively this second resilient coating.
Aforesaid semiconductor structure, wherein this supporting layer has end face, and those second projection lower metal layers cover this end face.
Aforesaid semiconductor structure, wherein the material of those first projection lower metal layers be selected from CTB alloy or titanium tungsten-copper alloy one of them.
Aforesaid semiconductor structure, wherein the material of this supporting layer is selected from polyimides (Polyimide, PI), polyparaphenylene's benzo two uh azoles (Poly-p-phenylene benzo-bi soxazazole, PBO) or benzocyclobutene (Benezocy-clobutene, BCB) one of them.
Aforesaid semiconductor structure, wherein the material of those second projection lower metal layers be selected from CTB alloy or titanium tungsten-copper alloy one of them.
Aforesaid semiconductor structure, wherein the material of those first resilient coatings be selected from copper or nickel wherein it
Aforesaid semiconductor structure, wherein the material of those second resilient coatings be selected from copper, nickel or corronil one of them.
Aforesaid semiconductor structure, wherein respectively this junction surface of this first resilient coating has the composition surface, and respectively this second projection lower metal layer has the butt limit, and this butt edge joint touches this composition surface.
The utility model compared with prior art has tangible advantage and beneficial effect.By technique scheme, the utility model semiconductor structure can reach suitable technological progress and practicality, and has an extensive value on the industry, it has following advantage at least: when this semiconductor structure carries out thrust test, can prevent that this first projection lower metal layer from peeling off or damaging this connection pad by this connection pad, thereby improve the yield of this semiconductor structure.
Above-mentioned explanation only is the general introduction of technical solutions of the utility model, for can clearer understanding technological means of the present utility model, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1: existing known semiconductor structure schematic diagram.
Fig. 2: according to a preferred embodiment of the present utility model, a kind of flow chart of semiconductor fabrication process.
Fig. 3 A to Fig. 3 I: according to a preferred embodiment of the present utility model, the schematic cross-section of this semiconductor fabrication process.
Fig. 4: according to a preferred embodiment of the present utility model, a kind of flow chart of junction manufacturing process.
Fig. 5 A to Fig. 5 E: according to a preferred embodiment of the present utility model, the schematic cross-section of this junction manufacturing process.
[main element symbol description]
10: silicon substrate is provided
11: form first Seed Layer
12: form first photoresist layer
13: form first resilient coating
14: remove this first photoresist layer
15: remove this first Seed Layer
16: form supporting layer
17: form junction
20: form second Seed Layer
21: form second photoresist layer
22: form this second resilient coating
23: form this solder layer
24: remove this second photoresist layer
25: remove this second Seed Layer
100: semiconductor structure
110: silicon substrate 111: surface
112: connection pad 113: protective layer
113a: first opening
121: the first ring walls of 120: the first projection lower metal layers
120 ': the first Seed Layer, 120 ' a: first section
120 ': 130: the first resilient coatings of b second section
131: junction surface 131a: composition surface
132: 133: the second ring walls of embedding portion
140: 141: the second openings of supporting layer
142: end face
150: 151: the second projection lower metal layers of junction
151a: butt limit 151 ': the second Seed Layer
151 ' a: the 3rd section 151 ' b: the 4th section
153a: arcuation surface
200: semiconductor structure
210: silicon substrate 211: the aluminium pad
212: protective layer 220: the projection lower metal layer
230: soldered ball
O1: the first fluting O2: second fluting
P1: the first photoresist layer P2: second photoresist layer
Embodiment
Be to reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the utility model, below in conjunction with accompanying drawing and preferred embodiment, to according to its embodiment of semiconductor structure, structure, feature and the effect thereof that the utility model proposes, describe in detail as after.
See also Fig. 2 and Fig. 3 A to Fig. 3 I, it is a preferred embodiment of the present utility model, a kind of semiconductor fabrication process comprises the following step: at first, see also step 10 and Fig. 3 A of Fig. 2, silicon substrate 110 is provided, this silicon substrate 110 has surface 111, a plurality of connection pad 112 and protective layer 113, those connection pads 112 are formed on this surface 111, this protective layer 113 is formed on this surface 111 and covers those connection pads 112, this protective layer 113 has a plurality of first opening 113a, and respectively this first opening 113a appears respectively this connection pad 112 respectively; Then, see also step 11 and Fig. 3 B of Fig. 2, form first Seed Layer 120 ' on this protective layer 113 and those connection pads 112, this first Seed Layer 120 ' has a plurality of first section, 120 ' a and a plurality of second section, 120 ' b that is positioned at this first section 120 ' a outside, the material of this first Seed Layer 120 ' be selected from CTB alloy or titanium tungsten-copper alloy one of them; Afterwards, see also step 12 and Fig. 3 C of Fig. 2, form the first photoresist layer P1 on this first Seed Layer 120 ', this first photoresist layer P1 is formed with a plurality of first fluting O1 to appear those first sections 120 ' a; Then, see also step 13 and Fig. 3 D of Fig. 2, form a plurality of first resilient coatings 130 in those first flutings O1, respectively this first resilient coating 130 covers respectively this first section 120 ' a of this first Seed Layer 120 ', and respectively this first resilient coating 130 has junction surface 131 and embedding portion 132, the material of those first resilient coatings 130 be selected from copper or nickel one of them; Afterwards, see also step 14 and Fig. 3 E of Fig. 2, remove this first photoresist layer P1 to appear those second sections 120 ' b of this first Seed Layer 120 '; Then, see also step 15 and Fig. 3 F of Fig. 2, remove those second sections 120 ' b of this first Seed Layer 120 ' so that those first sections 120 ' a forms a plurality of first projection lower metal layers 120; Afterwards, see also step 16 and Fig. 3 G of Fig. 2, form supporting layer 140 on this protective layer 113 and those first resilient coatings 130, this supporting layer 140 have a plurality of second openings 141 and respectively this second opening 141 be to appear respectively this junction surface 131 of this first resilient coating 130 respectively, wherein respectively this first projection lower metal layer 120 has first ring wall 121, respectively this first resilient coating 130 has second ring wall 133, this supporting layer 140 coats respectively this first ring wall 121 of this first projection lower metal layer 120, respectively this second ring wall 133 of this first resilient coating 130 and this embedding portion 132, the material of this supporting layer 140 is selected from polyimides (Polyimide, PI), polyparaphenylene's benzo two uh azoles (Poly-p-phenylene benzo-bisoxazazole, PBO) or benzocyclobutene (Benezocy-clobutene, BCB) one of them; Then, see also step 17 and Fig. 3 H of Fig. 2, form a plurality of junctions 150 in those second openings 141 and cover respectively this junction surface 131 of this first resilient coating 130, preferably, in the present embodiment, respectively this junction 150 includes the second projection lower metal layer 151, second resilient coating 152 and solder layer 153, respectively this second projection lower metal layer 151 covers respectively this junction surface 131 of this first resilient coating 130, and this supporting layer 140 has end face 142, those second projection lower metal layers 151 cover this end face 142, in the present embodiment, respectively this second projection lower metal layer 151 has butt limit 151a, respectively this junction surface 131 of this first resilient coating 130 has composition surface 131a, this butt limit 151a contacts this composition surface 131a, respectively this second resilient coating 152 covers respectively this second projection lower metal layer 151, and respectively this solder layer 153 covers respectively this second resilient coating 152.
In addition, see also Fig. 4 and Fig. 5 A to Fig. 5 E, in the present embodiment, the manufacturing process that forms those junctions 150 comprises the following step: at first, see also step 20 and Fig. 5 A of Fig. 4, form second Seed Layer 151 ' on this supporting layer 140 and cover those first resilient coatings 130, this second Seed Layer 151 ' has a plurality of the 3rd section 151 ' a and a plurality of the 4th section 151 ' b that is positioned at the 3rd section 151 ' a outside, the material of this second Seed Layer 151 ' be selected from CTB alloy or titanium tungsten-copper alloy one of them; Then, see also step 21 and Fig. 5 B of Fig. 4, form the second photoresist layer P2 on this second Seed Layer 151 ', this second photoresist layer P2 is formed with a plurality of second fluting O2 to appear those the 3rd sections 151 ' a; Afterwards, see also step 22 and Fig. 5 C of Fig. 4, form those second resilient coatings 152 in those second flutings O2, respectively this second resilient coating 152 covers respectively the 3rd section 151 ' a of these second Seed Layer 151 ', the material of those second resilient coatings 152 be selected from copper, nickel or corronil one of them; Then, see also step 23 and Fig. 5 D of Fig. 4, form respectively this solder layer 153 on this second resilient coating 152 respectively; Afterwards, see also step 24 and Fig. 5 E of Fig. 4, remove this second photoresist layer P2 to appear those the 4th sections 151 ' b of this second Seed Layer 151 '; Then, see also step 25 and Fig. 3 H of Fig. 4, remove those the 4th sections 151 ' b of this second Seed Layer 151 ' so that those the 3rd sections 151 ' a forms those second projection lower metal layers 151, and form semiconductor structure 100; At last, see also Fig. 3 I, those solder layers 153 of reflow so that respectively this solder layer 153 be formed with arcuation surface 153a.Because this supporting layer 140 of this semiconductor structure 100 coats respectively this first ring wall 121 of this first projection lower metal layer 120, respectively this second ring wall 133 of this first resilient coating 130 and this embedding portion 132, and respectively this first resilient coating 130 covers respectively this first projection lower metal layer 120, respectively this butt limit 151a of this second projection lower metal layer 151 contacts respectively this composition surface 131a at this junction surface 131, when therefore this semiconductor structure 100 carries out thrust test, can prevent that those first projection lower metal layers 120 from peeling off or damaging those connection pads 112 by those connection pads 112, thereby improve the yield of this semiconductor structure 100.
Please consult Fig. 3 H again; it is a kind of semiconductor structure 100 of the present utility model; it includes silicon substrate 110 at least; a plurality of first projection lower metal layers 120; a plurality of first resilient coatings 130; supporting layer 140 and a plurality of junction 150; this silicon substrate 110 has surface 111; a plurality of connection pads 112 and protective layer 113; those connection pads 112 are formed on this surface 111; this protective layer 113 is formed on this surface 111 and covers those connection pads 112; this protective layer 113 has a plurality of first opening 113a; respectively this first opening 113a appears respectively this connection pad 112; respectively this first projection lower metal layer 120 covers this protective layer 113 and reaches respectively this connection pad 112; the material of those first projection lower metal layers 120 be selected from CTB alloy or titanium tungsten-copper alloy one of them; respectively this first projection lower metal layer 120 has first ring wall 121; respectively this first resilient coating 130 is formed at respectively on this first projection lower metal layer 120; the material of those first resilient coatings 130 be selected from copper or nickel one of them; respectively this first resilient coating 130 has junction surface 131; embedding portion 132 and second ring wall 133; this supporting layer 140 is formed at this protective layer 113; on those first projection lower metal layers 120 and those first resilient coatings 130; the material of this supporting layer 140 is selected from polyimides (Polyimide; PI); polyparaphenylene's benzo two uh azoles (Poly-p-phenylene benzo-bisoxazazole; PBO) or benzocyclobutene (Benezocy-clobutene; BCB) one of them; this supporting layer 140 has a plurality of second openings 141 and end face 142; and respectively this second opening 141 appears respectively this junction surface 131 of this first resilient coating 130; this supporting layer 140 coats respectively this first ring wall 121 of this first projection lower metal layer 120; respectively this second ring wall 133 of this first resilient coating 130 and this embedding portion 132; respectively this junction 150 is formed at respectively this second opening 141 and covers respectively this junction surface 131 of this first resilient coating 130; in the present embodiment; respectively this junction 150 includes the second projection lower metal layer 151; second resilient coating 152 and solder layer 153; respectively this second projection lower metal layer 151 is formed at respectively this second opening 141; and cover respectively this junction surface 131 of this first resilient coating 130; the material of those second projection lower metal layers 151 be selected from CTB alloy or titanium tungsten-copper alloy one of them; respectively this second resilient coating 152 covers respectively this second projection lower metal layer 151; the material of those second resilient coatings 152 is selected from copper; nickel or corronil one of them; respectively this solder layer 153 is respectively this second resilient coating 152 of covering, and those second projection lower metal layers 151 cover this end face 142 of this supporting layer 140.Preferably, in the present embodiment, respectively this junction surface 131 of this first resilient coating 130 has composition surface 131a, and respectively this second projection lower metal layer 151 has butt limit 151a, and this butt limit 151a contacts this composition surface 131a.
The above, it only is preferred embodiment of the present utility model, be not that the utility model is done any pro forma restriction, though the utility model discloses as above with preferred embodiment, yet be not in order to limit the utility model, any those skilled in the art, in not breaking away from the technical solutions of the utility model scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solutions of the utility model, any simple modification that foundation technical spirit of the present utility model is done above embodiment, equivalent variations and modification all still belong in the scope of technical solutions of the utility model.
Claims (9)
1. semiconductor structure is characterized in that it comprises at least:
Silicon substrate, it has surface, a plurality of connection pad and protective layer, and those connection pads are formed on this surface, and this protective layer is formed on this surface and covers those connection pads, and this protective layer has a plurality of first openings, and respectively this first opening appears respectively this connection pad respectively;
A plurality of first projection lower metal layers, it covers this protective layer and those connection pads, and respectively this first projection lower metal layer has first ring wall;
A plurality of first resilient coatings, it is formed at respectively this first projection lower metal layer respectively, and respectively this first resilient coating has junction surface, embedding portion and second ring wall;
Supporting layer, it is formed on this protective layer, those first projection lower metal layers and those first resilient coatings, this supporting layer have a plurality of second openings and respectively this second opening appear respectively this junction surface of this first resilient coating respectively, this supporting layer coats this first ring wall of this first projection lower metal layer respectively, respectively this second ring wall and this embedding portion of this first resilient coating; And
A plurality of junctions, it is formed at respectively this second opening respectively and covers respectively this junction surface of this first resilient coating.
2. semiconductor structure according to claim 1, it is characterized in that respectively this junction includes the second projection lower metal layer, second resilient coating and solder layer, respectively this second projection lower metal layer is formed at respectively in this second opening, and cover respectively this junction surface of this first resilient coating, respectively this second resilient coating covers respectively this second projection lower metal layer, and respectively this solder layer covers respectively this second resilient coating.
3. semiconductor structure according to claim 2 is characterized in that this supporting layer has end face, and those second projection lower metal layers cover this end face.
4. semiconductor structure according to claim 1, the material that it is characterized in that those first projection lower metal layers be selected from CTB alloy or titanium tungsten-copper alloy one of them.
5. semiconductor structure according to claim 1, the material that it is characterized in that this supporting layer be selected from polyimides, polyparaphenylene's benzo two uh azoles or benzocyclobutene one of them.
6. semiconductor structure according to claim 2, the material that it is characterized in that those second projection lower metal layers be selected from CTB alloy or titanium tungsten-copper alloy one of them.
7. semiconductor structure according to claim 1, the material that it is characterized in that those first resilient coatings be selected from copper or nickel one of them.
8. semiconductor structure according to claim 2, the material that it is characterized in that those second resilient coatings be selected from copper, nickel or corronil one of them.
9. semiconductor structure according to claim 2 is characterized in that respectively this junction surface of this first resilient coating has the composition surface, and respectively this second projection lower metal layer has the butt limit, and this butt edge joint touches this composition surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101223917U TWM453582U (en) | 2012-12-10 | 2012-12-10 | Semiconductor structure |
| TW101223917 | 2012-12-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203118940U true CN203118940U (en) | 2013-08-07 |
Family
ID=48899259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220713058 Expired - Lifetime CN203118940U (en) | 2012-12-10 | 2012-12-20 | Semiconductor structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN203118940U (en) |
| TW (1) | TWM453582U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508919A (en) * | 2019-01-31 | 2020-08-07 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN112864021A (en) * | 2019-11-27 | 2021-05-28 | 南茂科技股份有限公司 | Conductive bump and method for making the same |
-
2012
- 2012-12-10 TW TW101223917U patent/TWM453582U/en not_active IP Right Cessation
- 2012-12-20 CN CN 201220713058 patent/CN203118940U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508919A (en) * | 2019-01-31 | 2020-08-07 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| US11476212B2 (en) | 2019-01-31 | 2022-10-18 | United Microelectronics Corporation | Semiconductor contact structure having stress buffer layer formed between under bump metal layer and copper pillar |
| CN112864021A (en) * | 2019-11-27 | 2021-05-28 | 南茂科技股份有限公司 | Conductive bump and method for making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM453582U (en) | 2013-05-21 |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130807 |
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| CX01 | Expiry of patent term |