CN103367298A - Semiconductor packaging structure and packaging method thereof - Google Patents
Semiconductor packaging structure and packaging method thereof Download PDFInfo
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- CN103367298A CN103367298A CN2012101007085A CN201210100708A CN103367298A CN 103367298 A CN103367298 A CN 103367298A CN 2012101007085 A CN2012101007085 A CN 2012101007085A CN 201210100708 A CN201210100708 A CN 201210100708A CN 103367298 A CN103367298 A CN 103367298A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention relates to a semiconductor packaging structure which comprises a first substrate, a second substrate and sealing glue. The first substrate is provided with multiple first protrusion blocks and multiple first solder layers. Each of first solder layers is formed on each of the first protrusion blocks and is provided with a conical groove. The conical groove is provided with an inner side wall. The second substrate is provided with multiple second protrusion blocks and multiple second solder layers. Each of second solder layers is formed on each of the second protrusion blocks and is a conical shape body which is provided with an external annular wall. Each of second solder layers is combined with each of the first solder layers and is accommodated in each of the first solder layers. The inner side wall of each conical groove contacts the external annular wall of each of second solder layers. Said sealing glue is formed between the first substrate and the second substrate.
Description
Technical field
The invention relates to a kind of semiconductor package, particularly relevant for a kind of semiconductor package that can thinning.
Background technology
Because environmental consciousness comes back at present; so the pollution level that semiconductor technology causes also receives everybody concern; in order to reduce the produced pollution in the technique; therefore adopt the pb-free solder projection; yet; the pb-free solder projection is but too crisp and easily produce the crack; and the coefficient of thermal expansion mismatch between chip and base plate for packaging will produce stress; and stress also impacts for the reliability of the Lead-free in Electronic Packaging system that uses the pb-free solder projection; and the underfill that uses at present also can't provide enough protections to the pb-free solder projection, and then causes the reliability of product to reduce.
This shows, above-mentioned existing semiconductor technology obviously still has inconvenience and defective, and demands urgently further being improved in product structure, manufacture method and use.Therefore how to found a kind of new semiconductor package and method for packing thereof, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing semiconductor technology exists, the inventor is based on being engaged in for many years abundant practical experience and professional knowledge of this type of product design manufacturing, and the utilization of cooperation scientific principle, positive research and innovation in addition, to founding a kind of new semiconductor package and method for packing thereof, can improve general existing semiconductor technology, make it have more practicality.Through constantly research, design, and through after repeatedly studying sample and improvement, finally create the present invention who has practical value.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing semiconductor technology exists, and provide a kind of new semiconductor package and method for packing thereof, technical problem to be solved be make its by this first solder layer respectively be formed at respectively on this first projection and respectively this first solder layer have this taper groove, respectively this second solder layer be formed at respectively on this second projection and respectively this second solder layer be a cone, therefore this first substrate can directly dock with this second substrate and storehouse and docking formed spacing and thickness are less afterwards, so that this semiconductor package has contaminative is low, high and the effect of saving cost of reliability is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor package according to the present invention's proposition, wherein comprise at least: a first substrate, it has a first surface, a plurality of the first connection pad of this first surface, a plurality of the first projection and a plurality of the first solder layer that is electrically connected at described the first connection pad of being arranged at, respectively this first solder layer be formed at respectively on this first projection and respectively this first solder layer have a taper groove, this taper groove has a madial wall; One second substrate, it has a second surface, a plurality of the second connection pad of this second surface, a plurality of the second projection and a plurality of the second solder layer that is formed at described the second connection pad of being arranged at, respectively this second solder layer is formed at respectively on this second projection, respectively this second solder layer is a cone and has an external annulus, respectively this second solder layer be incorporated into respectively this first solder layer and respectively this second solder layer be located in respectively this first solder layer, this madial wall contact of this taper groove this external annulus of this second solder layer respectively respectively; And an adhesive body, it is formed between this first substrate and this second substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor package, wherein said respectively this first projection has one first end face, and respectively this second solder layer has one second end face in addition, and this first end face contacts this second end face.
Aforesaid semiconductor package, wherein said respectively this second projection has a taper ring wall, has one first angle between this taper ring wall and this second surface, and this first angle is greater than 90 degree.
Aforesaid semiconductor package has one second angle between this external annulus of wherein said respectively this second solder layer and this second surface, this second angle is greater than 90 degree.
Aforesaid semiconductor package, wherein said respectively this taper groove has a upper shed and a under shed, and this upper shed has one first width, and this under shed has one second width, and this second width is less than this first width.
Aforesaid semiconductor package, the material of wherein said the first projection and described the second projection be selected from gold, copper, copper/nickel or copper/nickel/gold one of them.
Aforesaid semiconductor package, the material of wherein said the first projection are dielectric material.
Aforesaid semiconductor package, wherein saidly include in addition a plurality of the first metal column sandwich layers, respectively this first projection coat respectively this first metal column sandwich layer and respectively this first metal column sandwich layer have a first end and one second end, respectively this first end contact respectively this first projection and respectively this second end for appearing.
Aforesaid semiconductor package, the material of wherein said the second projection are dielectric material.
Aforesaid semiconductor package, wherein saidly include in addition a plurality of the second metal column sandwich layers, respectively this second projection coat respectively this second metal column sandwich layer and respectively this second metal column sandwich layer have one the 3rd end and one the 4th end, respectively this second projection and the 4th end in contact this second solder layer respectively respectively of the 3rd end in contact respectively.
Aforesaid semiconductor package, the material of wherein said the first solder layer and described the second solder layer is selected from lead-free solder.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of method for packaging semiconductor according to the present invention's proposition, wherein comprise at least: a first substrate is provided, this first substrate has a first surface, a plurality of the first connection pad of this first surface, a plurality of the first projection and a plurality of the first solder layer that is electrically connected at described the first connection pad of being arranged at, respectively this first solder layer be formed at respectively on this first projection and respectively this first solder layer have a taper groove, this taper groove has a madial wall; Flip-chip bonded one second substrate and this first substrate, this second substrate has a second surface, a plurality of the second connection pad of this second surface, a plurality of the second projection and a plurality of the second solder layer that is electrically connected at described the second connection pad of being arranged at, respectively this second solder layer is formed at respectively on this second projection, and respectively this second solder layer is a cone and has an external annulus; This second substrate of Pressurized-heated so that respectively this second solder layer be incorporated into respectively this first solder layer and respectively this second solder layer be located in respectively this first solder layer, this madial wall contact of this taper groove this external annulus of this second solder layer respectively respectively; And form an adhesive body between this first substrate and this second substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid method for packaging semiconductor, in the step of wherein said this second substrate of Pressurized-heated, force value is between 0.4 newton (N)-120 newton (N), and temperature value is between 180 ℃-460 ℃.
Aforesaid method for packaging semiconductor, the manufacture method of wherein said first substrate comprises: one first base material is provided, and this first base material has a first surface and a plurality of the first connection pad that is arranged at this first surface; Form one first photoresist layer at this first base material; This first photoresist layer of patterning is to form a plurality of the first flutings, corresponding described the first connection pad of described the first fluting; Form a plurality of the first projections at described the first fluting; Remove this first photoresist layer; Form one second photoresist layer at this first base material, and cover described the first projection; This second photoresist layer of patterning is to form a plurality of the second flutings, corresponding described the first projection of described the second fluting; Form a plurality of the first solder layers at described the second fluting, respectively this first solder layer has a taper groove and this taper groove has a madial wall; And remove this second photoresist layer.
Aforesaid method for packaging semiconductor, the manufacture method of wherein said second substrate comprises: one second base material is provided, and this second base material has a second surface and a plurality of the second connection pad that is arranged at this second surface; Form one the 3rd photoresist layer in this second base material; Patterning the 3rd photoresist layer is to form a plurality of the 3rd flutings, corresponding described the second connection pad of described the 3rd fluting; Form a plurality of the second projections at described the 3rd fluting; Etching respectively this second projection so that respectively this second projection have a taper ring wall; Remove the 3rd photoresist layer; Form one the 4th photoresist layer at this second base material, and cover described the second projection; Patterning the 4th photoresist layer is to form a plurality of the 4th flutings, corresponding described the second projection of described the 4th fluting; Form a plurality of the second solder layers at described the 4th fluting; And remove the 4th photoresist layer.
Aforesaid method for packaging semiconductor, wherein said respectively this first projection has one first end face, and respectively this second solder layer has one second end face in addition, and this first end face contacts this second end face.
Aforesaid method for packaging semiconductor, wherein said respectively this taper groove has a upper shed and a under shed, and this upper shed has one first width, and this under shed has one second width, and this second width is less than this first width.
Aforesaid method for packaging semiconductor, the material of wherein said the first projection and described the second projection be selected from gold, copper, copper/nickel or copper/nickel/gold one of them.
Aforesaid method for packaging semiconductor, the material of wherein said the first projection are dielectric material.
Aforesaid method for packaging semiconductor, wherein saidly include in addition a plurality of the first metal column sandwich layers, respectively this first projection coat respectively this first metal column sandwich layer and respectively this first metal column sandwich layer have a first end and one second end, respectively this first end contact respectively this first projection and respectively this second end for appearing.
Aforesaid method for packaging semiconductor, the material of wherein said the second projection are dielectric material.
Aforesaid method for packaging semiconductor, wherein saidly include in addition a plurality of the second metal column sandwich layers, respectively this second projection coat respectively this second metal column sandwich layer and respectively this second metal column sandwich layer have one the 3rd end and one the 4th end, respectively this second projection and the 4th end in contact this second solder layer respectively respectively of the 3rd end in contact respectively.
Aforesaid method for packaging semiconductor, the material of wherein said the first solder layer and described the second solder layer is selected from lead-free solder.
Aforesaid method for packaging semiconductor has one first angle between this taper ring wall of wherein said respectively this second projection and this second surface, and this first angle is greater than 90 degree.
Aforesaid method for packaging semiconductor has one second angle between this external annulus of wherein said respectively this second solder layer and this second surface, this second angle is greater than 90 degree.
The present invention compared with prior art has obvious advantage and beneficial effect.By above technical scheme as can be known, main technical content of the present invention is as follows: a kind of semiconductor package is provided, it comprises a first substrate, one second substrate and an adhesive body, this first substrate has a first surface, a plurality of the first connection pads that are arranged at this first surface, a plurality of the first projection and a plurality of the first solder layers that are electrically connected at described the first connection pad, respectively this first solder layer be formed at respectively on this first projection and respectively this first solder layer have a taper groove, this taper groove has a madial wall, this second substrate has a second surface, a plurality of the second connection pads that are arranged at this second surface, a plurality of the second projection and a plurality of the second solder layers that are formed at described the second connection pad, respectively this second solder layer be formed at respectively on this second projection and respectively this second solder layer be a cone and have an external annulus, respectively this second solder layer be incorporated into respectively this first solder layer and respectively this second solder layer be located in respectively this first solder layer, respectively this madial wall of this taper groove contacts respectively this external annulus of this second solder layer, and this adhesive body is formed between this first substrate and this second substrate.
By technique scheme, semiconductor package of the present invention and method for packing thereof have following advantages and beneficial effect at least: by this first solder layer respectively be formed at respectively on this first projection and respectively this first solder layer have this taper groove, respectively this second solder layer be formed at respectively on this second projection and respectively this second solder layer be a cone, therefore this first substrate can directly dock with this second substrate and storehouse and docking after formed spacing and thickness less contaminative is low, reliability is high and the effect of saving cost so that this semiconductor package has.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and the cooperation accompanying drawing, be described in detail as follows.
Description of drawings
Fig. 1 is according to the first preferred embodiment of the present invention, a kind of schematic cross-section of semiconductor package.
Fig. 2 is according to the second preferred embodiment of the present invention, the schematic cross-section of another kind of semiconductor package.
Fig. 3 A to Fig. 3 B is according to the first preferred embodiment of the present invention, a kind of schematic cross-section of method for packaging semiconductor.
Fig. 4 A to Fig. 4 I is according to the first preferred embodiment of the present invention, the schematic cross-section of this first substrate manufacture method.
Fig. 5 A to Fig. 5 J is according to the first preferred embodiment of the present invention, the schematic cross-section of this second substrate manufacture method.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, semiconductor package and its embodiment of method for packing, structure, method, step, feature and effect thereof to foundation the present invention proposes are described in detail as follows.
See also Fig. 1; its first preferred embodiment of the present invention; a kind of semiconductor package 100 comprises a first substrate 110; one second substrate 120 and an adhesive body 130; this first substrate 110 has a first surface 111; one covers the first protective layer 112 of this first surface 111; a plurality of the first connection pads 113 that are arranged at this first surface 111; a plurality of the first projection 114 and a plurality of the first solder layers 115 that are electrically connected at described the first connection pad 113; this first protective layer 112 has the first opening 112a of described the first connection pad 113 of a plurality of correspondences to appear described the first connection pad 113; the material of described the first projection 114 can be selected from gold; copper; copper/nickel or copper/nickel/gold one of them; respectively this first solder layer 115 be formed at respectively on this first projection 114 and respectively this first solder layer 115 have a taper groove 115a; this taper groove 115a has a madial wall 115b; one upper shed 115c and a under shed 115d; this upper shed 115c has one first width W 1; this under shed 115d has one second width W 2; this second width W 2 is less than this first width W 1; this second substrate 120 has a second surface 121; one covers the second protective layer 122 of this second surface 121; a plurality of the second connection pads 123 that are arranged at this second surface 121; a plurality of the second projection 124 and a plurality of the second solder layers 125 that are formed at described the second connection pad 123; this second protective layer 122 has the second opening 122a of described the second connection pad 123 of a plurality of correspondences to appear described the first connection pad 113; respectively this second solder layer 125 is formed at respectively on this second projection 124; the material of described the second projection 124 is selected from gold; copper; copper/nickel or copper/nickel/gold one of them; in the present embodiment; respectively this second projection 124 has a taper ring wall 124a; has one first included angle B 1 between this taper ring wall 124a and this second surface 121; this first included angle B 1 is greater than 90 degree; respectively this second solder layer 125 is a cone and has an external annulus 125a; respectively has one second included angle B 2 between this external annulus 125a of this second solder layer 125 and this second surface 121; this second included angle B 2 is greater than 90 degree; in the present embodiment; respectively this second solder layer 125 be incorporated into respectively this first solder layer 115 and respectively this second solder layer 125 be located in respectively this first solder layer 115; respectively this madial wall 115b of this taper groove 115a contacts respectively this external annulus 125a of this second solder layer 125; and respectively this first projection 114 has one first end face 114a; respectively this second solder layer 125 has one second end face 125b in addition; this first end face 114a contacts this second end face 125b; in the present embodiment; the material of described the first solder layer 115 and described the second solder layer 125 is selected from lead-free solder, and this adhesive body 130 is formed between this first substrate 110 and this second substrate 120.Since respectively this first solder layer 115 be formed at respectively on this first projection 114 and respectively this first solder layer 115 have this taper groove 115a, respectively this second solder layer 125 be formed at respectively on this second projection 124 and respectively this second solder layer 125 be a cone, therefore this first substrate 110 can directly dock with this second substrate 120 and storehouse and docking formed spacing and thickness are less afterwards, in addition, the material of described the first solder layer 115 and described the second solder layer 125 is selected from lead-free solder, therefore can omit scaling powder and have contaminative and hang down and cost-effective effect, and then promote the reliability of this semiconductor package 100.
Perhaps, see also Fig. 2, its second preferred embodiment of the present invention, in the present embodiment, the material of described the first projection 114 and described the second projection 124 is dielectric material, and this semiconductor package 100 includes a plurality of the first metal column sandwich layers 140 and a plurality of the second metal column sandwich layer 150 in addition, respectively this first projection 114 coat respectively this first metal column sandwich layer 140 and respectively this first metal column sandwich layer 140 have a first end 141 and one second end 142, respectively 141 contacts of this first end respectively this first projection 114 and respectively this second end 142 for appearing, respectively this second projection 124 coat respectively this second metal column sandwich layer 150 and respectively this second metal column sandwich layer 150 have one the 3rd end 151 and one the 4th end 152, respectively this second projection 124 and the 4th end 152 contacts this second solder layer 125 respectively respectively of the 3rd end 151 contacts respectively.
Then; see also Fig. 3 A to Fig. 3 B; it is the method for packaging semiconductor of the first preferred embodiment of the present invention; it comprises the following step at least: at first; see also Fig. 3 A; one first substrate 110 is provided; this first substrate 110 has a first surface 111; one covers the first protective layer 112 of this first surface 111; a plurality of the first connection pads 113 that are arranged at this first surface 111; a plurality of the first projection 114 and a plurality of the first solder layers 115 that are electrically connected at described the first connection pad 113; respectively this first solder layer 115 be formed at respectively on this first projection 114 and respectively this first solder layer 115 have a taper groove 115a, this taper groove 115a has a madial wall 115b.
In addition, see also Fig. 4 A to Fig. 4 I, it is the manufacture method of this first substrate 110, comprise the following step: at first, see also Fig. 4 A, provide one first base material 110 ', this first base material 110 ' have first surface 111, covers the first protective layer 112 and a plurality of first connection pad 113 that is arranged at this first surface 111 of this first surface 111; Then, see also Fig. 4 B, form one first photoresist layer P1 in this first base material 110 '; Afterwards, see also Fig. 4 C, this first photoresist layer of patterning P1 is to form a plurality of the first fluting A1, corresponding described the first connection pad 113 of described the first fluting A1; Then, see also Fig. 4 D, form a plurality of the first projections 114 at described the first fluting A1, respectively the material of this first projection 114 with one first end face 114a and described first projection 114 be selected from gold, copper, copper/nickel or copper/nickel/gold one of them; Afterwards, see also Fig. 4 E, remove this first photoresist layer P1; Then, see also Fig. 4 F, form one second photoresist layer P2 this first base material 110 ', and cover described the first projection 114; Afterwards, see also Fig. 4 G, this second photoresist layer of patterning P2 is to form a plurality of the second fluting A2, corresponding described the first projection 114 of described the second fluting A2; Then, please join Fig. 4 H, form a plurality of the first solder layers 115 at described the second fluting A2, the material of described the first solder layer 115 can be lead-free solder; At last, see also Fig. 4 I, remove this second photoresist layer P2 and appear described the first solder layer 115 to form this first substrate 110, respectively this first solder layer 115 has a taper groove 115a and this taper groove 115a has a madial wall 115b, respectively this taper groove 115a has a upper shed 115c and a under shed 115d, this upper shed 115c has one first width W 1, and this under shed 115d has one second width W 2, and this second width W 2 is less than this first width W 1.
Then; see also Fig. 3 B; flip-chip bonded one second substrate 120 is at this first substrate 110; this second substrate 120 has the second protective layer 122, a plurality of the second connection pad 123 of this second surface 121, a plurality of the second projection 124 and a plurality of the second solder layer 125 that is electrically connected at described the second connection pad 123 of being arranged at that a second surface 121, covers this second surface 121; respectively this second solder layer 125 is formed at respectively on this second projection 124, and respectively this second solder layer 125 is a cone and has an external annulus 125a.
In addition, see also Fig. 5 A to Fig. 5 J, it is the manufacture method of this second substrate 120, comprise the following step: at first, see also Fig. 5 A, provide one second base material 120 ', this second base material 120 ' have second surface 121, covers the second protective layer 122 and a plurality of second connection pad 123 that is arranged at this second surface 121 of this second surface 121; Then, see also Fig. 5 B, form one the 3rd photoresist layer P3 this second base material 120 '; Afterwards, see also Fig. 5 C, patterning the 3rd photoresist layer P 3 is to form a plurality of the 3rd fluting A3, corresponding described the second connection pad 123 of described the 3rd fluting A3; Then, see also Fig. 5 D, form a plurality of the second projections 124 described the 3rd the fluting A3, the material of described the second projection 124 can be selected from gold, copper, copper/nickel or copper/nickel/gold one of them; Afterwards, see also Fig. 5 E, etching respectively this second projection 124 so that respectively this second projection 124 have a taper ring wall 124a; Then, see also Fig. 5 F, remove the 3rd photoresist layer P3 to manifest described the second projection 124, in the present embodiment, respectively have one first included angle B 1 between this taper ring wall 124a of this second projection 124 and this second surface 121, this first included angle B 1 is greater than 90 degree; Afterwards, see also Fig. 5 G, form one the 4th photoresist layer P4 this second base material 120 ', and cover described the second projection 124; Then, see also Fig. 5 H, patterning the 4th photoresist layer P4 is to form a plurality of the 4th fluting A4, corresponding described the second projection 124 of described the 4th fluting A4; Afterwards, see also Fig. 5 I, form a plurality of the second solder layers 125 at described the 4th fluting A4, respectively this second solder layer 125 has one second end face 125b in addition, and the material of described the second solder layer 125 is selected from lead-free solder; At last, see also Fig. 5 J, remove the 4th photoresist layer P4 and appear described the second solder layer 125 to form this second substrate 120, in the present embodiment, respectively have one second included angle B 2 between this external annulus 125a of this second solder layer 125 and this second surface 121, this second included angle B 2 is greater than 90 degree.
Then, please consult again Fig. 3 B, this second substrate 120 of Pressurized-heated so that respectively this second solder layer 125 be incorporated into respectively this first solder layer 115 and respectively this second solder layer 125 be located in respectively this first solder layer 115, respectively this madial wall 115b of this taper groove 115a contacts respectively this external annulus 125a of this second solder layer 125, respectively this first end face 114a of this first projection 114 contacts respectively this second end face 125b of this second solder layer 125, in the present embodiment, in the step of this second substrate 120 of Pressurized-heated, force value is between 0.4 newton (N)-120 newton (N), and temperature value is between 180 ℃-460 ℃; At last, please consult again Fig. 1, form between an adhesive body 130 and this first substrate 110 and this second substrate 120 to form this semiconductor package 100.Since respectively this first solder layer 115 have this taper groove 115a and respectively this second solder layer 125 be a cone, so this first substrate 110 can directly dock with this second substrate 120 and storehouse and have the effect of simple process.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet be not to limit the present invention, any those skilled in the art, within not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, any simple modification that foundation technical spirit of the present invention is done above embodiment, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (25)
1. semiconductor package is characterized in that it comprises at least:
One first substrate, have a first surface, a plurality of the first connection pad of this first surface, a plurality of the first projection and a plurality of the first solder layer that is electrically connected at described the first connection pad of being arranged at, respectively this first solder layer be formed at respectively on this first projection and respectively this first solder layer have a taper groove, this taper groove has a madial wall;
One second substrate, it has a second surface, a plurality of the second connection pad of this second surface, a plurality of the second projection and a plurality of the second solder layer that is formed at described the second connection pad of being arranged at, respectively this second solder layer is formed at respectively on this second projection, respectively this second solder layer is a cone and has an external annulus, respectively this second solder layer be incorporated into respectively this first solder layer and respectively this second solder layer be located in respectively this first solder layer, this madial wall contact of this taper groove this external annulus of this second solder layer respectively respectively; And
One adhesive body, it is formed between this first substrate and this second substrate.
2. semiconductor package as claimed in claim 1 is characterized in that wherein said respectively this first projection has one first end face, and respectively this second solder layer has one second end face in addition, and this first end face contacts this second end face.
3. semiconductor package as claimed in claim 1 is characterized in that wherein said respectively this second projection has a taper ring wall, has one first angle between this taper ring wall and this second surface, and this first angle is greater than 90 degree.
4. semiconductor package as claimed in claim 1 is characterized in that having one second angle between this external annulus of wherein said respectively this second solder layer and this second surface, and this second angle is greater than 90 degree.
5. semiconductor package as claimed in claim 1, it is characterized in that wherein said respectively this taper groove has a upper shed and a under shed, this upper shed has one first width, and this under shed has one second width, and this second width is less than this first width.
6. semiconductor package as claimed in claim 1, the material that it is characterized in that wherein said the first projection and described the second projection be selected from gold, copper, copper/nickel or copper/nickel/gold one of them.
7. semiconductor package as claimed in claim 1, the material that it is characterized in that wherein said the first projection is dielectric material.
8. semiconductor package as claimed in claim 7, it is characterized in that including in addition a plurality of the first metal column sandwich layers, respectively this first projection coat respectively this first metal column sandwich layer and respectively this first metal column sandwich layer have a first end and one second end, respectively this first end contact respectively this first projection and respectively this second end for appearing.
9. semiconductor package as claimed in claim 1, the material that it is characterized in that wherein said the second projection is dielectric material.
10. semiconductor package as claimed in claim 9, it is characterized in that including in addition a plurality of the second metal column sandwich layers, respectively this second projection coat respectively this second metal column sandwich layer and respectively this second metal column sandwich layer have one the 3rd end and one the 4th end, respectively this second projection and the 4th end in contact this second solder layer respectively respectively of the 3rd end in contact respectively.
11. semiconductor package as claimed in claim 1 is characterized in that the material of wherein said the first solder layer and described the second solder layer is selected from lead-free solder.
12. a method for packaging semiconductor is characterized in that it comprises at least:
One first substrate is provided, this first substrate has a first surface, a plurality of the first connection pad of this first surface, a plurality of the first projection and a plurality of the first solder layer that is electrically connected at described the first connection pad of being arranged at, respectively this first solder layer be formed at respectively on this first projection and respectively this first solder layer have a taper groove, this taper groove has a madial wall;
Flip-chip bonded one second substrate and this first substrate, this second substrate has a second surface, a plurality of the second connection pad of this second surface, a plurality of the second projection and a plurality of the second solder layer that is electrically connected at described the second connection pad of being arranged at, respectively this second solder layer is formed at respectively on this second projection, and respectively this second solder layer is a cone and has an external annulus;
This second substrate of Pressurized-heated so that respectively this second solder layer be incorporated into respectively this first solder layer and respectively this second solder layer be located in respectively this first solder layer, this madial wall contact of this taper groove this external annulus of this second solder layer respectively respectively; And
Form an adhesive body between this first substrate and this second substrate.
13. method for packaging semiconductor as claimed in claim 12 is characterized in that in the step of wherein said this second substrate of Pressurized-heated, force value is between 0.4 newton (N)-120 newton (N), and temperature value is between 180 ℃-460 ℃.
14. method for packaging semiconductor as claimed in claim 12 is characterized in that the manufacture method of wherein said first substrate comprises:
One first base material is provided, and this first base material has a first surface and a plurality of the first connection pad that is arranged at this first surface;
Form one first photoresist layer at this first base material;
This first photoresist layer of patterning is to form a plurality of the first flutings, corresponding described the first connection pad of described the first fluting;
Form a plurality of the first projections at described the first fluting;
Remove this first photoresist layer;
Form one second photoresist layer at this first base material, and cover described the first projection;
This second photoresist layer of patterning is to form a plurality of the second flutings, corresponding described the first projection of described the second fluting;
Form a plurality of the first solder layers at described the second fluting, respectively this first solder layer has a taper groove and this taper groove has a madial wall; And
Remove this second photoresist layer.
15. method for packaging semiconductor as claimed in claim 12 is characterized in that the manufacture method of wherein said second substrate comprises:
One second base material is provided, and this second base material has a second surface and a plurality of the second connection pad that is arranged at this second surface;
Form one the 3rd photoresist layer in this second base material;
Patterning the 3rd photoresist layer is to form a plurality of the 3rd flutings, corresponding described the second connection pad of described the 3rd fluting;
Form a plurality of the second projections at described the 3rd fluting;
Etching respectively this second projection so that respectively this second projection have a taper ring wall;
Remove the 3rd photoresist layer;
Form one the 4th photoresist layer at this second base material, and cover described the second projection;
Patterning the 4th photoresist layer is to form a plurality of the 4th flutings, corresponding described the second projection of described the 4th fluting;
Form a plurality of the second solder layers at described the 4th fluting; And
Remove the 4th photoresist layer.
16. method for packaging semiconductor as claimed in claim 12 is characterized in that wherein said respectively this first projection has one first end face, respectively this second solder layer has one second end face in addition, and this first end face contacts this second end face.
17. method for packaging semiconductor as claimed in claim 12, it is characterized in that wherein said respectively this taper groove has a upper shed and a under shed, this upper shed has one first width, and this under shed has one second width, and this second width is less than this first width.
18. method for packaging semiconductor as claimed in claim 12, the material that it is characterized in that wherein said the first projection and described the second projection be selected from gold, copper, copper/nickel or copper/nickel/gold one of them.
19. method for packaging semiconductor as claimed in claim 12, the material that it is characterized in that wherein said the first projection is dielectric material.
20. method for packaging semiconductor as claimed in claim 19, it is characterized in that including in addition a plurality of the first metal column sandwich layers, respectively this first projection coat respectively this first metal column sandwich layer and respectively this first metal column sandwich layer have a first end and one second end, respectively this first end contact respectively this first projection and respectively this second end for appearing.
21. method for packaging semiconductor as claimed in claim 12, the material that it is characterized in that wherein said the second projection is dielectric material.
22. method for packaging semiconductor as claimed in claim 21, it is characterized in that including in addition a plurality of the second metal column sandwich layers, respectively this second projection coat respectively this second metal column sandwich layer and respectively this second metal column sandwich layer have one the 3rd end and one the 4th end, respectively this second projection and the 4th end in contact this second solder layer respectively respectively of the 3rd end in contact respectively.
23. method for packaging semiconductor as claimed in claim 12 is characterized in that the material of wherein said the first solder layer and described the second solder layer is selected from lead-free solder.
24. method for packaging semiconductor as claimed in claim 15 is characterized in that having one first angle between this taper ring wall of wherein said respectively this second projection and this second surface, this first angle is greater than 90 degree.
25. method for packaging semiconductor as claimed in claim 12 is characterized in that having one second angle between this external annulus of wherein said respectively this second solder layer and this second surface, this second angle is greater than 90 degree.
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| CN108133924A (en) * | 2017-12-20 | 2018-06-08 | 江苏冠达通电子科技有限公司 | Semiconductor chip package and its method |
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