CN203070202U - Resetting management circuit among multiple processors - Google Patents
Resetting management circuit among multiple processors Download PDFInfo
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- CN203070202U CN203070202U CN 201220607838 CN201220607838U CN203070202U CN 203070202 U CN203070202 U CN 203070202U CN 201220607838 CN201220607838 CN 201220607838 CN 201220607838 U CN201220607838 U CN 201220607838U CN 203070202 U CN203070202 U CN 203070202U
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Abstract
The utility model relates to a resetting management circuit among multiple processors. The resetting management circuit among the multiple processors comprises a timer circuit, a field programmable gate array (GPGA) unit, a first logic controller, a second logic controller, a digital signal processor (DSP) unit and a PPC unit. One circuit of an output end of the timer circuit is connected with the first logic controller, and another circuit of the output end of the timer circuit is connected with the second logic controller. One circuit of an output end of the FPGA unit is connected with an input end of the timer circuit, and another two circuits of the output end of the FPGA unit are respectively connected with the first logic controller and the second logic controller. An output end of the first logic controller is connected with an input end of the FPGA unit through the DSP unit, and an output end of the second logic controller is connected with the input end of the FPGA unit through the DSP unit. According to the resetting management circuit among the multiple processors, simple unified resetting among the multiple processors does not exist anymore, a single processor can judge according to programs or conduct single resetting according to instructions of an upper computer, and the stability of the whole system is improved.
Description
Technical field
The utility model relates to a kind of management circuit that resets, and is specifically related to the management circuit that resets between a kind of multiprocessor.
Background technology
Along with the further raising of product technology demand, the platform that single-processor is formed can't satisfy the demand of properties of product and function, so the platform that the multiprocessor collaborative work is formed more and more has been applied in the new product design.Will produce the problem of management that resets between multiprocessor thus; Solution is to use following two kinds of solutions at present:
1, with the reset signal of a plurality of relatively independent systems and all peripherals with the unified way to manage that resets, this reset mode can reduce the management that resets, when system has any one functional module to reset, all can only adopt the mode of system's general reset, can not carry out independently resetting at functional module.
2, will adopt many cover reset circuits to manage each relatively independent system respectively, though this mode can independently be carried out the reset function of partial function assembly, total system can not be unified to manage, and brings certain test for the stability of system;
In sum, the problem that adopts conventional reset processing mode to exist is, system's shortage unified management that resets can't be carried out the individual reset of partial function assembly, influences the reliability service of total system.
The utility model content
The problem that the utility model solves provides the management circuit that resets between a kind of multiprocessor, by with DSP, PPC, the reset signal unification of three processors of FPGA manages control by FPGA, and system unifies at the initial stage that powers on to realize that by the house dog electrify restoration circuit of outside system synchronization resets; The management circuit judges that resets, or according to host computer instruction is carried out partial function and is resetted separately, with the resolution system shortage unified management that resets, can't carry out partial function and reset separately, influence the problem of total system reliability service.
For addressing the above problem, the technical solution adopted in the utility model is:
The management circuit that resets between a kind of multiprocessor, its special character is: comprise timer circuit, the FPGA unit, first logic controller, second logic controller, the DSP unit, the PPC unit, the output terminal one tunnel of timer circuit is connected with first logic controller, another road is connected with second logic controller, the output terminal one tunnel of FPGA unit is connected with the input end of timer circuit, in addition two-way respectively with first logic controller, second logic controller connects, input end with the FPGA unit is connected the output terminal of first logic controller through the DSP unit, and the input end with the FPGA unit is connected the output terminal of second logic controller through the PPC unit.
The chip UD5 that above-mentioned timer circuit adopts is that MAX823, chip UD6 are that 74LVC1G32, chip QD2 are that S9013, chip UD7 and UP23 are that 74LVC1G08, chip UF22-1 are EP4CE55.
The chip UF22-1 that above-mentioned FPGA unit adopts is that EP4CE55, chip UD25C are that ADSP-BF548, chip UP24-2 are MPC8313E.
The chip UD7 that the above-mentioned first logic controller adopts is 74LVC1G08.
The chip UP23 that the second above-mentioned logic controller adopts is 74LVC1G08.
The chip UD25C that above-mentioned DSP unit adopts is ADSP-BF548.
The chip UP24-2 that above-mentioned PPC unit adopts is MPC8313E.
Compared with prior art, the beneficial effects of the utility model:
1, resetting between multiprocessor is being not simple unified resetting;
2, single-processor can be judged according to program, or independent resetting carried out in instruction according to host computer; Improved the stability of total system.
Description of drawings
Fig. 1 is the utility model theory diagram;
Fig. 2 is the schematic diagram of utility model circuit.
Embodiment
Below in conjunction with accompanying drawing the utility model is specifically described.
Referring to Fig. 1, the utility model, comprise timer circuit 1, FPGA unit 2, first logic controller 3, second logic controller 4, DSP unit 5, PPC unit 6, the output terminal one tunnel of timer circuit 1 is connected with first logic controller 3, another road is connected with second logic controller 4, the output terminal one tunnel of FPGA unit 2 is connected with the input end of timer circuit 1, in addition two-way respectively with first logic controller 3, second logic controller 4 connects, input end with FPGA unit 2 is connected the output terminal of first logic controller 3 through DSP unit 5, and the input end with FPGA unit 2 is connected the output terminal of second logic controller 4 through PPC unit 6.
The chip UD5 that above-mentioned timer circuit 1 adopts is that MAX823, chip UD6 are that 74LVC1G32, chip QD2 are that S9013, chip UD7 and UP23 are that 74LVC1G08, chip UF22-1 are EP4CE55.
The chip UF22-1 that above-mentioned FPGA unit 2 adopts is that EP4CE55, chip UD25C are that ADSP-BF548, chip UP24-2 are MPC8313E.
The chip UD7 that above-mentioned first logic controller 3 adopts is 74LVC1G08.
The chip UP23 that the second above-mentioned logic controller 4 adopts is 74LVC1G08.
The chip UD25C that above-mentioned DSP unit 5 adopts is ADSP-BF548.
The chip UP24-2 that above-mentioned PPC unit 6 adopts is MPC8313E.
Timer circuit 1 is that 2 feeding-dog signals of the reset output signal of house dog and FPGA are respectively through first logic controller 3, second logic controller 4, DSP is given in the output of first logic controller 3, second logic controller 4 respectively, PPC is as the independent reset signal of each processor system; DSP, PPC processor export 1 feeding-dog signal respectively and link to each other with FPGA, and feeding-dog signal of FPGA output is connected with timer circuit 1; FPGA realizes 3 independently timers respectively, and wherein 2 are used for counting DSP respectively, and the feeding-dog signal that PPC provides can not produce negative edge, then output low level in less than the time of 1.6S; And then by the logic controller DSP that resets, PPC; It is that the square wave output of 1S is connected with timer circuit 1 that another timer is used for the generation cycle.
Wherein 2 receptions of FPGA unit are from the feeding-dog signal of DSP unit 5 and PPC unit 6,2 reset signals of FPGA unit 2 outputs, connect first logic controller and second logic controller respectively, FPGA unit 2 output feeding-dog signals link to each other with timer circuit 1, make the reset signal of DSP and PPC independent like this, resetting of total system can manage by FPGA, dsp processor and the PPC processor own system that also can reset separately, and can not have influence on other module of system.
Referring to Fig. 2, in the utility model, the chip UD5 that described timer circuit 1 adopts is MAX823, comprises 5 pins, and the 1st pin is the output pin that resets, and wherein the 4th pin is " feeding dog " pin; Chip UD6 is 74LVC1G32, comprises 5 pins, and the 1st, 2 pin is 2 input pins, and the 4th pin is output pin; Chip QD2 is S9013, comprises 3 pins, and the 1st pin is base stage, and the 2nd pin is emitting stage, and the 3rd pin is collector; Chip UD7 and UP23 are 74LVC1G08, comprise 5 pins, and the 1st, 2 pin is and the door input pin that the 4th pin is output pin; Chip UF22-1 is that EP4CE55 comprises 484 pins; The 1st pin of chip UD5 links to each other with the 2nd pin of UD6, the 4th pin of chip UD5 links to each other with the 3rd pin of QD2 by resistance R D82, the 1st pin of chip QD2 links to each other with the H7 pin of UF22-1 by resistance R D36, the 4th pin of chip UD6 is respectively at UD7, and the 1st pin of UP23 and the E4 pin of UF22-1 link to each other;
It is EP4CE55 that described FPGA unit 2 adopts chip UF22-1, comprises 484 pins; Chip UD25C is ADSP-BF548, comprises 400 pins, and chip UP24-2 is MPC8313E, comprises 516 pins; The E4 pin of chip UF22-1 links to each other with the 4th pin of UD6, the C1 pin of UF22-1 links to each other with the Y14 pin of UD25C, the D2 pin of UF22-1 links to each other with the 2nd pin of UD7, the H7 pin of UF22-1 links to each other with the 1st pin of QD2 by resistance R D36, the H6 pin of UF22-1 links to each other with the AC24 pin of UP24-2, and the J6 pin of UF22-1 links to each other with the 2nd pin of UP23;
It is 74LVC1G08 that described first logic controller 3 adopts chip UD7, comprise 5 pins, the 1st pin of chip UD7 links to each other with the 4th pin of UD6, the 2nd pin links to each other with the D2 pin of UF22-1, the 4th pin links to each other with the C12 pin of UD25C, the 3rd pin links to each other with GND, and the 5th pin links to each other with+3.3V;
It is 74LVC1G08 that described second logic controller 4 adopts chip UP23, comprise 5 pins, the 1st pin of chip UP23 links to each other with the 4th pin of UD6, the 2nd pin links to each other with the J6 pin of UF22-1, the 4th pin links to each other with the F3 pin of UP24-2, the 3rd pin links to each other with GND, and the 5th pin links to each other with+3.3V;
It is ADSP-BF548 that described DSP unit 5 adopts chip UD25C, comprises 400 pins, and the Y14 pin of chip UD25C links to each other with the C1 of UF22-1, and the C12 pin of UD25C links to each other with the 4th pin of UD7;
It is MPC8313E that described PPC unit 6 adopts chip UP24-2, comprises 516 pins, and the AC24 pin of chip UP24-2 links to each other with the H6 pin of UF22-1, and the F3 pin of UP24-2 links to each other with the 4th pin of UP23;
Principle of work of the present utility model: total system powers on the initial stage by the unified reset signal of timer circuit output, make FPGA, DSP, PPC unifies synchronous reset in the unit, after the end that resets, 3 processor independent operatings program separately, and periodic DSP feeding-dog signal, the PPC feeding-dog signal that produces separately, the FPGA feeding-dog signal makes timer circuit not produce reset signal, timer in the FPGA unit does not produce FPGA DSP signal and the FPGA PPC signal that resets that resets, and total system is normally moved; Find the program mal of oneself when some moment DSP unit, perhaps program check errors, perhaps other fatal errors, the DSP feeding-dog signal is just closed in the DSP unit, then management circuit will only produce the FPGA DSP signal that resets, dsp system is resetted separately, and then do not influence the operate as normal of PPC unit and FPGA unit, in like manner the PPC unit also is such principle of work, another kind of situation is to allow some unit reset separately or integral reset when host computer by instruction, management circuit will be closed the corresponding element circuit of corresponding reset enable signal and be resetted separately, perhaps closes the FPGA feeding-dog signal, makes the total system unification reset.
Claims (7)
1. the management circuit that resets between a multiprocessor, it is characterized in that: comprise timer circuit (1), FPGA unit (2), first logic controller (3), second logic controller (4), DSP unit (5), PPC unit (6), the output terminal one tunnel of timer circuit (1) is connected with first logic controller (3), another road is connected with second logic controller (4), the output terminal one tunnel of FPGA unit (2) is connected with the input end of timer circuit (1), in addition two-way respectively with first logic controller (3), second logic controller (4) connects, input end with FPGA unit (2) is connected the output terminal of first logic controller (3) through DSP unit (5), and the input end with FPGA unit (2) is connected the output terminal of second logic controller (4) through PPC unit (6).
2. the management circuit that resets between a kind of multiprocessor according to claim 1 is characterized in that: the chip UD5 that described timer circuit (1) adopts is that MAX823, chip UD6 are that 74LVC1G32, chip QD2 are that S9013, chip UD7 and UP23 are that 74LVC1G08, chip UF22-1 are EP4CE55.
3. the management circuit that resets between a kind of multiprocessor according to claim 1 and 2 is characterized in that: the chip UF22-1 that described FPGA unit (2) adopts is that EP4CE55, chip UD25C are that ADSP-BF548, chip UP24-2 are MPC8313E.
4. the management circuit that resets between a kind of multiprocessor according to claim 3 is characterized in that: the chip UD7 that described first logic controller (3) adopts is 74LVC1G08.
5. the management circuit that resets between a kind of multiprocessor according to claim 4 is characterized in that: the chip UP23 that described second logic controller (4) adopts is 74LVC1G08.
6. the management circuit that resets between a kind of multiprocessor according to claim 5 is characterized in that: the chip UD25C that described DSP unit (5) adopts is ADSP-BF548.
7. the management circuit that resets between a kind of multiprocessor according to claim 6 is characterized in that: the chip UP24-2 that described PPC unit (6) adopts is MPC8313E.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220607838 CN203070202U (en) | 2012-11-17 | 2012-11-17 | Resetting management circuit among multiple processors |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220607838 CN203070202U (en) | 2012-11-17 | 2012-11-17 | Resetting management circuit among multiple processors |
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| CN203070202U true CN203070202U (en) | 2013-07-17 |
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| CN 201220607838 Expired - Fee Related CN203070202U (en) | 2012-11-17 | 2012-11-17 | Resetting management circuit among multiple processors |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105388982A (en) * | 2015-11-16 | 2016-03-09 | 中国电子科技集团公司第十研究所 | Multiprocessor power-on reset circuit |
-
2012
- 2012-11-17 CN CN 201220607838 patent/CN203070202U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105388982A (en) * | 2015-11-16 | 2016-03-09 | 中国电子科技集团公司第十研究所 | Multiprocessor power-on reset circuit |
| CN105388982B (en) * | 2015-11-16 | 2019-01-08 | 中国电子科技集团公司第十研究所 | Multiprocessor electrification reset circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Resetting management circuit among multiple processors Effective date of registration: 20140624 Granted publication date: 20130717 Pledgee: Bank of Changan Limited by Share Ltd. Xi'an branch Pledgor: Xi'an Xirui Protection and Congtrol Equipment Co.,Ltd. Registration number: 2014990000502 |
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| PLDC | Enforcement, change and cancellation of contracts on pledge of patent right or utility model | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 710077 Shaanxi Province, Xi'an City Road 85 No. 2 Modern Enterprise Center Building 3, 1 District 3 Building Patentee after: XI'AN XIRUI CONTROL TECHNOLOGY Co.,Ltd. Address before: 710077 Shaanxi Province, Xi'an City Road 85 No. 2 Modern Enterprise Center Building 3, 1 District 3 Building Patentee before: Xi'an Xirui Protection and Congtrol Equipment Co.,Ltd. |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20160415 Granted publication date: 20130717 Pledgee: Bank of Changan Limited by Share Ltd. Xi'an branch Pledgor: XI'AN XIRUI CONTROL TECHNOLOGY Co.,Ltd. Registration number: 2014990000502 |
|
| PLDC | Enforcement, change and cancellation of contracts on pledge of patent right or utility model | ||
| PM01 | Change of the registration of the contract for pledge of patent right |
Change date: 20160415 Registration number: 2014990000502 Pledgor after: XI'AN XIRUI CONTROL TECHNOLOGY Co.,Ltd. Pledgor before: Xi'an Xirui Protection and Congtrol Equipment Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130717 Termination date: 20211117 |