CN203057077U - Enhanced gain-type amplifying circuit - Google Patents
Enhanced gain-type amplifying circuit Download PDFInfo
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- CN203057077U CN203057077U CN 201220664174 CN201220664174U CN203057077U CN 203057077 U CN203057077 U CN 203057077U CN 201220664174 CN201220664174 CN 201220664174 CN 201220664174 U CN201220664174 U CN 201220664174U CN 203057077 U CN203057077 U CN 203057077U
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- amplifying circuit
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Abstract
The utility model discloses an enhanced gain-type amplifying circuit, and belongs to the circuit field. The enhanced gain-type amplifying circuit comprises a common source and base series circuit composed of a JFET common source circuit serving as a first stage and a BJT current follower serving as a second stage, wherein the JFET common source circuit is connected with an operational amplifier circuit. According to the abovementioned arrangement, the aim of solving the defect of low input voltage is achieved by simply adopting the operational amplifier circuit, thereby making the enhanced gain-type amplifying circuit few in power consumption, low n costs, and suitable for popularization and application.
Description
Technical field
The utility model relates to a kind of amplifying circuit, concretely, belongs to a kind of enhancing gain-type amplifying circuit.
Background technology
Amplifying circuit is a kind of circuit the most ordinary in the circuit, though existing amplifying circuit is effective, but in case when requiring the low and upper limiting frequency of noise high, must make voltage reach certain intensity.
The utility model content
The purpose of this utility model is to solve the low excessively defective of input voltage, and a kind of enhancing gain-type amplifying circuit is provided.
To achieve these goals, the technical solution adopted in the utility model is as follows:
A kind of enhancing gain-type amplifying circuit comprises common source-cobasis sequential circuit of being made up of as the second level as the first order and BJT current follower JFET common source circuit, wherein also is connected with operational amplification circuit on the JFET common source circuit.
Further, the common base of described BJT links to each other with the drain electrode of JFET.
Simultaneously, be connected with capacitor C b1 between the grid of described operational amplification circuit and JFET, be connected with resistance R 3 on the positive input terminal of this operational amplifier, be connected with resistance R 4 and the resistance R 5 of mutual series connection on the negative input end, also be parallel with capacitor C on this resistance R 5.
Further, be connected with between the common collector of described BJT and the power supply VCC and be connected with capacitor C b parallel with one another and resistance R b2 on resistance R c, the common emitter, wherein Bing Lian other end ground connection also is connected with resistance R b1 between this common emitter and the power supply VCC.
Further, an end that also connects resistance R g on the grid of described JFET, the other end ground connection of resistance R g, also be connected with capacitor C b1 between this grid and the DC power supply RS, also be connected with an end of resistance R 2 on the source electrode of described JFET, the other end of resistance R 2 is connected with resistance R 1, and resistance R 1 is also in parallel with capacitor C, the above-mentioned parallel branch other end ground connection that both constitute.
Compared with prior art, the utlity model has following beneficial effect:
(1) the utility model circuit structure is simple, with low cost, solves the low excessively defective of input voltage, is fit to promote the use of;
(2) the utility model adopts the configuration of BJT and JFET to cooperate, because the paraphase voltage amplifier circuit that JFET constitutes has the high and high characteristics of output resistance of voltage gain, adopt the BJT current follower can reach good amplification in the second level, upper limiting frequency can＞1MHz, and can eliminate Miller effect, intercept noise well.
(3) the utility model adopts a simple calculations amplifying circuit can realize this function, and little power consumption and cost are low.
Description of drawings
Fig. 1 is the circuit theory diagrams of the utility model-embodiment.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing and embodiment, and execution mode of the present utility model includes but not limited to the following example.
Embodiment
As shown in Figure 1, a kind of enhancing gain-type amplifying circuit comprises common source-cobasis sequential circuit of being made up of as the second level as the first order and BJT current follower JFET common source circuit, wherein also is connected with operational amplification circuit on the JFET common source circuit.
Be connected with capacitor C b1 between the grid of described operational amplification circuit and JFET, be connected with resistance R 3 on the positive input terminal of this operational amplifier, be connected with resistance R 4 and the resistance R 5 of mutual series connection on the negative input end, also be parallel with capacitor C on this resistance R 5, wherein resistance R 4 links to each other with the negative input end of operational amplifier, is loaded with power supply Vs between resistance R 5 and the R3.
The common base of described BJT links to each other with the drain electrode of JFET.Be connected with between the common collector of described BJT and the power supply VCC and be connected with capacitor C b parallel with one another and resistance R b2 on resistance R c, the common emitter, Bing Lian other end ground connection wherein, common collector also is connected with resistance R b1 by capacitor C b2 output dc voltage V0 between this common emitter and the power supply VCC.Power supply VCC=20V wherein, resistance R c=20k Ω, resistance R b1=47k Ω, resistance R b2=47k Ω, capacitor C b=47 uF, capacitor C b2=10 uF, the T2 among the BJT selects 3DG4 for use.
In order to realize the utility model better, an end that also connects resistance R g on the grid of described JFET, the other end ground connection of resistance R g, also be connected with capacitor C b1 between this grid and the DC power supply RS, also be connected with an end of resistance R 2 on the source electrode of described JFET, the other end of resistance R 2 is connected with resistance R 1, and resistance R 1 is also in parallel with capacitor C, the above-mentioned parallel branch other end ground connection that both constitute.Resistance R 1=4.7 K ω wherein, resistance R 2=100 Ω, capacitor C b1=0.47 uF, capacitor C=47 uF, the T1 among the JFET selects CS146 for use.
According to above-described embodiment, just can realize the utility model well.
Claims (5)
1. one kind strengthens the gain-type amplifying circuit, it is characterized in that, comprises common source-cobasis sequential circuit of being made up of as the second level as the first order and BJT current follower JFET common source circuit, wherein also is connected with operational amplification circuit on the JFET common source circuit.
2. a kind of enhancing gain-type amplifying circuit according to claim 1 is characterized in that the common base of described BJT links to each other with the drain electrode of JFET.
3. a kind of enhancing gain-type amplifying circuit according to claim 2, it is characterized in that, be connected with capacitor C b1 between the grid of described operational amplification circuit and JFET, be connected with resistance R 3 on the positive input terminal of this operational amplifier, be connected with resistance R 4 and the resistance R 5 of mutual series connection on the negative input end, also be parallel with capacitor C on this resistance R 5.
4. a kind of enhancing gain-type amplifying circuit according to claim 3, it is characterized in that, be connected with between the common collector of described BJT and the power supply VCC and be connected with capacitor C b parallel with one another and resistance R b2 on resistance R c, the common emitter, wherein Bing Lian other end ground connection also is connected with resistance R b1 between this common emitter and the power supply VCC.
5. a kind of enhancing gain-type amplifying circuit according to claim 4, it is characterized in that, an end that also connects resistance R g on the grid of described JFET, the other end ground connection of resistance R g, also be connected with capacitor C b1 between this grid and the DC power supply RS, also be connected with an end of resistance R 2 on the source electrode of described JFET, the other end of resistance R 2 is connected with resistance R 1, resistance R 1 is also in parallel with capacitor C, the above-mentioned parallel branch other end ground connection that both constitute.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220664174 CN203057077U (en) | 2012-12-06 | 2012-12-06 | Enhanced gain-type amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220664174 CN203057077U (en) | 2012-12-06 | 2012-12-06 | Enhanced gain-type amplifying circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203057077U true CN203057077U (en) | 2013-07-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220664174 Expired - Fee Related CN203057077U (en) | 2012-12-06 | 2012-12-06 | Enhanced gain-type amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203057077U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103457544A (en) * | 2013-09-10 | 2013-12-18 | 昆山奥德鲁自动化技术有限公司 | Low-noise amplification circuit |
-
2012
- 2012-12-06 CN CN 201220664174 patent/CN203057077U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103457544A (en) * | 2013-09-10 | 2013-12-18 | 昆山奥德鲁自动化技术有限公司 | Low-noise amplification circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130710 Termination date: 20131206 |