CN203014773U - Digital signal processing system - Google Patents
Digital signal processing system Download PDFInfo
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- CN203014773U CN203014773U CN 201220736426 CN201220736426U CN203014773U CN 203014773 U CN203014773 U CN 203014773U CN 201220736426 CN201220736426 CN 201220736426 CN 201220736426 U CN201220736426 U CN 201220736426U CN 203014773 U CN203014773 U CN 203014773U
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Abstract
The utility model discloses a digital signal processing system relating to the signal processing field. The digital signal processing system comprises a signal input end, a digital user circuit, a phase-locked loop circuit, a synchronous protector, an EFM data demodulator, a digital attenuator/peak detector, a parallel/serial conversion circuit, a digital deemphasis circuit, a digital filter, a D/A converter, a signal output end, and a control circuit. A digital signal input by the signal input end can be processed by the digital user circuit, which is sequentially serially connected with the phase-locked loop circuit, the synchronous protector, the EFM data demodulator, the digital attenuator/peak detector, the parallel/serial conversion circuit, the digital deemphasis circuit, the digital filter, and the D/A converter, and then the signal output end can be used to output a processed simulation signal. The digital signal processing system is advantageous in that the stability is good, the data processing precision is high, the interference on the signal, the noise, and the distortion can be greatly reduced, and the tone quality can be greatly improved after the signal processing.
Description
Technical field
The utility model relates to the signal process field, relates in particular to a kind of digital information processing system.
Background technology
Along with science and technology and informationalized fast development, signal processing technology has been made significant headway, and is widely used in fields such as computer industry, communications industry and multimedia industries.But the signal of most is processed and is all carried out in simulation field, and analog signal processing technology is larger to interference and the distortion effect of signal, makes the signal quality of output relatively poor.Data processing speed is fast, the operational precision advantages of higher and digital processing technology has, and therefore develops digital information processing system for the interference, noise and the distortion that reduce signal, and the quality that improves signal is significant.
The utility model content
The technical problems to be solved in the utility model is: a kind of digital information processing system is provided, and interference, noise and distortion effect to signal in can effective address signal processing are larger, the relatively poor problem of signal tonequality of output.
to achieve these goals, the technical solution adopted in the utility model is: a kind of digital information processing system, comprise signal input part, digital line circuit, phase-locked loop circuit, the synchronous protection device, the EFM data demodulator, digital pad/peak detector, parallel/serial translation circuit, digital deemphasis circuit, digital filter, the D/A converter, signal output part and control circuit, the phase-locked loop circuit that the digital signal of inputting from signal input part is connected in series through order by digital line circuit, the synchronous protection device, the EFM data demodulator, digital pad/peak detector, parallel/serial translation circuit, digital deemphasis circuit, after digital filter and D/A converter are processed, again by the analog signal after signal output part output processing conversion.
Described phase-locked loop circuit is comprised of phase discriminator, frequency detector and voltage controlled oscillator.
Described synchronous protection device is connected with control circuit.
Described EFM data demodulator is connected with control circuit.
Described digital filter is 8 times of oversampling digital filters.
The beneficial effect that the utility model brings is: the utility model good stability, data processing precision are high, greatly reduce interference, noise and distortion to signal, and after signal is processed, tonequality is significantly improved; Phase-locked loop circuit and synchronous protection device have guaranteed that the synchronism stability of signal transmission carries out; Digital pad/peak detector has improved the stability of digital signal in the transmitting procedure; It is minimum that the processing of 8 times of oversampling digital filters is arrived the reducing noise in signal, further improved tonequality.
Description of drawings
Fig. 1 is the structured flowchart of the utility model embodiment.
Embodiment
The utility model is described in further detail below in conjunction with drawings and the specific embodiments.
as shown in Figure 1, a kind of digital information processing system, comprise signal input part, digital line circuit, phase-locked loop circuit, the synchronous protection device, the EFM data demodulator, digital pad/peak detector, parallel/serial translation circuit, digital deemphasis circuit, digital filter, the D/A converter, signal output part and control circuit, the phase-locked loop circuit that the digital signal of inputting from signal input part is connected in series through order by digital line circuit, the synchronous protection device, the EFM data demodulator, digital pad/peak detector, parallel/serial translation circuit, digital deemphasis circuit, after digital filter and D/A converter are processed, again by the analog signal after signal output part output processing conversion.
Described phase-locked loop circuit is comprised of phase discriminator, frequency detector and voltage controlled oscillator.
Described synchronous protection device is connected with control circuit.
Described EFM data demodulator is connected with control circuit.
Described digital filter is 8 times of oversampling digital filters.
the utility model course of work is as follows: from the digital signal of signal input part input by digital line circuit after phase-locked loop circuit and synchronous protection device carry out the signal synchronous protection, demodulation out from the EFM data demodulator, processing stablizing with inhibit signal through digital pad/peak detector, digital signal is transformed to serial signal through after parallel/serial translation circuit conversion by parallel signal again, then the processing by digital deemphasis circuit and 8 times of oversampling digital filters, the noise of further raising signal is the filtering interfering noise when, after being transformed to high-quality analog signal finally by the D/A converter, exported by signal output part.Control circuit is used for transmission and the conversion of control signal, and shows relevant information.
Claims (5)
1. digital information processing system; comprise signal input part, digital line circuit, phase-locked loop circuit, synchronous protection device, EFM data demodulator, digital pad/peak detector, parallel/serial translation circuit, digital deemphasis circuit, digital filter, D/A converter, signal output part and control circuit, it is characterized in that:
From the digital signal of signal input part input by digital line circuit after phase-locked loop circuit, synchronous protection device, EFM data demodulator, digital pad/peak detector, parallel/serial translation circuit, digital deemphasis circuit, digital filter and the D/A converter of order serial connection are processed, then process analog signal after conversion by signal output part output.
2. a kind of digital information processing system according to claim 1, it is characterized in that: described phase-locked loop circuit is comprised of phase discriminator, frequency detector and voltage controlled oscillator.
3. a kind of digital information processing system according to claim 1, it is characterized in that: described synchronous protection device is connected with control circuit.
4. a kind of digital information processing system according to claim 1, it is characterized in that: described EFM data demodulator is connected with control circuit.
5. a kind of digital information processing system according to claim 1, it is characterized in that: described digital filter is 8 times of oversampling digital filters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220736426 CN203014773U (en) | 2012-12-28 | 2012-12-28 | Digital signal processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220736426 CN203014773U (en) | 2012-12-28 | 2012-12-28 | Digital signal processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203014773U true CN203014773U (en) | 2013-06-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220736426 Expired - Lifetime CN203014773U (en) | 2012-12-28 | 2012-12-28 | Digital signal processing system |
Country Status (1)
| Country | Link |
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| CN (1) | CN203014773U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104581094A (en) * | 2014-12-16 | 2015-04-29 | 河南铭视安防工程有限公司 | Video optical transceiver and detecting method thereof |
| CN105306045A (en) * | 2014-06-23 | 2016-02-03 | 英特尔Ip公司 | Circuit, a time-to-digital converter, an integrated circuit, a transmitter, a receiver and a transceiver |
| CN105306046A (en) * | 2014-06-27 | 2016-02-03 | 英特尔Ip公司 | High-order sigma delta for a divider-less digital phase-locked loop |
| CN105703766A (en) * | 2014-12-15 | 2016-06-22 | 英特尔Ip公司 | Injection locked ring oscillator based digital-to-time converter |
| CN106209088A (en) * | 2016-06-30 | 2016-12-07 | 中国科学技术大学 | A kind of high energy efficiency orthogonal two-divider of high accuracy |
-
2012
- 2012-12-28 CN CN 201220736426 patent/CN203014773U/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105306045A (en) * | 2014-06-23 | 2016-02-03 | 英特尔Ip公司 | Circuit, a time-to-digital converter, an integrated circuit, a transmitter, a receiver and a transceiver |
| CN105306045B (en) * | 2014-06-23 | 2019-04-05 | 英特尔Ip公司 | Circuit, time-to-digit converter, integrated circuit and correlation method |
| CN105306046A (en) * | 2014-06-27 | 2016-02-03 | 英特尔Ip公司 | High-order sigma delta for a divider-less digital phase-locked loop |
| CN105306046B (en) * | 2014-06-27 | 2019-03-22 | 英特尔Ip公司 | The high-order Σ △ of digital phase-locked loop for no frequency divider |
| CN105703766A (en) * | 2014-12-15 | 2016-06-22 | 英特尔Ip公司 | Injection locked ring oscillator based digital-to-time converter |
| CN105703766B (en) * | 2014-12-15 | 2019-07-09 | 英特尔Ip公司 | Digit time converter based on injection locking ring oscillator |
| CN104581094A (en) * | 2014-12-16 | 2015-04-29 | 河南铭视安防工程有限公司 | Video optical transceiver and detecting method thereof |
| CN106209088A (en) * | 2016-06-30 | 2016-12-07 | 中国科学技术大学 | A kind of high energy efficiency orthogonal two-divider of high accuracy |
| CN106209088B (en) * | 2016-06-30 | 2018-11-02 | 中国科学技术大学 | A kind of orthogonal two-divider of high energy efficiency high-precision |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130619 |