CN106209088B - A kind of orthogonal two-divider of high energy efficiency high-precision - Google Patents
A kind of orthogonal two-divider of high energy efficiency high-precision Download PDFInfo
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- CN106209088B CN106209088B CN201610518127.1A CN201610518127A CN106209088B CN 106209088 B CN106209088 B CN 106209088B CN 201610518127 A CN201610518127 A CN 201610518127A CN 106209088 B CN106209088 B CN 106209088B
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- 230000011664 signaling Effects 0.000 description 2
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- 230000007812 deficiency Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
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- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a kind of orthogonal two-dividers of high energy efficiency high-precision, it is characterized in that connecting into loop by the first orthogonal cells and the second orthogonal cells；First orthogonal cells and the second orthogonal cells are controlled by differential input clock signal simultaneously, connection type and control sequential of the differential input clock signal in the first orthogonal cells and the second orthogonal cells are opposite each other, orthogonal two divided-frequency signal is obtained in the positive output end OUT1 and negative output terminal OUTB1 of the first orthogonal cells, and in the positive output end OUT2 and negative output terminal OUTB2 of the second orthogonal cells.The present invention is based on digital circuit structures, do not use passive device and tail current source, with high energy efficiency can obtain high-speed transitions at low supply voltages, and have technological flexibility and portability.
Description
Technical field
The present invention relates to number and technical field of radio frequency integrated circuits more particularly to a kind of orthogonal two-dividers.
Background technology
Frequency divider (Frequency Divider, FD) is widely used, for example is used for dividing in phaselocked loop (PLL) loop
The output signal of voltage controlled oscillator (VCO) is allowed to be equal to reference frequency, to reach loop-locking；It is used in transceiver
Accurate quadrature carrier signals are generated, inphase-quadrature modem is carried out to signal.
Traditional orthogonal two-divider based on Source Coupled Logic (SCL) structure is as shown in Figure 5.The structure is complete by two
Exactly the same SCL D-flip flops cascade, and conversion speed is fast, but its power consumption is very big；Tail current source in SCL D-flip flops is
In order to ensure the more stable direct current biasing of circuit, but minimum power supply voltage, is limited, if directly removing tail current source can lead
Send a telegraph increase of the road to the dependence of flow-route and temperature；In addition, the ohmic load of SCL D-flip flops has inaccuracy and domain
Although the big disadvantage of area will increase parasitic capacitance, and then limit the structure in this way it is contemplated that replaced using active load
The maximum operating frequency of orthogonal two-divider.
Invention content
The present invention be to avoid above-mentioned deficiency of the prior art, provide it is a kind of it is simple and compact for structure, without
The orthogonal signalling of passive device and tail current source, output have the high-precision orthogonal two-divider of high-precision high energy efficiency.
The present invention is to solve technical problem to adopt the following technical scheme that：
The high energy efficiency orthogonal two-divider of high-precision of the present invention is structurally characterized in that：By the first orthogonal cells and the second positive presentate
Member connects into loop；The loop refer to the positive output end OUT1 and negative output terminal OUTB1 of the first orthogonal cells correspondingly
It is separately connected the negative input end INB2 and positive input terminal IN2 of the second orthogonal cells, the positive output end of second orthogonal cells
OUT2 and negative output terminal OUTB2 connects the positive input terminal IN1 and negative input end INB1 of the first orthogonal cells correspondingly；
First orthogonal cells and the second orthogonal cells are controlled by differential input clock signal simultaneously, the difference
Connection type and control sequential of the input clock signal in the first orthogonal cells and the second orthogonal cells are each other on the contrary, described
The positive output end OUT1 and negative output terminal OUTB1 of first orthogonal cells, and the positive output end in second orthogonal cells
OUT2 and negative output terminal OUTB2 obtain orthogonal two divided-frequency signal.
The design feature of the orthogonal two-divider of high energy efficiency of the present invention high-precision is lain also in：First orthogonal cells and second
Orthogonal cells have following identical structure type：By the first dynamic inverter and the second dynamic inverter in a pair of of Differential Input
Pseudo-differential dynamic inverter is formed under clock signal control, in the output of first dynamic inverter and the second dynamic inverter
One CMOS inverter type latch is set between end.
The design feature of the orthogonal two-divider of high energy efficiency of the present invention high-precision is lain also in：The dynamic inverter is by first
PMOS tube (P1) and the first NMOS tube (N1) constitute CMOS inverter, in the output node (A) and first of the CMOS inverter
Second PMOS tube of connecting between PMOS tube (P1) (P2), in output node (A) and the first NMOS tube of the CMOS inverter
(N1) the second NMOS tube of connecting between (N2), with the pair of differential input clock signal for second PMOS tube (P2) and
The grid voltage of second NMOS tube (N2).
Compared with the prior art, the present invention has the beneficial effect that：
The present invention realizes orthogonal two divided-frequency using pseudo-differential dynamic inverter structure, and simple and compact for structure, output is just
Hand over signal that there is high-precision；Compared to orthogonal two-divider of the tradition based on Source Coupled Logic SCL structures, the present invention is based on numbers
Circuit structure does not use passive device and tail current source, with high energy efficiency can obtain high-speed transitions at low supply voltages, simultaneously
With technological flexibility and portability.
Description of the drawings
Fig. 1 is the high-precision orthogonal two-divider structural schematic diagram of high energy efficiency of the present invention；
Fig. 2 is orthogonal cells electrical block diagram in the orthogonal two-divider of the present invention；
Fig. 3 is dynamic inverter electrical block diagram in the orthogonal two-divider of the present invention；
Fig. 4 is the orthogonal signal waveforms figure of the orthogonal two-divider output of the present invention；
Fig. 5 is the existing orthogonal two-divider structural schematic diagram based on Source Coupled Logic SCL.
Specific implementation mode
Referring to Fig. 1, the orthogonal two-divider of high energy efficiency high-precision is orthogonal by the first orthogonal cells and second in the present embodiment
Unit connects into loop；Loop refers to that the positive output end OUT1 and negative output terminal OUTB1 of the first orthogonal cells divide correspondingly
The negative input end INB2 and positive input terminal IN2, the positive output end OUT2 of second orthogonal cells of the second orthogonal cells are not connected
Connect the positive input terminal IN1 and negative input end INB1 of the first orthogonal cells correspondingly with negative output terminal OUTB2.
The first orthogonal cells and the second orthogonal cells are simultaneously by differential input clock signal CLK and CLKB in the present embodiment
Control, connection types and control of the differential input clock signal CLK and CLKB in the first orthogonal cells and the second orthogonal cells
Sequential processed each other on the contrary, the first orthogonal cells positive output end OUT1 and negative output terminal OUTB1, and in the second orthogonal cells
Positive output end OUT2 and negative output terminal OUTB2 obtain orthogonal two divided-frequency signal OUT0, OUT90, OUT180 as shown in Figure 4 and
OUT270。
In specific implementation, as shown in Fig. 2, the first orthogonal cells and the second orthogonal cells have following identical structure shape
Formula：Pseudo-differential dynamic is formed under the control of a pair of of differential input clock signal by the first dynamic inverter and the second dynamic inverter
A CMOS inverter type lock is arranged in phase inverter between first dynamic inverter and the output end of the second dynamic inverter
Storage.
As shown in figure 3, dynamic inverter is to constitute CMOS by the first PMOS tube P1 and the first NMOS tube N1 in the present embodiment
Phase inverter, connect the second PMOS tube P2 between the output node A and the first PMOS tube P1 of CMOS inverter, in CMOS inverter
Output node A and the first NMOS tube N1 between connect the second NMOS tube N2, a pair of of differential input clock signal is for controlling the
The grid voltage of two PMOS tube P2 and the second NMOS tube N2.
The present embodiment utilizes the CMOS technology realization of 40nm, supply voltage VDD=1.1V, entire orthogonal two-divider power consumption
For 313 μ W, differential signal CLK and the CLKB frequency of input is 10GHz, orthogonal two divided-frequency signal OUT0, OUT90 of output,
The centre frequency of OUT180 and OUT270 is 5GHz.
The circuit structure of base in this present embodiment is tested, and high-precision orthogonal two points of high energy efficiency shown in Fig. 4 is obtained
The orthogonal signal waveforms figure of frequency device output, orthogonal signalling OUT0, OUT90, OUT180 and OUT270 of orthogonal two-divider output
Average phase error in the vicinity output frequency 5GHz is zero.
Claims (3)
1. a kind of orthogonal two-divider, it is characterized in that：Loop is connected by the first orthogonal cells and the second orthogonal cells；The ring
Road refers to that the positive output end OUT1 and negative output terminal OUTB1 of the first orthogonal cells are separately connected the second orthogonal cells correspondingly
Negative input end INB2 and positive input terminal IN2, the positive output end OUT2 and negative output terminal OUTB2 of second orthogonal cells are one by one
The positive input terminal IN1 and negative input end INB1 of correspondingly connected first orthogonal cells；
First orthogonal cells and the second orthogonal cells are controlled by differential input clock signal simultaneously, the Differential Input
Connection type and control sequential of the clock signal in the first orthogonal cells and the second orthogonal cells are each other on the contrary, described first
The positive output end OUT1 and negative output terminal OUTB1 of orthogonal cells, and second orthogonal cells positive output end OUT2 and
Negative output terminal OUTB2 obtains orthogonal two divided-frequency signal.
2. orthogonal two-divider according to claim 1, it is characterized in that：First orthogonal cells and the second orthogonal cells
With following identical structure type：By the first dynamic inverter and the second dynamic inverter in a pair of of differential input clock signal
Pseudo-differential dynamic inverter is formed under control, is set between first dynamic inverter and the output end of the second dynamic inverter
Set a CMOS inverter type latch.
3. orthogonal two-divider according to claim 2, it is characterized in that：The dynamic inverter is by the first PMOS tube
(P1) and the first NMOS tube (N1) constitutes CMOS inverter, in output node (A) and the first PMOS tube of the CMOS inverter
(P1) the second PMOS tube of connecting between (P2), between the output node (A) and the first NMOS tube (N1) of the CMOS inverter
Second NMOS tube of connecting (N2) is used for second PMOS tube (P2) and the 2nd NMOS with the pair of differential input clock signal
Manage the grid voltage of (N2).
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| CN106209088B true CN106209088B (en) | 2018-11-02 |
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| CN203014773U (en) * | 2012-12-28 | 2013-06-19 | 河南中多科技发展有限公司 | Digital signal processing system |
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| US8618967B2 (en) * | 2012-03-30 | 2013-12-31 | Broadcom Corporation | Systems, circuits, and methods for a sigma-delta based time to digital converter |
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