CN109698803B - Circuit structure for realizing FSK signal high-efficiency demodulation in wireless charging equipment - Google Patents
Circuit structure for realizing FSK signal high-efficiency demodulation in wireless charging equipment Download PDFInfo
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- CN109698803B CN109698803B CN201710983836.1A CN201710983836A CN109698803B CN 109698803 B CN109698803 B CN 109698803B CN 201710983836 A CN201710983836 A CN 201710983836A CN 109698803 B CN109698803 B CN 109698803B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
- H02J50/80—Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
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Abstract
The invention relates to a circuit structure for realizing efficient demodulation of FSK signals in wireless charging equipment, which comprises a data sampling module, a period point counting module, a direct current filtering module and a period point processing module, wherein the input end of the period point counting module is connected with the output end of the data sampling module, the input end of the direct current filtering module is connected with the output end of the period point counting module, and the input end of the period point processing module is connected with the output end of the direct current filtering module. By adopting the circuit structure, the demodulation circuit only adopts a 2M clock to process data, high-efficiency demodulation can be realized when an input signal is very poor, the unpacking rate is greatly improved, meanwhile, a negative direct current circuit is adopted in the direct current filtering module, the multiplier of the original negative direct current circuit is replaced by two shift registers and an adder, hardware resources are greatly saved, and the demodulation of the FSK signal is more efficient and has a wide application range.
Description
Technical Field
The invention relates to the technical field of wireless charging, in particular to the technical field of wireless charging communication, and particularly relates to a circuit structure for realizing efficient demodulation of FSK signals in wireless charging equipment.
Background
The wireless charging device using Qi standard transmits power by means of 2FSK (binary frequency shift keying), and the signal received by the energy receiving end in the wireless charging system is an inductively coupled signal, so that the signal received by the wireless charging system is not a single-frequency sinusoidal signal, but may be doped with a lot of high-frequency noise. At present, because the wireless charging technology is in a starting stage, the FSK signal demodulation circuits aiming at the Qi standard wireless charging equipment are not much, the existing FSK demodulation circuits are all aiming at common FSK signals, and the traditional 2FSK demodulation method mainly comprises three modes of coherent demodulation, filtering incoherent demodulation and orthogonal multiplication incoherent demodulation.
In the Qi standard communication protocol, a period difference between the carrier frequency Fop and the modulation frequency Fmod is specified for ensuring the stability of the transmission energy, namely 282ns at maximum and 32ns at minimum. If demodulation is performed using conventional methods, the overall system requires very high precision to resolve the different frequencies, which increases the overhead of the overall circuit, either in analog or digital fashion. Meanwhile, the carrier frequency Fop in different communication stages of the same system can be any value between 110 and 205KHz, so that the cost of the whole demodulation circuit is greatly increased.
Disclosure of Invention
It is an object of the present invention to overcome at least one of the above-mentioned drawbacks of the prior art and to provide a circuit configuration that enables efficient demodulation of FSK signals in a wireless charging device.
In order to achieve the above object, a circuit configuration for realizing efficient demodulation of FSK signals in a wireless charging device of the present invention has the following constitution:
the circuit structure for realizing FSK signal high-efficiency demodulation in the wireless charging equipment comprises:
the data sampling module is used for receiving the original data from the coil, smoothing the original data and sampling the number of the period points in the data;
the periodic point counting module is used for calculating the sum of periodic points, and the input end of the periodic point counting module is connected with the output end of the data sampling module;
the direct current filtering module is used for filtering the forward direct current component, and the input end of the direct current filtering module is connected with the output end of the periodic point counting module;
and the periodic point number processing module is used for carrying out smoothing processing on the data again, carrying out data bit judgment and outputting a demodulated FSK signal, and the input end of the periodic point number processing module is connected with the output end of the direct current filtering module.
The data sampling module of the circuit structure for realizing the FSK signal high-efficiency demodulation algorithm in the wireless charging equipment comprises:
a receiving coil for receiving a signal from the transmitter;
the first comparator is used for receiving the original data from the receiving coil, comparing the original data with a reference potential, sampling the output signal of the receiving coil through 2MHz frequency and inputting the sampled output signal to the first input end of the first comparator, and connecting the second input end of the first comparator with the reference potential;
the first low-pass filter is used for carrying out smoothing processing on data, the input end of the first low-pass filter is connected with the output end of the first comparator, and the output end of the first low-pass filter sends the filtered data to the high-frequency sampling unit;
the high-frequency sampling unit is used for detecting and sampling the number of the period points according to the rising edge, the input end of the high-frequency sampling unit is connected with the first low-pass filter, and the output end of the high-frequency sampling unit is connected with the input end of the period point counting module.
The first low-pass filter of the circuit structure for realizing the efficient demodulation of the FSK signal in the wireless charging equipment is a 2-order IIR low-pass filter, the cut-off frequency of the low-pass filter is 5KHz, and the sampling frequency is 2MHz.
The periodic point counting module of the circuit structure for realizing high-efficiency demodulation of FSK signals in the wireless charging equipment comprises a first inverter, a first AND gate circuit, a first subtracter, a first selector, a first adder and a second adder, wherein a rising edge signal is input to a first input end of the first AND gate circuit, a second input end of the first AND gate circuit is connected with an output end of the first inverter, an output end of the first AND gate circuit is connected with an enabling end of the first selector, the enabling end of the first selector is also connected with an output end of a gating control signal, an output end of the first subtracter is connected with a first input end of the first adder, a feedback control end of the first selector is connected with a second input end of the first adder, a second input end of the first selector is connected with an output end of the first adder, the second input end of the first selector is connected with an enabling end of the first adder, and when the data of the first adder is greater than or equal to the data of the first adder and the first adder when the data of the first adder is sampled by the data sampling module.
The direct current filter module of the circuit structure for realizing high-efficiency demodulation of FSK signals in the wireless charging equipment comprises a first direct current filter removing circuit and a direct current adding and subtracting circuit, wherein the first direct current filter removing circuit comprises a first data buffer, a second subtracter, a first shift register, a third adder, a third subtracter, a second shift register, a third shift register and a second comparator, the first data buffer outputs buffer data at the m moment and buffer data at the n moment, m and n are different values, the second data buffer outputs first buffer data, the first input end of the second subtracter inputs buffer data at the m moment, the second input end of the second subtracter inputs buffer data at the n moment, the input end of the first shift register is connected with the output end of the second subtracter, the input end of the third shift register is input with the first adder, the output end of the first shift register is connected with the output end of the third adder, the output end of the third subtracter is connected with the output end of the third adder, and the output end of the third subtracter is connected with the output end of the third adder.
The negative adding direct current circuit for realizing the efficient demodulation of the FSK signal in the wireless charging equipment comprises a fourth adder, a fourth shift register, a fifth shift register and a fifth adder, wherein the first input end of the fourth adder is connected with the output end of the first low-pass filter, the second input end of the fourth adder inputs a first constant value-200, the first output end of the fourth adder is connected with the input end of the fourth shift register, the second output end of the fourth adder is connected with the input end of the fifth shift register, the first input end of the fifth adder is connected with the output end of the fourth shift register, and the second input end of the fifth adder is connected with the output end of the fifth shift register.
The first shift register of the circuit structure for realizing the high-efficiency demodulation of the FSK signal in the wireless charging equipment is a 10-bit left shift register, and the second shift register and the third shift register are both 10-bit right shift registers.
The fourth shift register of the circuit structure for realizing the high-efficiency demodulation of the FSK signal in the wireless charging equipment is a 1-bit left shift register, and the fifth shift register is a 3-bit left shift register.
The periodic point number processing module of the circuit structure for realizing the FSK signal high-efficiency demodulation in the wireless charging equipment comprises:
the second low-pass filter is used for carrying out smoothing treatment on the data after the negative direct current circuit is added, and the input end of the second low-pass filter is connected with the output end of the direct current filter module;
the second DC removing filter circuit is used for filtering the DC component of the data passing through the second low-pass filter, and the input end of the second DC removing filter circuit is connected with the output end of the second low-pass filter;
the frequency jitter elimination unit is used for eliminating the jitter part of the data passing through the second DC eliminating filter circuit, and the input end of the frequency jitter elimination unit is connected with the output end of the second DC eliminating filter circuit;
the waveform modifying unit is used for modifying the output waveform within a certain numerical range, the output end of the frequency jitter eliminating unit is connected with the control end of the waveform modifying unit, and the output end of the waveform modifying unit is the output end of the demodulation circuit.
The second low-pass filter of the circuit structure for realizing the efficient demodulation of the FSK signal in the wireless charging equipment is a 2-order IIR low-pass filter.
The frequency jitter elimination unit of the circuit structure for realizing the high-efficiency demodulation of the FSK signal in the wireless charging equipment comprises a first absolute value taking subunit and a third comparator, wherein the input end of the first absolute value taking subunit is connected with the output end of the second low-pass filter, the first input end of the third comparator is connected with the output end of the first absolute value taking subunit, and the second output end of the third comparator inputs a second constant value.
The waveform modifying unit of the circuit structure for realizing the efficient demodulation of the FSK signal in the wireless charging equipment is a second selector, the input end of the second selector is connected with the output end of the third comparator, and the output end of the second selector is the output end of the circuit structure.
By adopting the circuit structure for realizing the high-efficiency demodulation of the FSK signal in the wireless charging equipment, the demodulation circuit adopts the method described in the cycle point counting module, the direct current filtering module and the cycle point processing module, so that the demodulation circuit can realize the high-efficiency demodulation by only adopting a 2M clock to process data, and even if an input signal is poor, the high-efficiency demodulation can be accurately carried out, and the unpacking rate (the number of correct unpacking) is greatly improved; meanwhile, a first DC removing filter circuit and a plus-minus DC circuit are adopted in the DC filter module, DC components are filtered, and particularly in the plus-minus DC circuit, a multiplier of the original plus-minus DC circuit is replaced by two shift registers and an adder, so that hardware resources are greatly saved, the demodulation of FSK signals is more efficient, and the application range is wide.
Drawings
Fig. 1 is a schematic diagram of a circuit structure for implementing FSK signal efficient demodulation in a wireless charging device according to the present invention.
Fig. 2 is a circuit diagram of a first low-pass filter of a circuit structure for realizing efficient demodulation of FSK signals in the wireless charging device of the present invention.
Fig. 3 is a schematic structural diagram of a high-frequency sampling unit of a circuit structure for implementing FSK signal high-efficiency demodulation in the wireless charging device of the present invention.
Fig. 4 is a circuit diagram of a cycle count module of a circuit structure for implementing efficient demodulation of FSK signals in a wireless charging device according to the present invention.
Fig. 5 is a schematic structural diagram of a first dc-dc removing filter circuit of a circuit structure for implementing FSK signal efficient demodulation in a wireless charging device according to the present invention.
Fig. 6 is a schematic diagram of a negative dc circuit of a circuit structure for implementing FSK signal efficient demodulation in a wireless charging device according to the present invention.
Fig. 7 is a circuit diagram of a second low-pass filter of the circuit structure for realizing efficient demodulation of FSK signals in the wireless charging device of the present invention.
Fig. 8 is a circuit diagram of a cycle count processing module of a circuit structure for implementing FSK signal efficient demodulation in the wireless charging device of the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
In a possible implementation manner, the circuit structure for implementing FSK signal efficient demodulation in the wireless charging device includes:
the data sampling module is used for receiving the original data from the coil, smoothing the original data and sampling the number of the period points in the data;
the periodic point counting module is used for calculating the sum of periodic points, and the input end of the periodic point counting module is connected with the output end of the data sampling module;
the direct current filtering module is used for filtering the forward direct current component, and the input end of the direct current filtering module is connected with the output end of the periodic point counting module;
and the periodic point number processing module is used for carrying out smoothing processing on the data again, carrying out data bit judgment and outputting a demodulated FSK signal, and the input end of the periodic point number processing module is connected with the output end of the direct current filtering module.
The data sampling module of the circuit structure for realizing the FSK signal high-efficiency demodulation algorithm in the wireless charging equipment comprises:
a receiving coil for receiving a signal from the transmitter;
the first comparator is used for receiving the original data from the receiving coil, comparing the original data with a reference potential, sampling the output signal of the receiving coil through 2MHz frequency and inputting the sampled output signal to the first input end of the first comparator, and connecting the second input end of the first comparator with the reference potential;
the first low-pass filter is used for carrying out smoothing processing on data, the input end of the first low-pass filter is connected with the output end of the first comparator, and the output end of the first low-pass filter sends the filtered data to the high-frequency sampling unit;
the high-frequency sampling unit is used for detecting and sampling the number of the period points according to the rising edge, the input end of the high-frequency sampling unit is connected with the first low-pass filter, and the output end of the high-frequency sampling unit is connected with the input end of the period point counting module.
The first low-pass filter of the circuit structure for realizing the efficient demodulation of the FSK signal in the wireless charging equipment is a 2-order IIR low-pass filter, the cut-off frequency of the low-pass filter is 5KHz, and the sampling frequency is 2MHz.
The periodic point counting module of the circuit structure for realizing high-efficiency demodulation of FSK signals in the wireless charging equipment comprises a first inverter, a first AND gate circuit, a first subtracter, a first selector, a first adder and a second adder, wherein a rising edge signal is input to a first input end of the first AND gate circuit, a second input end of the first AND gate circuit is connected with an output end of the first inverter, an output end of the first AND gate circuit is connected with an enabling end of the first selector, the enabling end of the first selector is also connected with an output end of a gating control signal, an output end of the first subtracter is connected with a first input end of the first adder, a feedback control end of the first selector is connected with a second input end of the first adder, a second input end of the first selector is connected with an output end of the first adder, the second input end of the first selector is connected with an enabling end of the first adder, and when the data of the first adder is greater than or equal to the data of the first adder and the first adder when the data of the first adder is sampled by the data sampling module.
The direct current filter module of the circuit structure for realizing high-efficiency demodulation of FSK signals in the wireless charging equipment comprises a first direct current filter removing circuit and a direct current adding and subtracting circuit, wherein the first direct current filter removing circuit comprises a first data buffer, a second subtracter, a first shift register, a third adder, a third subtracter, a second shift register, a third shift register and a second comparator, the first data buffer outputs buffer data at the m moment and buffer data at the n moment, m and n are different values, the second data buffer outputs first buffer data, the first input end of the second subtracter inputs buffer data at the m moment, the second input end of the second subtracter inputs buffer data at the n moment, the input end of the first shift register is connected with the output end of the second subtracter, the input end of the third shift register is input with the first adder, the output end of the first shift register is connected with the output end of the third adder, the output end of the third subtracter is connected with the output end of the third adder, and the output end of the third subtracter is connected with the output end of the third adder.
The negative adding direct current circuit for realizing the efficient demodulation of the FSK signal in the wireless charging equipment comprises a fourth adder, a fourth shift register, a fifth shift register and a fifth adder, wherein the first input end of the fourth adder is connected with the output end of the first low-pass filter, the second input end of the fourth adder inputs a first constant value-200, the first output end of the fourth adder is connected with the input end of the fourth shift register, the second output end of the fourth adder is connected with the input end of the fifth shift register, the first input end of the fifth adder is connected with the output end of the fourth shift register, and the second input end of the fifth adder is connected with the output end of the fifth shift register.
The first shift register of the circuit structure for realizing the high-efficiency demodulation of the FSK signal in the wireless charging equipment is a 10-bit left shift register, and the second shift register and the third shift register are both 10-bit right shift registers.
The fourth shift register of the circuit structure for realizing the high-efficiency demodulation of the FSK signal in the wireless charging equipment is a 1-bit left shift register, and the fifth shift register is a 3-bit left shift register.
The periodic point number processing module of the circuit structure for realizing the FSK signal high-efficiency demodulation in the wireless charging equipment comprises:
the second low-pass filter is used for carrying out smoothing treatment on the data after the negative direct current circuit is added, and the input end of the second low-pass filter is connected with the output end of the direct current filter module;
the second DC removing filter circuit is used for filtering the DC component of the data passing through the second low-pass filter, and the input end of the second DC removing filter circuit is connected with the output end of the second low-pass filter;
the frequency jitter elimination unit is used for eliminating the jitter part of the data passing through the second DC eliminating filter circuit, and the input end of the frequency jitter elimination unit is connected with the output end of the second DC eliminating filter circuit;
the waveform modifying unit is used for modifying the output waveform within a certain numerical range, the output end of the frequency jitter eliminating unit is connected with the control end of the waveform modifying unit, and the output end of the waveform modifying unit is the output end of the demodulation circuit.
The second low-pass filter of the circuit structure for realizing the efficient demodulation of the FSK signal in the wireless charging equipment is a 2-order IIR low-pass filter.
The frequency jitter elimination unit of the circuit structure for realizing the high-efficiency demodulation of the FSK signal in the wireless charging equipment comprises a first absolute value taking subunit and a third comparator, wherein the input end of the first absolute value taking subunit is connected with the output end of the second low-pass filter, the first input end of the third comparator is connected with the output end of the first absolute value taking subunit, and the second output end of the third comparator inputs a second constant value.
The waveform modifying unit of the circuit structure for realizing the efficient demodulation of the FSK signal in the wireless charging equipment is a second selector, the input end of the second selector is connected with the output end of the third comparator, and the output end of the second selector is the output end of the circuit structure.
In a more specific embodiment, as shown in fig. 1, in the whole FSK communication process, in order to ensure that the jitter of the waveform of the input signal does not affect the following decoding algorithm, the signal on the coil enters the chip, after passing through the comparator, the output value of the comparator is read through 2MHz frequency, then the value can be regarded as 1bit sampling data of 2MHz, the data is passed through the low-pass filter 1 to filter the jitter waveform with higher frequency, then the number of the period points is counted, the values of 256 sampling points are added up, the signal is subjected to direct current removal through the first direct current removing filter circuit, then is subjected to data smoothing through the negative direct current adding module, then is subjected to data smoothing through the low-pass filter 2, and finally, the output of the low-pass filter is subjected to data bit judgment, and 0 or 1 is output.
(1) Low-pass filter 1
Fig. 2 is a circuit diagram of a first low-pass filter of a circuit structure for implementing FSK signal high-efficiency demodulation in the wireless charging device according to the present invention, in order to smooth a curve output by a comparator, to eliminate amplitude abrupt points in an original signal, a 2-order IIR low-pass filter LPF1 is used for processing. This filter comprises 6 coefficients, which need to be 8bit spotted and correspondingly optimized.
In the calculation, 3 8 multiplied operations, 5 8+8 added operations and 3 filter coefficients required to be stored are obtained, and two 8bit intermediate variable storage buffers are also provided
(2) Referring to fig. 3, which is a schematic diagram of a high-frequency sampling unit of a circuit structure for implementing FSK signal high-efficiency demodulation in the wireless charging device of the present invention, a counter t_counter is used to count the number of output data of a filter LPF1, and once the output of the filter LPF1 is changed from 0 to 1, a rising edge occurs, the value of the counter t_counter is output, and is reassigned to 1.
In the present system, the counter t_counter will always count at a fixed frequency of 2MHz, with a length of 5 bits, since 2MHz/110 khz=18.2, this value is less than 32, and this counter does not take into account the overflow process: because the following two conditions may occur once the t_counter overflows the specification: 1) No signal is generated on the coil for a long time; 2) The period of the signal on the coil is too long; both cases the chip should be in an abnormal operating state.
(3) Cycle point number and calculation
Referring to fig. 4, a circuit diagram of a cycle count module of a circuit structure for implementing FSK signal high-efficiency demodulation in a wireless charging device according to the present invention is shown, if a counter t_counter has an output, a sum of points of 256 recent cycles is calculated first, then the output value is stored in a cycle count buffer, and then a sum of buffer members, sumTbuff, is calculated with 256 as a window, and then the SumTbuff is processed later. The synchronous FIFO is used here to control the writing and reading of t_counter. When the initial data is less than 256, the T_counter is accumulated and written into the FIFO, and when the number of the T_counters is greater than 256, the first data in the FIFO is read out and subtracted in the SumTiff before the data is written.
(4) Removing DC and adding negative DC
Referring to fig. 5 and fig. 6, which are respectively a schematic structural diagram of a first DC-removing filter circuit and a schematic structural diagram of a negative DC-adding circuit for implementing efficient demodulation of FSK signals in the wireless charging device of the present invention, the output of the cycle count and counting module firstly filters the positive DC component through DC Blocking (DC-removing filter), then adds a negative DC to the positive DC component and amplifies the signal, so that the signal is negative as a whole.
The negative dc adding section adds the output of the first dc removing filter circuit to-200 and then multiplies by 10, which is replaced by two shifts and an adder in order to save hardware resources.
(5) Low-pass filter 2
Referring to fig. 7, a circuit diagram of a second low-pass filter of a circuit structure for implementing FSK signal high-efficiency demodulation in the wireless charging device of the present invention is shown, the purpose of the low-pass filter 2 is to perform a smoothing process on output data, the update frequency of input data is Fop or Fmod, the low-pass filter 2 is designed when the maximum value of the input data is 205KHz, the low-pass filter 2 is a 2-order IIR low-pass filter, and the coefficients can be fixed at 16 bits and optimized correspondingly.
In the implementation process of the low-pass filter 2, an input signal is firstly shifted left by 8 bits to be expanded into a 23bit signal, four 23×16 multiplication operations are performed in the specific operation process, four 23+23 addition operations are performed, 4 filter coefficients are required to be stored, and two 23bit intermediate variable storage buffers are also provided
(6) Cycle point and process
Referring to fig. 8, a circuit diagram of a cycle count processing module of a circuit structure for implementing FSK signal high-efficiency demodulation in a wireless charging device according to the present invention is shown, where l_dc_out2 is an output of a second stage DC module, and after taking an absolute value, the output is compared with a constant const, if l_dc_out2 is greater than const, l_clip_sum is 0, otherwise l_clip_sum is l_dc_out2, and l_clip_sum is used for data determination of a decoding module. The periodic point number processing module is used for eliminating frequency jitter and returning the near zero part to zero.
The circuit structure for realizing the efficient demodulation of the FSK signal in the wireless charging equipment is adopted, and the method described in the cycle point counting module, the direct current filtering module and the cycle point processing module is adopted in the demodulation circuit, so that the efficient demodulation can be realized by only adopting a 2M clock to process data in the demodulation circuit, even if an input signal is poor, the accurate demodulation can be carried out, and the unpacking rate (the number of correct unpacking) is greatly improved; meanwhile, a first DC removing filter circuit and a plus-minus DC circuit are adopted in the DC filter module, DC components are filtered, and particularly in the plus-minus DC circuit, a multiplier of the original plus-minus DC circuit is replaced by two shift registers and an adder, so that hardware resources are greatly saved, the demodulation of FSK signals is more efficient, and the application range is wide.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (11)
1. A circuit structure for realizing FSK signal high-efficiency demodulation algorithm in wireless charging equipment is characterized in that the circuit structure comprises:
the data sampling module is used for receiving the original data from the coil, smoothing the original data and sampling the number of the period points in the data;
the periodic point counting module is used for calculating the sum of periodic points, and the input end of the periodic point counting module is connected with the output end of the data sampling module;
the direct current filtering module is used for filtering the forward direct current component, and the input end of the direct current filtering module is connected with the output end of the periodic point counting module;
the periodic point number processing module is used for carrying out smoothing processing on the data again, carrying out data bit judgment and outputting a demodulated FSK signal, and the input end of the periodic point number processing module is connected with the output end of the direct current filtering module;
the direct current filtering module comprises a first direct current removing filtering circuit and a negative direct current adding circuit, the first direct current removing filtering circuit comprises a first data buffer, a second subtracter, a first shift register, a third adder, a third subtracter, a second shift register, a third shift register and a second comparator, the first data buffer outputs buffer data at the m moment and buffer data at the n moment, the m and the n are different values, the second data buffer outputs first buffer data, the first input end of the second subtracter is connected with the buffer data at the m moment, the second input end of the second subtracter is connected with the buffer data at the n moment, the input end of the first shift register is connected with the output end of the second subtracter, the input end of the third shift register is connected with the first buffer data at the m moment, the first input end of the third adder is connected with the output end of the third subtracter, the output end of the third subtracter is connected with the output end of the third adder is connected with the output end of the third subtracter, and the output end of the third subtracter is connected with the output end of the third adder.
2. The circuit structure for implementing an FSK signal efficient demodulation algorithm in a wireless charging apparatus according to claim 1, wherein the data sampling module comprises:
a receiving coil for receiving a signal from the transmitter;
the first comparator is used for receiving the original data from the receiving coil, comparing the original data with a reference potential, sampling the output signal of the receiving coil through 2MHz frequency and inputting the sampled output signal to the first input end of the first comparator, and connecting the second input end of the first comparator with the reference potential;
the first low-pass filter is used for carrying out smoothing processing on data, the input end of the first low-pass filter is connected with the output end of the first comparator, and the output end of the first low-pass filter sends the filtered data to the high-frequency sampling unit;
the high-frequency sampling unit is used for detecting and sampling the number of the period points according to the rising edge, the input end of the high-frequency sampling unit is connected with the first low-pass filter, and the output end of the high-frequency sampling unit is connected with the input end of the period point counting module.
3. The circuit structure for implementing FSK signal efficient demodulation in a wireless charging device according to claim 2, wherein the first low pass filter is a 2 nd order IIR low pass filter, the cut-off frequency of the low pass filter is 5KHz, and the sampling frequency is 2MHz.
4. The circuit structure for implementing FSK signal high efficiency demodulation in a wireless charging device according to claim 1, wherein said cycle point counting module comprises a first inverter, a first and gate, a first subtractor, a first selector, a first adder and a second adder, said first and gate first input is connected to a rising edge signal, said first and gate second input is connected to said first inverter output, said first and gate output is connected to said first selector enable, said first selector enable is further connected to a strobe control signal output, said first subtractor output is connected to said first input, said first selector feedback control is connected to said first adder second input, said first selector first input is connected to said first adder output, said first selector first input is connected to said first adder first data output is equal to said first and said first adder second adder output, said first and second adder output is equal to said first adder output data output, said first and said first adder output is sampled when said first and said first adder output is equal to said first adder output data output.
5. The circuit structure for implementing FSK signal high efficiency demodulation in a wireless charging device according to claim 2, wherein said negative dc adding circuit comprises a fourth adder, a fourth shift register, a fifth shift register and a fifth adder, said fourth adder having a first input connected to said output of said first low pass filter, a second input of said fourth adder having a first constant value-200, a first output of said fourth adder connected to said input of said fourth shift register, a second output of said fourth adder connected to said input of said fifth shift register, a first input of said fifth adder connected to said output of said fourth shift register, and a second input of said fifth adder connected to said output of said fifth shift register.
6. The circuit structure for implementing FSK signal efficient demodulation in a wireless charging apparatus according to claim 1, wherein said first shift register is a 10-bit shift left register, and said second shift register and said third shift register are both 10-bit shift right registers.
7. The circuit structure for implementing FSK signal efficient demodulation in a wireless charging apparatus according to claim 5, wherein said fourth shift register is a 1-bit shift left register and said fifth shift register is a 3-bit shift left register.
8. The circuit structure for implementing FSK signal efficient demodulation in a wireless charging apparatus according to claim 1, wherein said cycle count processing module comprises:
the second low-pass filter is used for carrying out smoothing treatment on the data after the negative direct current circuit is added, and the input end of the second low-pass filter is connected with the output end of the direct current filter module;
the second DC removing filter circuit is used for filtering the DC component of the data passing through the second low-pass filter, and the input end of the second DC removing filter circuit is connected with the output end of the second low-pass filter;
the frequency jitter elimination unit is used for eliminating the jitter part of the data passing through the second DC eliminating filter circuit, and the input end of the frequency jitter elimination unit is connected with the output end of the second DC eliminating filter circuit;
the waveform modifying unit is used for modifying the output waveform within a certain numerical range, the output end of the frequency jitter eliminating unit is connected with the control end of the waveform modifying unit, and the output end of the waveform modifying unit is the output end of the demodulation circuit.
9. The circuit structure for implementing FSK signal efficient demodulation in a wireless charging device according to claim 8, wherein said second low pass filter is a 2 nd order IIR low pass filter.
10. The circuit structure for implementing FSK signal high efficiency demodulation in a wireless charging device according to claim 8, wherein said frequency debounce unit comprises a first absolute value taking subunit and a third comparator, said first absolute value taking subunit having its input connected to said second low pass filter output, said third comparator having its first input connected to said first absolute value taking subunit output, said third comparator having its second output input for inputting a second constant value.
11. The circuit structure for implementing FSK signal efficient demodulation in a wireless charging apparatus according to claim 10, wherein said waveform modification unit is a second selector, an input terminal of said second selector is connected to an output terminal of said third comparator, and an output terminal of said second selector is an output terminal of said circuit structure.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104218918A (en) * | 2013-05-30 | 2014-12-17 | 无锡华润矽科微电子有限公司 | Direct-current filter circuit for realizing ASIC (Application Specific Integrated Circuit) audio processing function |
| US9225568B1 (en) * | 2014-12-09 | 2015-12-29 | Freescale Semiconducotr, Inc. | FSK demodulator |
| CN105516040A (en) * | 2015-11-30 | 2016-04-20 | 无锡华润矽科微电子有限公司 | Low-consumption demodulation method for FSK signal in wireless charging equipment |
| CN105811590A (en) * | 2014-12-30 | 2016-07-27 | 无锡华润矽科微电子有限公司 | Method for realizing amplitude modulation signal demodulation and decoding in wireless charging device |
| CN106487424A (en) * | 2015-12-28 | 2017-03-08 | 无锡华润矽科微电子有限公司 | The demodulator circuit of fsk signal in wireless charging device |
| CN106532969A (en) * | 2016-11-03 | 2017-03-22 | 无锡华润矽科微电子有限公司 | Circuit structure realizing FSK signal efficient demodulation in wireless charging device |
-
2017
- 2017-10-20 CN CN201710983836.1A patent/CN109698803B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104218918A (en) * | 2013-05-30 | 2014-12-17 | 无锡华润矽科微电子有限公司 | Direct-current filter circuit for realizing ASIC (Application Specific Integrated Circuit) audio processing function |
| US9225568B1 (en) * | 2014-12-09 | 2015-12-29 | Freescale Semiconducotr, Inc. | FSK demodulator |
| CN105811590A (en) * | 2014-12-30 | 2016-07-27 | 无锡华润矽科微电子有限公司 | Method for realizing amplitude modulation signal demodulation and decoding in wireless charging device |
| CN105516040A (en) * | 2015-11-30 | 2016-04-20 | 无锡华润矽科微电子有限公司 | Low-consumption demodulation method for FSK signal in wireless charging equipment |
| CN106487424A (en) * | 2015-12-28 | 2017-03-08 | 无锡华润矽科微电子有限公司 | The demodulator circuit of fsk signal in wireless charging device |
| CN106532969A (en) * | 2016-11-03 | 2017-03-22 | 无锡华润矽科微电子有限公司 | Circuit structure realizing FSK signal efficient demodulation in wireless charging device |
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