CN103178836A - Method, device and frequency spectrum analyzer for providing clock signals - Google Patents
Method, device and frequency spectrum analyzer for providing clock signals Download PDFInfo
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- CN103178836A CN103178836A CN2011104316349A CN201110431634A CN103178836A CN 103178836 A CN103178836 A CN 103178836A CN 2011104316349 A CN2011104316349 A CN 2011104316349A CN 201110431634 A CN201110431634 A CN 201110431634A CN 103178836 A CN103178836 A CN 103178836A
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Abstract
An embodiment of the invention provides a method, device and frequency spectrum analyzer for providing clock signals. The method is applied to a device with a radio frequency circuit and a digital circuit simultaneously, and the method includes: providing a system clock; acquiring the clock signals sent by the system clock; and sending one path of clock signal to the radio frequency circuit to be used, and sending another path of clock signal to the digital circuit to be used. The device is provided with the radio frequency circuit and the digital circuit simultaneously, the device only comprises the system clock for sending the clock signals, and one path of clock signal is sent to the radio frequency circuit to be used, and another path of clock signal is sent to the digital circuit to be used. The method, device and frequency spectrum analyzer for providing clock signals can solve interference problems and synchronization problems between the digital circuit and the radio frequency circuit and particularly solve interference problems and synchronization problems caused by the fact that a digital circuit and a radio frequency circuit in the field of wideband receivers are integrated on the same circuit board.
Description
Technical field
The present invention relates to the radio-frequency technique field, relate in particular to a kind of method, device and spectrum analyzer that clock signal is provided.
Background technology
In the radio-frequency communication field, coexist epoch of a system of digital circuit and radio frequency analog circuit are continuing and will continue, and in this case, digital circuit interference simulation circuit also will continue.especially in radio-frequency (RF) receiving circuit, radio-frequency front-end is highly sensitive, and the useful signal that receives is very faint, be easy to be disturbed by the switch high order harmonic component of digital circuit, and the interference of numerical portion circuit is unpredictable, it is uncorrelated namely disturbing, so usually in the circuit design process, digital circuit and radio frequency analog circuit are spaced from each other physically, as whole radio system is divided into digital circuit board and radio frequency circuit board, because physically-isolated reason, two boards is each clock separately of having used by oneself also, on market, existing DSA1030 series frequency spectrograph has just used this structure.
as shown in Figure 1, be existing DSA1030 spectrum analyzer system clock block diagram, be divided into radio frequency circuit board 1 and digital circuit board 2, radio frequency circuit board 1 radio circuit is synchronized with a clock 11, and the device of digital circuit board 2 processes due to data or the difference of transmission rate is used respectively different clocks, use clock 12 as data processing unit 122, and peripheral hardware 132 uses clock 13, peripheral hardware 142 uses clock 14, just used DSP (Digital Signal Processing as data processing unit 122 in DSA1030, Digital Signal Processing), the clock that needs 25MHz, peripheral hardware 132 is USB (Universal Serial BUS, USB) interface chip needs the clock signal of 12MHz, peripheral hardware 142 needs the clock signal of 25MHz for Ethernet chip, they have all used the relatively poor passive crystal oscillator of frequency stability.The isolation of physics is isolated from each other radio frequency circuit board 1 and digital circuit board 2, clock is also independent of one another, such benefit is that the physical separation of each clock and its effect device reduces, and clock PCB (Printed Circuit Board, printed circuit board (PCB)) line shortens.
Certain isolation physically can be good at stoping digital circuit interference simulation circuit, and still for the radio-frequency apparatus of small volume, the cost that this isolation physically brings and the increase of volume are difficult to tolerate, have also increased assembly difficulty.Also can occur when radio circuit and the mutual communication of digital circuit due to the asynchronous asynchronous problem that communication signal occurs of circuit both sides clock.
After the clock interference signal of digital signal is sneaked into analog circuit, because the digital dock phase noise is inferior to simulated clock simulation clock, so superposeing mutually, both cause final signal phase noise variation.
To sum up, for the interference problem between digital circuit and radio circuit and stationary problem, need at present solution badly.
Summary of the invention
The embodiment of the present invention provides a kind of method, device and spectrum analyzer that clock signal is provided, to solve interference problem and the stationary problem between digital circuit and radio circuit.
On the one hand, the embodiment of the present invention provides a kind of method that clock signal is provided, and described method is applied to exist simultaneously the device of radio circuit and digital circuit, and described method comprises: a system clock is provided; Obtain the clock signal that described system clock sends; Riches all the way gives described radio circuit and use with described clock signal, and send to described digital circuit to use on another road of described clock signal.
Optionally, in one embodiment of this invention, describedly obtain the clock signal that described system clock sends, comprising: by a plurality of clock driver circuits, described clock signal is told a plurality of with clock signals frequently.
Optionally, in one embodiment of this invention, described riches all the way gives described radio circuit and use with described clock signal, comprising: that will tell a plurality ofly carries out frequency synthesis with clock signals frequently through phase-locked loop and frequency mixer, obtains the clock signal for described radio circuit.
Optionally, in one embodiment of this invention, described another road with described clock signal sends to described digital circuit to use, comprise: another clock signal that will tell changes clock signal for the unit of described digital circuit into by frequency synthesis successively after oversampling clock shaping circuit, transmission channel clock, clock receiving circuit.
Optionally, in one embodiment of this invention, describedly change clock signal for the unit of described digital circuit into by frequency synthesis, comprise: the phase-locked loop pll that utilizes the on-site programmable gate array FPGA in the data processing unit of described digital circuit to carry, change clock signal for the unit of described digital circuit into by frequency synthesis.
Optionally, in one embodiment of this invention, described clock shaping circuit is realized by low pass filter or band pass filter.
Optionally, in one embodiment of this invention, when described radio circuit and described digital circuit existed on same circuit board simultaneously, described transmission channel clock was by the printing board PCB microstrip line, or the optocoupler transmission, or the transmission of magnetic coupling realizes; When described radio circuit and described digital circuit did not exist on same circuit board simultaneously, described transmission channel clock was realized by coaxial cable.
Optionally, in one embodiment of this invention, described clock receiving circuit carries out process of frequency multiplication to the clock signal of process.
On the other hand, the embodiment of the present invention provides a kind of device that clock signal is provided, described device is for existing simultaneously the device of radio circuit and digital circuit, described device includes only a system clock, be used for sending clock signal, riches all the way gives described radio circuit and use with described clock signal for this system clock, and send to described digital circuit to use on another road of described clock signal.
Optionally, in one embodiment of this invention, described device also comprises: a plurality of clock driver circuits are used for described clock signal is told a plurality of with clock signal frequently.
Optionally, in one embodiment of this invention, described radio circuit comprises: phase-locked loop and frequency mixer, a plurality of clock signals with frequency that are used for telling are carried out frequency synthesis through phase-locked loop and frequency mixer, obtain the clock signal for described radio circuit.
Optionally, in one embodiment of this invention, described digital circuit comprises clock shaping circuit, transmission channel clock, clock receiving circuit, frequency synthesis unit, be used for another clock signal that to tell successively after oversampling clock shaping circuit, transmission channel clock, clock receiving circuit, change clock signal for the unit of described digital circuit into by the frequency synthesis unit.
Optionally, in one embodiment of this invention, described frequency synthesis unit, the phase-locked loop pll that the concrete on-site programmable gate array FPGA that is used for utilizing the data processing unit of described digital circuit carries changes clock signal for the unit of described digital circuit into by frequency synthesis.
Optionally, in one embodiment of this invention, described clock shaping circuit is realized by low pass filter or band pass filter.
Optionally, in one embodiment of this invention, when described radio circuit and described digital circuit existed on same circuit board simultaneously, described transmission channel clock was by the printing board PCB microstrip line, or the optocoupler transmission, or the transmission of magnetic coupling realizes; When described radio circuit and described digital circuit did not exist on same circuit board simultaneously, described transmission channel clock was realized by coaxial cable.
Optionally, in one embodiment of this invention, described clock receiving circuit carries out process of frequency multiplication to the clock signal of process.
On the one hand, the embodiment of the present invention provides a kind of spectrum analyzer again, and described spectrum analyzer comprises the above-mentioned device that clock signal is provided.
Technique scheme has following beneficial effect: because adopted a kind of device that clock signal is provided, described device is used for sending clock signal for to exist the device of radio circuit and digital circuit, described device to include only a system clock simultaneously; Riches all the way gives described radio circuit and use with described clock signal, and the technological means that sends to described digital circuit to use on another road of described clock signal, so can solve interference problem and stationary problem between digital circuit and radio circuit.The digital circuit and the radio circuit that have particularly solved in the broad-band receiver field are integrated in interference problem and the stationary problem that same circuit board brings, and clock also makes circuit design greatly simplify, and save cost.Same clock signal makes each clock of whole system relevant, can process by software like this and remove the spurious signal irrelevant with input signal.The fair digital dock that is better than of radio frequency clock signal is so can improve the whole system frequency resolution after adopting same clock synchronous.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is existing DSA1030 spectrum analyzer system clock block diagram;
Fig. 2 provides the method flow diagram of clock signal for the embodiment of the present invention is a kind of;
Fig. 3 provides the apparatus structure schematic diagram of clock signal for the embodiment of the present invention is a kind of;
Fig. 4 is a kind of spectrum analyzer structural representation of the embodiment of the present invention;
Fig. 5 is the first design diagram of embodiment of the present invention clock driver circuit;
Fig. 6 is the second design diagram of embodiment of the present invention clock driver circuit;
Fig. 7 is the 3rd design diagram of embodiment of the present invention clock driver circuit;
Fig. 8 is the first design diagram of embodiment of the present invention clock shaping circuit;
Fig. 9 is the second design diagram of embodiment of the present invention clock shaping circuit;
Figure 10 is that the embodiment of the present invention is carried out the circuit design schematic diagram of process of frequency multiplication to clock signal.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
As shown in Figure 2, provide the method flow diagram of clock signal for the embodiment of the present invention is a kind of, described method is applied to exist simultaneously the device of radio circuit and digital circuit, and described method comprises:
201, provide a system clock;
202, obtain the clock signal that described system clock sends;
203, riches all the way gives described radio circuit and use with described clock signal, and send to described digital circuit to use on another road of described clock signal.
Optionally, describedly obtain the clock signal that described system clock sends, can comprise: by a plurality of clock driver circuits, described clock signal is told a plurality of with clock signals frequently.
Optionally, described riches all the way gives described radio circuit and use with described clock signal, can comprise: that will tell a plurality ofly carries out frequency synthesis with clock signals frequently through phase-locked loop and frequency mixer, obtains the clock signal for described radio circuit.
Optionally, described another road with described clock signal sends to described digital circuit to use, can comprise: another clock signal that will tell changes clock signal for the unit of described digital circuit into by frequency synthesis successively after oversampling clock shaping circuit, transmission channel clock, clock receiving circuit.
Optionally, describedly change clock signal for the unit of described digital circuit into by frequency synthesis, can comprise: the phase-locked loop pll that utilizes the on-site programmable gate array FPGA in the data processing unit of described digital circuit to carry, change clock signal for the unit of described digital circuit into by frequency synthesis.
Optionally, described clock shaping circuit can be realized by low pass filter or band pass filter.
Optionally, when described radio circuit and described digital circuit existed on same circuit board simultaneously, described transmission channel clock was by the printing board PCB microstrip line, or the optocoupler transmission, or the transmission of magnetic coupling realizes; When described radio circuit and described digital circuit did not exist on same circuit board simultaneously, described transmission channel clock was realized by coaxial cable.
Optionally, described clock receiving circuit can carry out process of frequency multiplication to the clock signal of process.
Said method technical scheme of the present invention can solve interference problem and the stationary problem between digital circuit and radio circuit.The digital circuit and the radio circuit that have particularly solved in the broad-band receiver field are integrated in interference problem and the stationary problem that same circuit board brings, and clock also makes circuit design greatly simplify, and save cost.Same clock signal makes each clock of whole system relevant, can process by software like this and remove the spurious signal irrelevant with input signal.The fair digital dock that is better than of radio frequency clock signal is so can improve the whole system frequency resolution after adopting same clock synchronous.
Corresponding to said method embodiment, as shown in Figure 3, the apparatus structure schematic diagram of clock signal is provided for the embodiment of the present invention is a kind of, described device is for existing simultaneously the device of radio circuit 32 and digital circuit 33, described device includes only a system clock 31, be used for sending clock signal, riches all the way gives described radio circuit 32 and use with described clock signal for this system clock 31, and send to described digital circuit 33 to use on another road of described clock signal.
Optionally, described device also comprises: a plurality of clock driver circuits are used for described clock signal is told a plurality of with clock signal frequently.
Optionally, described radio circuit comprises: phase-locked loop and frequency mixer, a plurality of clock signals with frequency that are used for telling are carried out frequency synthesis through phase-locked loop and frequency mixer, obtain the clock signal for described radio circuit.
Optionally, described digital circuit comprises clock shaping circuit, transmission channel clock, clock receiving circuit, frequency synthesis unit, be used for another clock signal that to tell successively after oversampling clock shaping circuit, transmission channel clock, clock receiving circuit, change clock signal for the unit of described digital circuit into by the frequency synthesis unit.
Optionally, described frequency synthesis unit, the phase-locked loop pll that the concrete on-site programmable gate array FPGA that is used for utilizing the data processing unit of described digital circuit carries changes clock signal for the unit of described digital circuit into by frequency synthesis.
Optionally, described clock shaping circuit is realized by low pass filter or band pass filter.
Optionally, when described radio circuit and described digital circuit existed on same circuit board simultaneously, described transmission channel clock was by the printing board PCB microstrip line, or the optocoupler transmission, or the transmission of magnetic coupling realizes; When described radio circuit and described digital circuit did not exist on same circuit board simultaneously, described transmission channel clock was realized by coaxial cable.
Optionally, described clock receiving circuit carries out process of frequency multiplication to the clock signal of process.
Said apparatus technical scheme of the present invention can solve interference problem and the stationary problem between digital circuit and radio circuit.The digital circuit and the radio circuit that have particularly solved in the broad-band receiver field are integrated in interference problem and the stationary problem that same circuit board brings, and clock also makes circuit design greatly simplify, and save cost.Same clock signal makes each clock of whole system relevant, can process by software like this and remove the spurious signal irrelevant with input signal.The fair digital dock that is better than of radio frequency clock signal is so can improve the whole system frequency resolution after adopting same clock synchronous.
The embodiment of the present invention provides a kind of spectrum analyzer, and described spectrum analyzer comprises the above-mentioned device that clock signal is provided.
As shown in Figure 4, be a kind of spectrum analyzer structural representation of the embodiment of the present invention, system clock 41 produces the low phase noise clock signal, use VCXO (the Voltage Controled X ' tal Oscillator of 10MHz in the present embodiment, voltage controlled oscillator) as the clock signal of native system, this signal driver ability a little less than, so added respectively clock driving 421, clock driving 431, clock to drive 441, respectively clock given local oscillator phase-locked loop 422, local oscillator phase-locked loop 432, digital circuit clock shaping circuit 442.Phase-locked loop 422 produces system's swept-frequency signal, produce the first intermediate-freuqncy signal under the effect of frequency mixer 423 with radio-frequency input signals, this first intermediate-freuqncy signal produces intermediate frequency output with the signal that phase-locked loop 432 produces again under the effect of frequency mixer 433, this intermediate-freuqncy signal frequency is lower, the present embodiment is 10.7MHz, in above-mentioned radio circuit, the highest to clock request, the phase noise of system clock 41 has determined the phase noise of whole system to a great extent.Digital dock shaping circuit 442 is low pass filter in the present embodiment, and this shaping circuit 442 drives clock the clock high order harmonic component filtering of 441 outputs, and making the signal that enters clock passage 443 is pure sinusoidal wave clock signal.This sinusoidal wave clock signal is transmitted in passage 443 and can't be brought interference to other digital circuits, and other numerical portion interference signals also can be by 442 filterings of clock shaping circuit equally.The 10MHz sine wave signal arrives clock receiving circuit 444 through passage 443, clock receiving circuit 444 has two effects, first serves as the matched termination, second is treated to digital circuit acceptable clock signal with this 10MHz sine wave, be one or two frequency multiplier circuits in the present embodiment, change the 10MHz sine wave into 20MHz square wave clock signal 2, then this clock signal 2 is delivered to data processing unit 446.
This data processing unit 446 is the FPGA that carry phase-locked loop 445, it is configurable different clocks output that software parameter so only need be set, and as peripheral hardware 447, is USB peripheral hardware chip in the present embodiment, this USB chip needs the 24MHz clock, so configuration FPGA phase-locked loop is output as 24MHz with clock signal 2; Same peripheral hardware 448 is network card chip in the present embodiment, and this network card chip needs the 25MHz clock, so configuration FPGA phase-locked loop is output as 25MHz with clock signal 3, has so just completed the distribution of whole system clock.
Clock driving 421,431,441 and clock receive design circuit such as Fig. 5, Fig. 6, shown in Figure 7 of 444.
Circuit in Fig. 5 both can be used as clock driver circuit, can be used as again the clock receiving circuit, in the present embodiment, U31B adopts device NL27WZ04, the ratio of R32 and R31 is about 4: 3, direct current biasing is on the trigging signal of not gate U31B like this, Vin31 only needs less amplitude can make not gate U31B work, makes it Vout31 output square wave.The replacement scheme of this driving also has Fig. 6 and Fig. 7, and in Fig. 6, not gate U41B is equivalent to a high-gain amplifier, is operated in the deep negative feedback states, and its gain is determined by R41; If circuit is responsive to the switch high order harmonic component of inverter, can also use replacement scheme Fig. 7, this amplifier harmonic distortion is little, can satisfy general circuit and drive requirement.
clock shaping 442 makes the clock signal that drives 441 outputs be convenient to transmit and designs, especially in spectrum analyzer, the radio circuit all parts is responsive to clock, especially the each harmonic of clock, be easy to enter the output that frequency mixer 423 and frequency mixer 433 cause spurious signal, so need to carry out filtering to clock signal processes, in the present embodiment, the clock shaping circuit as shown in Figure 8, it is a 10MHz band pass filter, L61, C63, C64 consists of the LC shunt-resonant circuit, resonance point is adjusted at the 10MHz place, Vout61 will export the 10MHz sine wave like this, C63 and C64 parallel connection are in order to increase the Q value of whole resonant tank.Replacement scheme also has the 10MHz low pass filter, as shown in Figure 9.
The embodiment of the present invention can not realize same clock in digital circuit and radio circuit yet on same circuit board, only need the clock passage 443 in Fig. 4 is revised as coaxial cable, when higher or cable is longer when frequency, notes the coupling of circuit.
digital circuit in the present embodiment and radio circuit are to concentrate on same circuit board, although used same clock, it is still very large that but digital circuit is disturbed, as the RGB on the liquid crystal circuit (RGB) data-signal, DDR SDRAM (Double Data Rate SDRAM, the Double Data Rate synchronous DRAM) data address signal, ADC (Analog-to-Digital Converter, A/D converter) data-signal etc. is all huge interference source concerning radio circuit, so digital circuit and radio circuit power supply need to be separated from each other, ground wire is separated from each other, namely cede territory.But can not be fully although need to cede territory again digitally cutting open with simulation ground, the signal path ground of digital circuit and radio circuit also needs assurance, will complete remaining as the ground wire of clock signal channel 443.
When system clock 41 frequencies can not satisfy in the situation of digital circuit work, also need this system clock 41 is carried out suitable processing.In the present embodiment, the 10MHz clock can not satisfy the minimum clock request of processor, this is to carry out process of frequency multiplication to it, this process of frequency multiplication is placed on clock and receives 23 places, and circuit carries out the circuit design schematic diagram of process of frequency multiplication as shown in figure 10 to clock signal for the embodiment of the present invention.Q81 in Figure 10, R81, R82, L81, C81, C82 forms oscillator amplifier circuit, L81, C81 and C82 form the 20MHz oscillator amplifier circuit, 20MHz harmonic wave after the sinusoidal wave amplification of 10MHz on Vin8 is taken out give by C83, L82, C84, C85, C86, L83, C87, the 20MHz band pass filter that C88 forms, signal after resonance is amplified filtering again takes out pure 20MHz signal, at last it is given by C89, R83, U81B, the shaping circuit that R84 forms, Vout8 output 20MHz square wave offers digital processing unit and uses, the frequency multiplication of so just having completed clock signal receives.
Digital circuit and radio circuit that the embodiment of the present invention has solved in the broad-band receiver field are integrated in interference problem and the stationary problem that same circuit board brings, and clock also makes circuit design greatly simplify, and save cost.Use same clock to drive in whole spectrum analyzer, make system's unit clock relevant, between unit, communication is synchronous; And the PLL (Phase Locked Loop, phase-locked loop) that frequency synthesis partly uses the FPGA (Field-Programmable Gate Array, field programmable gate array) in data processing unit to carry takes full advantage of resource, saves cost; Digiboard and rf board close in same plate, have reduced assembling and making sheet cost.Same clock signal makes each clock of whole system relevant, can process by software like this and remove the spurious signal irrelevant with input signal.In the present invention, system is based under same clock and works, no matter be the interference of radio circuit itself or from the interference of digital circuit, its effect is during frequency spectrum shows, fixing spuious existence to be arranged, and this is spuious irrelevant with input, so can be by the software calibration technology with this fixing spuious rejecting, even be under outer synchronous regime at spectrum analyzer, this fixing spuiously still can effectively remove.The fair digital dock that is better than of radio frequency clock signal is so can improve the whole system frequency resolution after adopting same clock synchronous.
Those skilled in the art can also recognize the various illustrative components, blocks (illustrative logical block) that the embodiment of the present invention is listed, the unit, and step can pass through electronic hardware, computer software, or both combinations realize.Be the clear replaceability (interchangeability) of showing hardware and software, above-mentioned various illustrative components (illustrative components), unit and step have been described their function generally.Such function is to realize depending on the designing requirement of specific application and whole system by hardware or software.Those skilled in the art can be for every kind of specific application, and can make ins all sorts of ways realizes described function, but this realization should not be understood to exceed the scope of embodiment of the present invention protection.
Various illustrative logical block described in the embodiment of the present invention, or the unit can pass through general processor, digital signal processor, application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the design of above-mentioned any combination realizes or operates described function.General processor can be microprocessor, and alternatively, this general processor also can be any traditional processor, controller, microcontroller or state machine.Processor also can realize by the combination of calculation element, for example digital signal processor and microprocessor, multi-microprocessor, Digital Signal Processor Core of one or more microprocessors associating, or any other similarly configuration realize.
Method described in the embodiment of the present invention or the step of algorithm can directly embed hardware, the software module of processor execution or the two combination.Software module can be stored in the storage medium of other arbitrary form in RAM memory, flash memory, ROM memory, eprom memory, eeprom memory, register, hard disk, moveable magnetic disc, CD-ROM or this area.Exemplarily, storage medium can be connected with processor so that processor can be from storage medium reading information, and can deposit write information to storage medium.Alternatively, storage medium can also be integrated in processor.Processor and storage medium can be arranged in ASIC, and ASIC can be arranged in user terminal.Alternatively, processor and storage medium also can be arranged in different parts in user terminal.
In one or more exemplary designs, the described above-mentioned functions of the embodiment of the present invention can realize in hardware, software, firmware or this three's combination in any.If realize in software, these functions can be stored on medium with computer-readable, or are transmitted on the medium of computer-readable with one or more instructions or code form.The computer-readable medium comprises the computer storage medium and is convenient to make allows computer program transfer to other local communication medium from a place.Storage medium can be the useable medium that any general or special computer can access.For example, such computer readable media can include but not limited to RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage device, or other anyly can be used for carrying or storage and can be read by general or special computer or general or special processor the medium of the program code of form with instruction or data structure and other.In addition, any connection can suitably be defined as the computer-readable medium, for example, if software is by a coaxial cable, optical fiber computer, twisted-pair feeder, Digital Subscriber Line (DSL) or also being comprised in defined computer-readable medium with wireless way for transmittings such as infrared, wireless and microwave from a web-site, server or other remote resource.Described video disc (disk) and disk (disc) comprise Zip disk, radium-shine dish, CD, DVD, floppy disk and Blu-ray Disc, and disk is usually with the magnetic duplication data, and video disc carries out the optical reproduction data with laser usually.Above-mentioned combination also can be included in the computer-readable medium.
Above-described embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above is only the specific embodiment of the present invention; the protection range that is not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (17)
1. method that clock signal is provided, described method is applied to exist simultaneously the device of radio circuit and digital circuit, it is characterized in that, and described method comprises:
A system clock is provided;
Obtain the clock signal that described system clock sends;
Riches all the way gives described radio circuit and use with described clock signal, and send to described digital circuit to use on another road of described clock signal.
2. method as claimed in claim 1, is characterized in that, describedly obtains the clock signal that described system clock sends, and comprising:
By a plurality of clock driver circuits, described clock signal is told a plurality of with clock signal frequently.
3. method as claimed in claim 2, is characterized in that, described riches all the way gives described radio circuit and use with described clock signal, comprising:
A plurality of clock signals with frequency of telling are carried out frequency synthesis through phase-locked loop and frequency mixer, obtain the clock signal for described radio circuit.
4. method as claimed in claim 2, is characterized in that, described another road with described clock signal sends to described digital circuit to use, and comprising:
Successively after oversampling clock shaping circuit, transmission channel clock, clock receiving circuit, change by frequency synthesis another clock signal of telling into for the unit of described digital circuit clock signal.
5. method as claimed in claim 4, is characterized in that, describedly changes clock signal for the unit of described digital circuit into by frequency synthesis, comprising:
The phase-locked loop pll that utilizes the on-site programmable gate array FPGA in the data processing unit of described digital circuit to carry changes clock signal for the unit of described digital circuit into by frequency synthesis.
6. method as claimed in claim 4, is characterized in that, described clock shaping circuit is realized by low pass filter or band pass filter.
7. method as claimed in claim 4, is characterized in that, when described radio circuit and described digital circuit existed on same circuit board simultaneously, described transmission channel clock was by the printing board PCB microstrip line, or the optocoupler transmission, or the transmission of magnetic coupling realizes; When described radio circuit and described digital circuit did not exist on same circuit board simultaneously, described transmission channel clock was realized by coaxial cable.
8. method as claimed in claim 4, is characterized in that, described clock receiving circuit carries out process of frequency multiplication to the clock signal of process.
9. device that clock signal is provided, described device is for existing simultaneously the device of radio circuit and digital circuit, it is characterized in that, described device includes only a system clock, be used for sending clock signal, riches all the way gives described radio circuit and use with described clock signal, and send to described digital circuit to use on another road of described clock signal.
10. install as claimed in claim 9, it is characterized in that, described device also comprises:
A plurality of clock driver circuits are used for described clock signal is told a plurality of with clock signal frequently.
11. device, is characterized in that as claimed in claim 10, described radio circuit comprises:
Phase-locked loop and frequency mixer, a plurality of clock signals with frequency that are used for telling are carried out frequency synthesis through phase-locked loop and frequency mixer, obtain the clock signal for described radio circuit.
12. install as claimed in claim 10, it is characterized in that, described digital circuit comprises clock shaping circuit, transmission channel clock, clock receiving circuit, frequency synthesis unit, be used for another clock signal that to tell successively after oversampling clock shaping circuit, transmission channel clock, clock receiving circuit, change clock signal for the unit of described digital circuit into by the frequency synthesis unit.
13. install as claimed in claim 12, it is characterized in that, described frequency synthesis unit, the phase-locked loop pll that the concrete on-site programmable gate array FPGA that is used for utilizing the data processing unit of described digital circuit carries changes clock signal for the unit of described digital circuit into by frequency synthesis.
14. device, is characterized in that as claimed in claim 12, described clock shaping circuit is realized by low pass filter or band pass filter.
15. device, is characterized in that as claimed in claim 12, when described radio circuit and described digital circuit existed on same circuit board simultaneously, described transmission channel clock was by the printing board PCB microstrip line, or the optocoupler transmission, or the transmission of magnetic coupling realizes; When described radio circuit and described digital circuit did not exist on same circuit board simultaneously, described transmission channel clock was realized by coaxial cable.
16. device, is characterized in that as claimed in claim 12, described clock receiving circuit carries out process of frequency multiplication to the clock signal of process.
17. a spectrum analyzer is characterized in that, described spectrum analyzer comprises the described device that clock signal is provided of any one in claim 9-16.
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| CN201110431634.9A CN103178836B (en) | 2011-12-21 | 2011-12-21 | A kind of method, device and spectrum analyzer that clock signal is provided |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105871393A (en) * | 2015-02-06 | 2016-08-17 | 硅实验室股份有限公司 | Managing spurs in a radio frequency circuit |
| CN110224603A (en) * | 2019-05-24 | 2019-09-10 | 毫厘机电(苏州)有限公司 | A kind of PCB layout structure of Multiple isolated outputs driving power circuit and circuit |
| CN113612556A (en) * | 2021-07-28 | 2021-11-05 | 清华大学 | Integrated multi-node spectrum sensing method and device |
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| CN105871393B (en) * | 2015-02-06 | 2021-01-22 | 硅实验室股份有限公司 | Managing spurs in radio frequency circuits |
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| CN114115438B (en) * | 2020-08-31 | 2023-07-04 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN113612556A (en) * | 2021-07-28 | 2021-11-05 | 清华大学 | Integrated multi-node spectrum sensing method and device |
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