CN103178836B - A kind of method, device and spectrum analyzer that clock signal is provided - Google Patents
A kind of method, device and spectrum analyzer that clock signal is provided Download PDFInfo
- Publication number
- CN103178836B CN103178836B CN201110431634.9A CN201110431634A CN103178836B CN 103178836 B CN103178836 B CN 103178836B CN 201110431634 A CN201110431634 A CN 201110431634A CN 103178836 B CN103178836 B CN 103178836B
- Authority
- CN
- China
- Prior art keywords
- clock
- circuit
- clock signal
- digital circuit
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The embodiment of the present invention provides a kind of method, device and spectrum analyzer for providing clock signal, and methods described is applied to there is radio circuit and the device of digital circuit simultaneously, including：One system clock is provided；Obtain the clock signal that the system clock is sent；The radio circuit that is sent to all the way of the clock signal is used, and another road of the clock signal is sent to the digital circuit and is used.Is while there is radio circuit and the device of digital circuit in described device, described device only includes a system clock, for sending clock signal, the radio circuit that is sent to all the way of the clock signal is used, and another road of the clock signal is sent to the digital circuit use.The present invention can solve the interference problem and stationary problem between digital circuit and radio circuit.The digital circuit particularly solved in broad-band receiver field is integrated in interference problem and the stationary problem that same circuit board is brought with radio circuit.
Description
Technical field
The present invention relates to radio frequency arts, more particularly to a kind of method, device and spectrum analysis for providing clock signal
Instrument.
Background technology
In radio-frequency communication field, digital circuit and radio frequency analog circuit, which coexist epoch of a system, to be continued and will
Continue, in this case, digital circuit interference simulation circuit will also continue.Especially in RF receiving circuit, before radio frequency
Hold sensitivity high, and the useful signal received is very faint, it is easy to disturbed by the switch higher hamonic wave of digital circuit, and it is digital
The interference of partial circuit is unpredictable, i.e., interference is irrelevant, so generally in circuit design process, by digital electricity
Road and radio frequency analog circuit are physically spaced from each other, and whole radio system such as is divided into digital circuit board and radio frequency circuit board,
Because the reason for physical isolation, two boards also each respective clock of having used by oneself, the serial frequency spectrographs of the existing DSA1030 of in the market are just
This structure is used.
As shown in figure 1, being existing DSA1030 spectrum analyzers system clock block diagram, it is divided into radio frequency circuit board 1 and numeral
Circuit board 2, the radio circuit of radio frequency circuit board 1 is synchronized with a clock 11, and the device of digital circuit board 2 due to data processing or
The different of transmission rate use different clocks respectively, when such as data processing unit 122 is used using clock 12, and peripheral hardware 132
Clock 13, peripheral hardware 142 uses clock 14, as data processing unit 122 has just used DSP (Digital Signal in DSA1030
Processing, Digital Signal Processing), it is necessary to which 25MHz clock, peripheral hardware 132 is that (Universal Serial BUS lead to USB
With universal serial bus) interface chip needs 12MHz clock signal, and peripheral hardware 142 is that Ethernet chip needs 25MHz clock
Signal, they have used the poor passive crystal oscillator of frequency stability.The isolation of physics makes radio frequency circuit board 1 and digital circuit board
2 are isolated from each other, and clock is also independent of one another, and such benefit is the physics spacing reduction that each clock functions device, clock
PCB (Printed Circuit Board, printed circuit board (PCB)) line shortens.
Certainly isolation physically can be good at preventing digital circuit interference simulation circuit, but for small volume
For radio-frequency apparatus, the increase of cost and volume that this isolation physically is brought is difficult to tolerate, also add dress
With difficulty.It there is also and communicated because circuit both sides clock is asynchronous when radio circuit is mutually communicated with digital circuit
The asynchronous problem of signal.
The clock interference signal of data signal is mixed into after analog circuit, when being inferior to simulation due to digital clock phases noise
Clock, causes final signal phase noise to be deteriorated so both are overlapped mutually.
To sum up, for the interference problem and stationary problem between digital circuit and radio circuit, current urgent need to resolve scheme.
The content of the invention
The embodiment of the present invention provides a kind of method, device and spectrum analyzer for providing clock signal, to solve digital electricity
Interference problem and stationary problem between road and radio circuit.
On the one hand, the embodiments of the invention provide a kind of method for providing clock signal, methods described is applied to deposit simultaneously
In radio circuit and the device of digital circuit, methods described includes：One system clock is provided；The system clock is obtained to send
Clock signal；The radio circuit that is sent to all the way of the clock signal is used, and by the another of the clock signal
Road is sent to the digital circuit and used.
Optionally, in one embodiment of this invention, the clock signal that the acquisition system clock is sent, including：
By multiple clock driver circuits, the clock signal is separated to the clock signal of multiple same frequencies.
Optionally, in one embodiment of this invention, it is described that the clock signal is sent to the radio frequency electrical all the way
Road is used, including：The clock signal of the multiple same frequencies separated is subjected to frequency synthesis through phaselocked loop and frequency mixer, obtained for described
The clock signal that radio circuit is used.
Optionally, in one embodiment of this invention, it is described that another road of the clock signal is sent to the numeral
Circuit is used, including：Another clock signal separated is sequentially passed through into clock shaping circuit, transmission channel clock, clock to connect
Receive after circuit, the clock signal used for the unit of the digital circuit is changed into by frequency synthesis.
Optionally, in one embodiment of this invention, it is described to be changed into by frequency synthesis for each of the digital circuit
The clock signal that individual unit is used, including：Utilize the field programmable gate array in the data processing unit of the digital circuit
The phase-locked loop pll that FPGA is carried, the clock signal used for the unit of the digital circuit is changed into by frequency synthesis.
Optionally, in one embodiment of this invention, the clock shaping circuit passes through low pass filter or bandpass filtering
Device is realized.
Optionally, in one embodiment of this invention, when the radio circuit and the digital circuit are in same circuit
On plate simultaneously in the presence of, the transmission channel clock pass through printing board PCB microstrip line, or optocoupler transmission, or magnetic coupling transmission
Realize；In the presence of the radio circuit and the digital circuit be not on same circuit board simultaneously, the clock transfer is led to
Realized by coaxial cable in road.
Optionally, in one embodiment of this invention, the clock receiving circuit carries out frequency multiplication to the clock signal of process
Processing.
On the other hand, the embodiments of the invention provide a kind of device for providing clock signal, described device is presence simultaneously
The device of radio circuit and digital circuit, described device only includes a system clock, for sending clock signal, during the system
Clock uses the radio circuit that is sent to all the way of the clock signal, and another road of the clock signal is sent into institute
Digital circuit is stated to use.
Optionally, in one embodiment of this invention, described device also includes：Multiple clock driver circuits, for by institute
State the clock signal that clock signal separates multiple same frequencies.
Optionally, in one embodiment of this invention, the radio circuit includes：Phaselocked loop and frequency mixer, for that will divide
The clock signal of the multiple same frequencies gone out carries out frequency synthesis through phaselocked loop and frequency mixer, obtain for the radio circuit use when
Clock signal.
Optionally, in one embodiment of this invention, the digital circuit is led to including clock shaping circuit, clock transfer
Road, clock receiving circuit, frequency synthesis unit, for by another clock signal separated sequentially pass through clock shaping circuit,
After transmission channel clock, clock receiving circuit, it is changed into by frequency synthesis unit and supplies the unit of the digital circuit to make
Clock signal.
Optionally, in one embodiment of this invention, the frequency synthesis unit, specifically for utilizing the digital circuit
Data processing unit in the phase-locked loop pll that carries of on-site programmable gate array FPGA, be changed into by frequency synthesis and supply institute
State the clock signal that the unit of digital circuit is used.
Optionally, in one embodiment of this invention, the clock shaping circuit passes through low pass filter or bandpass filtering
Device is realized.
Optionally, in one embodiment of this invention, when the radio circuit and the digital circuit are in same circuit
On plate simultaneously in the presence of, the transmission channel clock pass through printing board PCB microstrip line, or optocoupler transmission, or magnetic coupling transmission
Realize；In the presence of the radio circuit and the digital circuit be not on same circuit board simultaneously, the clock transfer is led to
Realized by coaxial cable in road.
Optionally, in one embodiment of this invention, the clock receiving circuit carries out frequency multiplication to the clock signal of process
Processing.
Another further aspect, the embodiments of the invention provide a kind of spectrum analyzer, the spectrum analyzer includes above-mentioned offer
The device of clock signal.
Above-mentioned technical proposal has the advantages that：Because employing a kind of device for providing clock signal, the dress
It is set to while there is radio circuit and the device of digital circuit, described device only includes a system clock, for sending clock
Signal；The radio circuit that is sent to all the way of the clock signal is used, and another road of the clock signal is sent
The technological means used to the digital circuit, it is possible to solve interference problem between digital circuit and radio circuit and same
Step problem.The digital circuit particularly solved in broad-band receiver field is integrated in same circuit board institute band with radio circuit
The interference problem and stationary problem come, and a clock also causes circuit design to greatly simplify, and saves cost.Same clock letter
Number cause whole system each clock related, can so pass through software processing and remove the spurious signal unrelated with input signal.
Radio frequency clock signals quality is typically better than digital dock, so using can improve whole system frequency after same clock synchronization
Resolution ratio.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is existing DSA1030 spectrum analyzers system clock block diagram；
Fig. 2 is a kind of method flow diagram for providing clock signal of the embodiment of the present invention；
Fig. 3 is a kind of apparatus structure schematic diagram for providing clock signal of the embodiment of the present invention；
Fig. 4 is a kind of spectrum analyzer structural representation of the embodiment of the present invention；
Fig. 5 is the first design diagram of clock driver circuit of the embodiment of the present invention；
Fig. 6 is the second design diagram of clock driver circuit of the embodiment of the present invention；
Fig. 7 is the 3rd design diagram of clock driver circuit of the embodiment of the present invention；
Fig. 8 is the first design diagram of clock shaping circuit of the embodiment of the present invention；
Fig. 9 is the second design diagram of clock shaping circuit of the embodiment of the present invention；
Figure 10 is the circuit design schematic diagram that the embodiment of the present invention carries out process of frequency multiplication to clock signal.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As shown in Fig. 2 being a kind of method flow diagram for providing clock signal of the embodiment of the present invention, methods described is applied to same
When there is radio circuit and the device of digital circuit, methods described includes：
The 201st, one system clock is provided；
202nd, the clock signal that the system clock is sent is obtained；
203rd, the radio circuit that is sent to all the way of the clock signal is used, and by the another of the clock signal
Road is sent to the digital circuit and used.
Optionally, it is described to obtain the clock signal that the system clock is sent, it can include：Electricity is driven by multiple clocks
Road, the clock signal is separated the clock signal of multiple same frequencies.
Optionally, it is described to use the radio circuit that is sent to all the way of the clock signal, it can include：It will separate
The clock signals of multiple same frequencies carry out frequency synthesis through phaselocked loop and frequency mixer, obtain the clock used for the radio circuit
Signal.
Optionally, it is described another road of the clock signal is sent to the digital circuit to use, it can include：It will divide
Another clock signal gone out is sequentially passed through after clock shaping circuit, transmission channel clock, clock receiving circuit, is closed by frequency
Into being changed into the clock signal that is used for the unit of the digital circuit.
It is optionally, described that the clock signal used for the unit of the digital circuit is changed into by frequency synthesis,
It can include：The phaselocked loop carried using the on-site programmable gate array FPGA in the data processing unit of the digital circuit
PLL, the clock signal used for the unit of the digital circuit is changed into by frequency synthesis.
Optionally, the clock shaping circuit can be realized by low pass filter or bandpass filter.
Optionally, in the presence of the radio circuit and the digital circuit are on same circuit board simultaneously, when described
Clock transmission channel is transmitted by printing board PCB microstrip line, or optocoupler, or the transmission of magnetic coupling is realized；When the radio circuit and
The digital circuit not on same circuit board simultaneously in the presence of, the transmission channel clock is realized by coaxial cable.
Optionally, the clock receiving circuit can carry out process of frequency multiplication to the clock signal of process.
Above method technical scheme of the present invention can solve interference problem between digital circuit and radio circuit and synchronous
Problem.Particularly solve the digital circuit in broad-band receiver field and be integrated in same circuit board with radio circuit and brought
Interference problem and stationary problem, and a clock also causes circuit design to greatly simplify, and saves cost.Same clock signal
So that each clock of whole system is related, the spurious signal unrelated with input signal can be so removed by software processing.Penetrate
Frequency clock signal quality is typically better than digital dock, so being divided using that can improve whole system frequency after same clock synchronization
Resolution.
Corresponding to above method embodiment, as shown in figure 3, being a kind of device knot for providing clock signal of the embodiment of the present invention
Structure schematic diagram, is there is the device of radio circuit 32 and digital circuit 33 in described device, described device only includes one and is simultaneously
System clock 31, for sending clock signal, the system clock 31 is sent to the radio circuit all the way by the clock signal
32 use, and another road of the clock signal is sent into the digital circuit 33 used.
Optionally, described device also includes：Multiple clock driver circuits, it is multiple with frequency for the clock signal to be separated
Clock signal.
Optionally, the radio circuit includes：Phaselocked loop and frequency mixer, for by the clock signal of the multiple same frequencies separated
Frequency synthesis is carried out through phaselocked loop and frequency mixer, the clock signal used for the radio circuit is obtained.
Optionally, the digital circuit includes clock shaping circuit, transmission channel clock, clock receiving circuit, frequency conjunction
Into unit, electricity is received for another clock signal separated to be sequentially passed through into clock shaping circuit, transmission channel clock, clock
Lu Hou, the clock signal used for the unit of the digital circuit is changed into by frequency synthesis unit.
Optionally, the frequency synthesis unit, specifically for showing in the data processing unit using the digital circuit
The phase-locked loop pll that field programmable gate array FPGA is carried, the unit for the digital circuit is changed into by frequency synthesis
The clock signal used.
Optionally, the clock shaping circuit is realized by low pass filter or bandpass filter.
Optionally, in the presence of the radio circuit and the digital circuit are on same circuit board simultaneously, when described
Clock transmission channel is transmitted by printing board PCB microstrip line, or optocoupler, or the transmission of magnetic coupling is realized；When the radio circuit and
The digital circuit not on same circuit board simultaneously in the presence of, the transmission channel clock is realized by coaxial cable.
Optionally, the clock receiving circuit carries out process of frequency multiplication to the clock signal of process.
Said apparatus technical scheme of the present invention can solve interference problem between digital circuit and radio circuit and synchronous
Problem.Particularly solve the digital circuit in broad-band receiver field and be integrated in same circuit board with radio circuit and brought
Interference problem and stationary problem, and a clock also causes circuit design to greatly simplify, and saves cost.Same clock signal
So that each clock of whole system is related, the spurious signal unrelated with input signal can be so removed by software processing.Penetrate
Frequency clock signal quality is typically better than digital dock, so being divided using that can improve whole system frequency after same clock synchronization
Resolution.
The embodiment of the present invention provides a kind of spectrum analyzer, and the spectrum analyzer includes the dress of above-mentioned offer clock signal
Put.
As shown in figure 4, being a kind of spectrum analyzer structural representation of the embodiment of the present invention, system clock 41 produces low phase position
10MHz VCXO (Voltage Controled X ' tal Oscillator, pressure are used in noisy clock signal, the present embodiment
Controlled oscillator) as the clock signal of the system, this signal driving force is weaker, thus be separately added into clock driving 421, when
Clock driving 431, clock driving 441, give local oscillator phaselocked loop 422, local oscillator phaselocked loop 432, digital circuit clock by clock respectively
Shaping circuit 442.The generation system swept-frequency signal of phaselocked loop 422, is produced with radio-frequency input signals in the presence of frequency mixer 423
One intermediate-freuqncy signal, it is defeated that the signal that this first intermediate-freuqncy signal is produced with phaselocked loop 432 again produces intermediate frequency in the presence of frequency mixer 433
Go out, this IF signal frequency is relatively low, the present embodiment is 10.7MHz, in above-mentioned radio circuit, to clock request highest, system
The phase noise of clock 41 has been largely fixed the phase noise of whole system.Digital dock shaping circuit 442 is in this reality
It is low pass filter to apply in example, and clock is driven the clock higher hamonic wave of 441 outputs to filter out, made into fashionable by this shaping circuit 442
The signal of clock passage 443 is pure sine-wave clock signal.This sine-wave clock signal is transmitted in passage 443 and can't given
Other digital circuits bring interference, and other same numerical portion interference signals can also be filtered out by clock shaping circuit 442.
10MHz sine wave signals reach clock receiving circuit 444 by passage 443, and clock receiving circuit 444 has two effects, first
Serve as reflexless terminal, second this 10MHz sine wave is processed as in digital circuit acceptable clock signal, the present embodiment be
One or two frequency multiplier circuits, 20MHz square-like clock signals 2 are changed into by 10MHz sine waves, and this clock signal 2 then is delivered into data
Processing unit 446.
This data processing unit 446 is the FPGA for carrying phaselocked loop 445, so need to only set software parameters to can configure not
Exported with clock, such as peripheral hardware 447, be USB peripheral chip in the present embodiment, this USB chip needs 24MHz clocks, then configured
Clock signal 2 is output as 24MHz by FPGA phaselocked loops；It is network card chip, this network card chip in same peripheral hardware 448, the present embodiment
25MHz clocks are needed, FPGA phaselocked loops is then configured and clock signal 3 is output as 25MHz, this completes during whole system
The distribution of clock.
The design circuit of clock driving 421,431,441 and clock reception 444 is as shown in Fig. 5, Fig. 6, Fig. 7.
Circuit in Fig. 5 both can be as clock driver circuit, again can be as clock receiving circuit, in the present embodiment
U31B is about 4: 3 using device NL27WZ04, R32 and R31 ratio, and such direct current biasing is about in NOT gate U31B trigging signal
On, Vin31 only needs less amplitude that NOT gate U31B can be made to work, and is allowed to Vout31 output square waves.The alternative solution of this driving
NOT gate U41B is operated in profound and negative feedbck state, its gain is by R41 equivalent to a high-gain amplifier in also Fig. 6 and Fig. 7, Fig. 6
Determine；If circuit is sensitive to the switch higher hamonic wave of phase inverter, alternative solution Fig. 7 can also be used, this amplifier harmonic distortion is small,
General circuit driving requirement can be met.
What the clock signal that clock shaping 442 exports driving 441 was easy to transmit and designed, especially in spectrum analyzer
In, radio circuit all parts are sensitive to clock, especially each harmonic of clock, it is easy to enter frequency mixer 423 and mixing
Device 433 causes the output of spurious signal, so needing to be filtered clock signal clock shaping circuit in processing, the present embodiment
As shown in figure 8, being a 10MHz bandpass filters, L61, C63, C64 constitute LC shunt-resonant circuits, and resonance point is adjusted in 10MHz
Place, such Vout61 will export 10MHz sine waves, C63 and C64 parallel connections are to increase the Q values of whole resonant tank.Alternative
Case also has 10MHz low pass filters, as shown in Figure 9.
Transmission channel clock 443 can be PCB microstrip lines either coaxial cable.Can be with for the isolation clock of ground wire
Optocoupler transmission either magnetic coupling transmission is selected according to system requirements.
The embodiment of the present invention can not also realize same clock in digital circuit and radio circuit on same circuit board, only
Clock lane 443 in Fig. 4 need to be revised as coaxial cable, when frequency is higher or during longer cable, notes the matching of circuit.
Digital circuit and radio circuit in the present embodiment are to concentrate on same circuit board, although used same clock,
But digital circuit interference is still very big, RGB (RGB) data-signal on such as liquid crystal circuit, DDR SDRAM (Double
Data Rate SDRAM, Double Data Rate synchronous DRAM) data address signal, ADC (Analog-to-Digital
Converter, A/D converter) data-signal etc. is all huge interference source for radio circuit, so needing numeral
Circuit and radio circuit power supply are separated from each other, and ground wire is separated from each other, that is, is ceded territory.Although needs are ceded territory but and can not be completely numbers
Cut open with simulation word, also need to ensure, such as clock signal channel 443 signal path of digital circuit and radio circuit
Ground wire still complete will be remained.
In the case that the frequency of system clock 41 can not meet digital circuit work, in addition it is also necessary to which this system clock 41 is carried out
Appropriate processing.10MHz clocks can not meet the minimum clock request of processor in the present embodiment, and this is to need to carry out it again
Frequency is handled, and this process of frequency multiplication is placed on clock and received at 23, and circuit is that the embodiment of the present invention is carried out to clock signal as shown in Figure 10
The circuit design schematic diagram of process of frequency multiplication.Q81, R81, R82, L81, C81, C82 composition oscillator amplifier circuit in Figure 10, L81,
C81 and C82 composition 20MHz oscillator amplifier circuits, the 20MHz harmonic waves after the 10MHz sine waves amplification on Vin8 are taken out and given
The 20MHz bandpass filters being made up of C83, L82, C84, C85, C86, L83, C87, C88, the signal after resonance is amplified is again
Pure 20MHz signals are taken out in filtering, are finally handed over to the shaping circuit being made up of C89, R83, U81B, R84, Vout8 is defeated
Going out 20MHz square waves is supplied to digital processing unit to use, and this completes the reception of the frequency multiplication of clock signal.
The digital circuit that the embodiment of the present invention is solved in broad-band receiver field is integrated in same electricity with radio circuit
Interference problem and stationary problem that road plate is brought, and a clock also causes circuit design to greatly simplify, and saves cost.
Driven in whole spectrum analyzer using same clock, make system unit clock related, communicated between unit synchronous；And
FPGA (Field-Programmable Gate Array, field programmable gate in the data processing unit of frequency synthesis part
Array) PLL (Phase Locked Loop, phaselocked loop) that carries, resource is made full use of, cost is saved；Digiboard and rf board
Together in same plate, assembling and making sheet cost are reduced.Same clock signal causes whole system each clock related, so can be with
The spurious signal unrelated with input signal is removed by software processing.System is to be based on working under same clock in the present invention, no
Pipe is radio circuit interference in itself or the interference from digital circuit, and its effect is that have fixed spuious deposit during frequency spectrum is shown
, and this is spuious unrelated with input, it is possible to by software calibration technology by the spuious rejecting of this fixation, even in frequency spectrum
Analyzer is under outer synchronous regime, and this fixes and spuious still can effectively removed.Radio frequency clock signals quality is typically better than number
Word clock, so using whole system frequency resolution can be improved after same clock synchronization.
Those skilled in the art will also be appreciated that the various illustrative components, blocks that the embodiment of the present invention is listed
(illustrative logical block), unit, and step can be by the knots of electronic hardware, computer software, or both
Conjunction is realized.To clearly show that the replaceability (interchangeability) of hardware and software, above-mentioned various explanations
Property part (illustrative components), unit and step universally describe their function.Such work(
Can be that the design requirement depending on specific application and whole system is realized by hardware or software.Those skilled in the art
For every kind of specific application various methods can be used to realize described function, but this realization is understood not to
The scope protected beyond the embodiment of the present invention.
Various illustrative logical blocks described in the embodiment of the present invention, or unit can by general processor,
Digital signal processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic devices,
The design of discrete gate or transistor logic, discrete hardware components, or any of the above described combination is come the function described by realizing or operate.
General processor can be microprocessor, alternatively, the general processor can also for any traditional processor, controller,
Microcontroller or state machine.Processor can also be realized by the combination of computing device, for example digital signal processor and micro-
Processor, multi-microprocessor, one or more microprocessors combine a Digital Signal Processor Core, or any other like
Configuration realize.
The step of method described in the embodiment of the present invention or algorithm can be directly embedded into hardware, computing device it is soft
Part module or the combination of both.Software module can be stored in RAM memory, flash memory, ROM memory, EPROM storages
Other any form of storage media in device, eeprom memory, register, hard disk, moveable magnetic disc, CD-ROM or this area
In.Exemplarily, storage medium can be connected with processor, to allow processor to read information from storage medium, and
Write information can be deposited to storage medium.Alternatively, storage medium can also be integrated into processor.Processor and storage medium can
To be arranged in ASIC, ASIC can be arranged in user terminal.Alternatively, processor and storage medium can also be arranged at use
In different parts in the terminal of family.
In one or more exemplary designs, above-mentioned functions described by the embodiment of the present invention can be in hardware, soft
Part, firmware or any combination of this three are realized.If realized in software, these functions can be stored and computer-readable
On medium, or with it is one or more instruction or code form be transmitted on the medium of computer-readable.Computer readable medium includes electricity
Brain stores medium and is easy to so that allowing computer program to be transferred to other local telecommunication medias from a place.Storing medium can be with
It is that any general or special computer can be with the useable medium of access.For example, such computer readable media can include but
It is not limited to RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or other
What can be used for carrying or store with instruct or data structure and it is other can be by general or special computer or general or specially treated
Device reads the medium of the program code of form.In addition, any connection can be properly termed computer readable medium, example
Such as, if software is to pass through a coaxial cable, optical fiber computer, double from web-site, server or other remote resources
Twisted wire, Digital Subscriber Line (DSL) or with defined in being also contained in of the wireless way for transmitting such as infrared, wireless and microwave
In computer readable medium.Described disk (disk) and disk (disc) include Zip disk, radium-shine disk, CD, DVD, floppy disk
And Blu-ray Disc, disk is generally with magnetic duplication data, and disk generally carries out optical reproduction data with laser.Combinations of the above
It can also be included in computer readable medium.
Above-described embodiment, has been carried out further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc. all should be included
Within protection scope of the present invention.
Claims (13)
1. a kind of method for providing clock signal, methods described is applied to the presence of the same of radio circuit and digital circuit simultaneously
Device on circuit board, it is characterised in that methods described includes：
One system clock is provided；
Obtain the clock signal that the system clock is sent；
By multiple clock driver circuits, the clock signal is separated to the clock signal of multiple same frequencies；
The radio circuit that is sent to all the way of the clock signal is used, and another road of the clock signal is sent to
The digital circuit is used；
It is described another road of the clock signal is sent to the digital circuit to use, including：
Another clock signal separated is sequentially passed through after clock shaping circuit, transmission channel clock, clock receiving circuit, led to
Overfrequency synthesis is changed into the clock signal used for the unit of the digital circuit.
2. method as claimed in claim 1, it is characterised in that described that the clock signal is sent to the radio frequency electrical all the way
Road is used, including：
The clock signal of the multiple same frequencies separated is subjected to frequency synthesis through phaselocked loop and frequency mixer, obtains and supplies the radio circuit
The clock signal used.
3. method as claimed in claim 1, it is characterised in that described to be changed into by frequency synthesis for each of the digital circuit
The clock signal that individual unit is used, including：
The phase-locked loop pll carried using the on-site programmable gate array FPGA in the data processing unit of the digital circuit, is led to
Overfrequency synthesis is changed into the clock signal used for the unit of the digital circuit.
4. method as claimed in claim 1, it is characterised in that the clock shaping circuit passes through low pass filter or bandpass filtering
Device is realized.
5. method as claimed in claim 1, it is characterised in that when the radio circuit and the digital circuit are in same circuit
On plate simultaneously in the presence of, the transmission channel clock pass through printing board PCB microstrip line, or optocoupler transmission, or magnetic coupling transmission
Realize；In the presence of the radio circuit and the digital circuit be not on same circuit board simultaneously, the clock transfer is led to
Realized by coaxial cable in road.
6. method as claimed in claim 1, it is characterised in that the clock receiving circuit carries out frequency multiplication to the clock signal of process
Processing.
7. a kind of device for providing clock signal, is while there is radio circuit and the same circuit of digital circuit in described device
Device on plate, it is characterised in that described device only includes a system clock, for sending clock signal,
Described device also includes：Multiple clock driver circuits, the clock signal for the clock signal to be separated to multiple same frequencies；
The radio circuit that is sent to all the way of the clock signal is used, and another road of the clock signal is sent to
The digital circuit is used；
The digital circuit includes clock shaping circuit, transmission channel clock, clock receiving circuit, frequency synthesis unit, is used for
Another clock signal separated is sequentially passed through after clock shaping circuit, transmission channel clock, clock receiving circuit, passes through frequency
Rate synthesis unit is changed into the clock signal used for the unit of the digital circuit.
8. device as claimed in claim 7, it is characterised in that the radio circuit includes：
Phaselocked loop and frequency mixer, are closed for the clock signal of the multiple same frequencies separated to be entered into line frequency through phaselocked loop and frequency mixer
Into the clock signal that acquisition is used for the radio circuit.
9. device as claimed in claim 7, it is characterised in that the frequency synthesis unit, specifically for utilizing the numeral electricity
The phase-locked loop pll that on-site programmable gate array FPGA in the data processing unit on road is carried, confession is changed into by frequency synthesis
The clock signal that the unit of the digital circuit is used.
10. device as claimed in claim 7, it is characterised in that the clock shaping circuit is filtered by low pass filter or band logical
Ripple device is realized.
11. device as claimed in claim 7, it is characterised in that when the radio circuit and the digital circuit are in same electricity
On the plate of road simultaneously in the presence of, the transmission channel clock pass through printing board PCB microstrip line, or optocoupler transmission, or magnetic coupling pass
It is defeated to realize；In the presence of the radio circuit and the digital circuit be not on same circuit board simultaneously, the clock transfer
Passage is realized by coaxial cable.
12. device as claimed in claim 7, it is characterised in that the clock receiving circuit is carried out again to the clock signal of process
Frequency is handled.
13. a kind of spectrum analyzer, it is characterised in that the spectrum analyzer includes carrying any one of claim 7-12
For the device of clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110431634.9A CN103178836B (en) | 2011-12-21 | 2011-12-21 | A kind of method, device and spectrum analyzer that clock signal is provided |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110431634.9A CN103178836B (en) | 2011-12-21 | 2011-12-21 | A kind of method, device and spectrum analyzer that clock signal is provided |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103178836A CN103178836A (en) | 2013-06-26 |
| CN103178836B true CN103178836B (en) | 2017-08-25 |
Family
ID=48638485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110431634.9A Active CN103178836B (en) | 2011-12-21 | 2011-12-21 | A kind of method, device and spectrum analyzer that clock signal is provided |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103178836B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9590644B2 (en) * | 2015-02-06 | 2017-03-07 | Silicon Laboratories Inc. | Managing spurs in a radio frequency circuit |
| CN110224603A (en) * | 2019-05-24 | 2019-09-10 | 毫厘机电(苏州)有限公司 | A kind of PCB layout structure of Multiple isolated outputs driving power circuit and circuit |
| CN114115438B (en) * | 2020-08-31 | 2023-07-04 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN113612556B (en) * | 2021-07-28 | 2022-09-09 | 清华大学 | Integrated multi-node spectrum sensing method and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020097823A1 (en) * | 2001-01-25 | 2002-07-25 | Pioneer Corporation | Data reproduction apparatus |
| CN1613192A (en) * | 2002-01-11 | 2005-05-04 | 皇家飞利浦电子股份有限公司 | Method for providing clock signals to transceiver chip and transceiver chip |
| CN1649287A (en) * | 2005-03-18 | 2005-08-03 | 北京北方烽火科技有限公司 | Digital phase-lock method for clock signal in radio-frequency Layuan module |
| CN2927565Y (en) * | 2006-06-13 | 2007-07-25 | 普天信息技术研究院 | Subsystem of base station |
| CN102004622A (en) * | 2010-11-17 | 2011-04-06 | 广东威创视讯科技股份有限公司 | Multiprocessor display system and method |
-
2011
- 2011-12-21 CN CN201110431634.9A patent/CN103178836B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020097823A1 (en) * | 2001-01-25 | 2002-07-25 | Pioneer Corporation | Data reproduction apparatus |
| CN1613192A (en) * | 2002-01-11 | 2005-05-04 | 皇家飞利浦电子股份有限公司 | Method for providing clock signals to transceiver chip and transceiver chip |
| CN1649287A (en) * | 2005-03-18 | 2005-08-03 | 北京北方烽火科技有限公司 | Digital phase-lock method for clock signal in radio-frequency Layuan module |
| CN2927565Y (en) * | 2006-06-13 | 2007-07-25 | 普天信息技术研究院 | Subsystem of base station |
| CN102004622A (en) * | 2010-11-17 | 2011-04-06 | 广东威创视讯科技股份有限公司 | Multiprocessor display system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103178836A (en) | 2013-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104980156B (en) | High-speed ADC synchronous based on FPGA | |
| CN103178836B (en) | A kind of method, device and spectrum analyzer that clock signal is provided | |
| CN106374927A (en) | Multi-channel high-speed AD system based on FPGA and PowerPC | |
| CN108631809A (en) | A kind of multi-channel digital TR components | |
| CN103781085A (en) | Multi-frequency range TETRA digital cluster detection method and apparatus | |
| CN104115425B (en) | Crosstalk reduces technology | |
| CN104055516A (en) | Multichannel radio-frequency signal control system | |
| CN103762979B (en) | Broadband frequency source for LTE channel simulator | |
| CN102355281A (en) | Combinable frequency hopping wireless transmitting-receiving system and operation method thereof | |
| CN107239611A (en) | A kind of Vector Signal Analysis device and method | |
| CN209497453U (en) | A kind of linear frequency sweep local oscillator | |
| CN210351129U (en) | Dual-channel ADC/DAC board card based on FMC | |
| CN202663383U (en) | S-band coherence multi-frequency signal source | |
| CN106788808A (en) | A kind of radio signal quality detector and method | |
| CN110149122A (en) | A kind of the radio frequency self-interference compensation device and method of wide frequency coverage | |
| CN108021081A (en) | The playback test method controlled based on WLAN and sample time domain | |
| CN204669343U (en) | A kind of apparatus for frequency synthesizing of LTE air interface monitor | |
| CN103312324B (en) | The generation method and system of short-wave band signal | |
| CN209218046U (en) | A kind of up-converter module inhibiting intermodulation signal | |
| CN203368443U (en) | Generation system of short wave band signal | |
| CN104868928B (en) | A kind of frequency selective device and method based on WIA PA agreements | |
| CN202395753U (en) | 100MHz-850MHz broadband excitation signal source | |
| CN105262485B (en) | A kind of wideband generative circuit for radio general measuring instrument RF local oscillator circuit | |
| CN107872235B (en) | The method and apparatus for reducing signal interference in wireless lan communication lsi | |
| CN206178854U (en) | Multifrequency RFID recognition device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |